Fast wake-up circuit

Abstract

A fast wake-up circuit including an LDO, a switch, an operation circuit, and an output capacitor is provided. LDO receives an input voltage at a first node and outputs an output voltage to a second node. The switch is coupled between the second node and a third node. The operation circuit is coupled to the second node and operates according to the output voltage and a clock signal. The output capacitor is coupled between the third node and a ground. When the operation circuit enters an ultra-low power mode, the output voltage transits from a normal operating voltage to a threshold voltage, and the switch opens before the output voltage starts to drop. When the operation circuit leaves the ultra-low power mode, the output voltage transits from the threshold voltage to the normal operating voltage, and the switch closes after the output voltage reaches the normal operating voltage.

Description

Technical Field

[0001] This invention relates to a fast wake-up circuit, and more particularly to a fast wake-up circuit for a system in ultra-low power mode. Prior Technology

[0002] As the number of transistors in a chip increases, chip design progresses towards higher-order processes, leading to increased transistor leakage current and resulting in higher power consumption even during periods of inactivity. Therefore, some circuits reduce leakage current by lowering the operating voltage during inactivity periods. However, when the operating voltage needs to return to normal operating conditions, it must be adjusted back to its original level. The greater the voltage drop during inactivity, the longer the wake-up time. This not only makes the circuit wait longer to fully boot up but may also cause circuit errors due to delayed startup. Therefore, a new solution is needed to address these problems. Summary of the Invention

[0003] According to an embodiment of the present invention, a fast wake-up circuit is provided, including a low-dropout regulator, a switch, an operating circuit, and an output capacitor. The low-dropout regulator is configured to receive an input voltage from a first node and output an output voltage from a second node. The switch is coupled between the second node and a third node. The operating circuit is coupled to the second node and configured to operate according to a clock signal and the output voltage. The output capacitor is coupled between the third node and a ground terminal.

[0004] When the operating circuit enters an ultra-low power mode, the output voltage transitions from a normal operating voltage to a critical voltage. The low-dropout regulator switches to a non-operating mode under the control of a mode control signal. Furthermore, the switch is turned off under the control of a switch control signal before the output voltage transition begins, isolating the output capacitor and the operating circuit. Conversely, when the operating circuit exits the ultra-low power mode, the output voltage transitions from the critical voltage to the normal operating voltage. The low-dropout regulator switches to an operating mode under the control of a mode control signal. And the switch is turned on under the control of a switch control signal after the output voltage transitions to the normal operating voltage.

[0005] The operating circuit includes a first part performing a current operation and a second part performing operations other than the current operation. The operation of entering the ultra-low power mode includes: stopping the generation of a clock signal to disable the second part of the operating circuit according to an ultra-low power mode signal; after disabling the second part of the operating circuit, controlling the low-dropout regulator to enter a non-operating mode via a mode control signal; controlling the switch to open via a switch control signal according to the ultra-low power mode signal to isolate the output capacitor from the operating circuit; and after the switch is opened, causing the output voltage to switch to a threshold voltage. The clock signal controls the first part of the operating circuit to perform the current operation.

[0006] The operation of exiting the ultra-low power mode includes: switching the output voltage according to a wake-up signal and controlling the low-dropout regulator to enter the operating mode via a mode control signal; after the output voltage switches to the normal operating voltage, controlling the switch to turn on via a switch control signal to connect the output capacitor and the operating circuit; and after the switch is turned on and the low-dropout regulator enters the operating mode, generating a clock signal and activating the first part of the operating circuit. When the output capacitor and the operating circuit are connected, the voltage across the output capacitor remains at the normal operating voltage. The wake-up signal is provided by a circuit system that generates the input voltage. Simple Explanation of the Diagram

[0007] Figure 1 is an example of a low dropout regulator (LDO) according to an embodiment of the present invention. Figure 2 shows a fast wake-up circuit disclosed according to an embodiment of the present invention. Figure 3 is a timing diagram showing the operation of the fast wake-up circuit according to an embodiment of the present invention. Figure 4 illustrates a fast wake-up circuit disclosed in an embodiment of the present invention. Figure 5 illustrates a fast wake-up circuit disclosed according to an embodiment of the present invention. Figure 6 illustrates a fast wake-up circuit disclosed according to an embodiment of the present invention. Figure 7A is a flowchart of entering an ultra-low power mode as disclosed in an embodiment of the present invention. Figure 7B is a flowchart of leaving an ultra-low power mode as disclosed in an embodiment of the present invention. Implementation

[0008] To make the present invention and other objects, features, and advantages more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings:

[0009] The following outlines some embodiments to facilitate a better understanding of the embodiments of the present invention by those skilled in the art. However, these embodiments are merely exemplary and not intended to limit the scope of the present invention. It is understood that those skilled in the art can modify the embodiments described below as needed, such as changing the process sequence and / or including more or fewer steps than described herein, and these modifications do not exceed the scope of the embodiments of the present invention.

[0010] Figure 1 is an example of a low dropout regulator (LDO) circuit 10 according to an embodiment of the present invention. The LDO circuit 10 includes an LDO 12 and an output capacitor Cout, and may further include an input capacitor (not shown) to mitigate voltage fluctuations of an input voltage Vin. The LDO 12 includes an operational amplifier 15, a transistor M0, and voltage divider resistors R1 and R2. The first input terminal of the operational amplifier 15 is coupled to a reference voltage Vref, the second input terminal is coupled to a node N0, and the output terminal is coupled to the gate (or control terminal) of the transistor M0. The first terminal of the transistor M0 is coupled to the input voltage Vin, the second terminal is coupled to the output voltage Vout and the first terminal of the voltage divider resistor R2, and the second terminal of the voltage divider resistor R2 is coupled to node N0. The first terminal of the voltage divider resistor R1 is coupled to node N0, and the second terminal is coupled to a ground terminal. To maintain the stability of the output voltage Vout, the output capacitor Cout is coupled between the node providing the output voltage Vout and the ground terminal. By utilizing the large capacitance value of the output capacitor Cout, the output voltage Vout will not fluctuate drastically during the operation period, thereby achieving the effect of voltage stabilization.

[0011] The output capacitor Cout, with its large capacitance, can prevent fluctuations in the output voltage Vout caused by drastic current changes during circuit operation (such as rapid transitions between logic 0 and logic 1). However, when the circuit needs to return from an ultra-low-power mode close to the transistor's critical voltage to the normal operating voltage, the large capacitance of the output capacitor Cout can cause the current used to boost the output voltage Vout to be absorbed. This results in the output voltage Vout requiring more time to charge to the required voltage (such as voltage V1 in Figure 3), or requiring a larger charging current. Furthermore, the large current at the LDO 12's output may cause the input voltage Vin to drop. If the input voltage Vin drops below a minimum operating voltage (such as the minimum voltage required to maintain operation), it will cause circuit malfunctions. Therefore, the size of the output capacitor Cout must be limited to accelerate the voltage rise of the output voltage Vout and prevent excessive drops in the input voltage Vin that could lead to circuit errors.

[0012] Figure 2 illustrates a fast wake-up circuit 100 disclosed according to an embodiment of the present invention. The fast wake-up circuit 100 includes LDOs 110 and 120, an operation circuit 130, a switch SW, and an output capacitor Cout. LDO 110 may be LDO 12 as shown in Figure 1. Compared to LDO 110, LDO 120 has the characteristic of providing a stable output voltage Vout without requiring an output capacitor Cout, and LDOs with this characteristic are generally referred to as cap-less LDOs. Therefore, LDO 120 may have a lower output capacitance value (or an output capacitance value of 0) and lower circuit drive force (e.g., an output current value lower than that of a typical LDO). For example, in one embodiment, LDO 120 does not have an output capacitor Cout. In another embodiment, LDO 120 has a smaller output capacitance Cout than LDO 110. Furthermore, the operation and mode switching of the operation circuit 130 are controlled by a clock signal CLK.

[0013] When the operating circuit 130 is in normal operating mode (i.e., not in an ultra-low power mode where no operation is performed), a switch control signal S1 controls the switch SW to turn on, and according to a mode control signal MD, LDOs 110 and 120 are enabled and disabled, respectively. At this time, since switch SW is on and only LDO 110 is enabled, when the operating circuit 130 is operating, it can be considered that LDO 110 and output capacitor Cout constitute an LDO circuit for stabilizing the output voltage Vout. Therefore, when the operating circuit 130 is not in ultra-low power mode, the fast wake-up circuit 100 can be considered to provide the operating voltage (e.g., output voltage Vout) using the LDO circuit (LDO 110 plus output capacitor Cout).

[0014] Conversely, if the operating circuit 130 enters the ultra-low power mode, the switch control signal S1 controls the switch SW to open, and the mode control signal MD disables and enables LDOs 110 and 120, respectively. Since the switch SW is open, the connection between the output capacitor Cout and the operating circuit 130 is broken. At this time, if the operating circuit 130 needs to leave the ultra-low power mode and enter the normal operating mode, the current required to boost the operating voltage of the operating circuit 130 (e.g., the output voltage Vout) to the required voltage level will only be affected by the small capacitor of LDO 120 (or not by the capacitor at all). Therefore, compared to when the operating circuit 130 and the output capacitor Cout are connected, the output voltage Vout can be charged with a smaller current. Furthermore, because the current charging the output voltage Vout is smaller, the drop in the input voltage Vin is also reduced, preventing the circuit from malfunctioning due to the input voltage Vin dropping below the minimum operating voltage.

[0015] Figure 3 is a timing diagram illustrating the operation of the fast wake-up circuit 100 according to an embodiment of the present invention. Voltages V1, V2, and V3 represent the normal operating voltage, the minimum operating voltage (e.g., the voltage level that the clock signal CLK can normally generate), and the threshold voltage for the ultra-low power mode of the operating circuit 130, respectively. Referring to Figures 2 and 3, before a time t0, the operating circuit 130 is in normal operating mode (i.e., not in ultra-low power mode). Therefore, the switch control signal S1 with a logic high level (e.g., logic 1) keeps the switch SW on, while the mode control signal MD with a logic high level enables LDO 110 and disables LDO 120. At this time, assuming the fast wake-up circuit 100 receives an ultra-low power mode signal from another circuit or system (e.g., a processor or controller), it indicates that the operating circuit 130 is about to enter ultra-low power mode. Next, at time t0, which is when the operating circuit 130 is in normal operating mode, the last positive edge of the clock signal CLK (i.e., from logic 0 to logic 1) causes the switch control signal S1 to change from logic high level to logic low level, thus turning off the switch SW.

[0016] Since the output voltage Vout remains at the level of voltage V1 (i.e., the normal operating voltage) at this time, the output capacitor Cout, even after being disconnected from node N2, can still maintain a voltage equivalent to the voltage V1. Furthermore, the time when switch SW switches from on to off coincides with the last positive edge of the pulse signal CLK during operation of the operating circuit 130, indicating that the operation is about to end. Since the operating circuit 130 typically does not perform operations that could cause drastic current changes at this time, LDO 110 and / or LDO 120 no longer require output capacitor Cout for voltage regulation, thus isolating output capacitor Cout from the operating circuit 130 at time t0.

[0017] Next, at time t1, the mode control signal MD transitions from a logic high level to a logic low level, disabling LDO 110 and enabling LDO 120. Then, LDO 120 lowers the output voltage Vout from voltage V1 to voltage V3, providing a threshold voltage to the operating circuit 130 to minimize leakage current in ultra-low power mode. Therefore, at time t1, the operating circuit 130 enters ultra-low power mode and is powered only by LDO 120. It should be noted that although LDO 120 has a smaller output capacitance than the output capacitance Cout, the operating circuit 130 does not experience drastic current changes in ultra-low power mode, thus allowing for stable voltage supply from LDO 120. Furthermore, lowering the output voltage Vout to voltage V3 reduces power consumption caused by leakage current in the operating circuit 130, achieving power saving.

[0018] Next, at time t2, the fast wake-up circuit 100 receives a wake-up signal from another circuit or system (e.g., a circuit or system that can operate without the clock signal CLK), indicating that the operating circuit 130 is about to leave the ultra-low power mode and return to normal operation mode. For example, this wake-up signal can be provided by a circuit system that provides the input voltage Vin (or includes the fast wake-up circuit 100). However, since the output capacitance of LDO 120 is much smaller than the output capacitance Cout, it cannot fully absorb the current fluctuations caused by the operating circuit 130 returning to normal operation mode. Therefore, at time t2, the mode control signal MD transitions from a logic low level to a logic high level, enabling LDO 110 and disabling LDO 120. Meanwhile, since the switch SW remains open, the output capacitance Cout does not affect the LDO 110's rise in output voltage Vout from voltage V3 to voltage V1.

[0019] Next, at time t3, the switch control signal S1 changes from a logic low level to a logic high level, causing the switch SW to turn on. Simultaneously, since the output voltage Vout already has a voltage V1 higher than voltage V2, the clock signal CLK is generated, and the operating circuit 130 leaves the ultra-low power mode and enters the normal operating mode. At this time, the output capacitor Cout and node N2 (i.e., the operating circuit 130) are reconnected. When the switch SW is turned off at time t0, the output capacitor Cout maintains the voltage V1 before the output voltage Vout dropped. At time t3, the output voltage Vout has returned to voltage V1. Since the output capacitor Cout is coupled to the output voltage Vout with voltage V1 both before and after the switch SW is turned on, it is not necessary to recharge the output capacitor Cout after the operating circuit 130 returns to the normal operating mode.

[0020] By opening switch SW before the output voltage Vout drops from voltage V1 to voltage V3 at time t1, the fast wake-up circuit 100 maintains the voltage across the output capacitor Cout at voltage V1 during the ultra-low power mode. Furthermore, by raising the output voltage Vout from voltage V3 to voltage V1 before switch SW turns on at time t3, the fast wake-up circuit 100 avoids the input voltage Vin from dropping due to the large current used to charge the output voltage Vout. Moreover, since the voltage across the output capacitor Cout is always maintained at voltage V1, the fast wake-up circuit 100 saves the additional time required to charge the output capacitor Cout to voltage V1.

[0021] Figure 4 illustrates a fast wake-up circuit 400 disclosed according to an embodiment of the present invention. Similar to fast wake-up circuit 100, fast wake-up circuit 400 includes a switch SW, an output capacitor Cout, and an operation circuit 130. Compared to fast wake-up circuit 100, fast wake-up circuit 400 replaces LDOs 110 and 120 with an LDO 410. LDO 410 is configured to receive an input voltage Vin and output an output voltage Vout to the operation circuit 130. Furthermore, LDO 410 is further configured to perform mode switching according to a mode control signal MD.

[0022] For example, referring to Figure 3, when the mode control signal MD changes from a logic high level to a logic low level at time t1 (e.g., from logic 1 to logic 0), the LDO 410 correspondingly switches from an operating mode (e.g., performing a function similar to LDO 110) to a non-operating mode (e.g., performing a function similar to LDO 120), so that the LDO 410 has an output capacitance smaller than the output capacitance Cout, or does not need to have an output capacitance. Then, when the mode control signal MD changes from a logic low level to a logic high level at time t2 (e.g., from logic 0 to logic 1), the LDO 410 correspondingly switches from the non-operating mode to the operating mode.

[0023] Therefore, in non-operating mode, when the output voltage Vout rises from voltage V3 to voltage V1 at time t2, the LDO 410 can prevent the input voltage Vin from dropping excessively due to excessive current used to charge the output voltage Vout, thanks to the output capacitor being much smaller (or non-existent) than the output capacitor Cout. Furthermore, since the output capacitor Cout is isolated from the effects of voltage bucking or boosting of the output voltage Vout by the switch SW, the fast wake-up circuit 400 does not need to additionally charge the output capacitor Cout when the operating circuit 130 returns to normal operating mode, thus achieving power saving.

[0024] Figure 5 illustrates a fast wake-up circuit 500 disclosed according to an embodiment of the present invention. Similar to fast wake-up circuit 400, fast wake-up circuit 500 includes a switch SW, an output capacitor Cout2 similar to output capacitor Cout, and an operating circuit 130. Compared to fast wake-up circuit 400, fast wake-up circuit 500 replaces LDO 410 with LDO 510 and adds an output capacitor Cout1. The output capacitor Cout is coupled between node N2 and ground and is configured to buffer the instantaneous current caused by possible logic transient transitions (e.g., transitions between logic 0 and 1) in ultra-low power mode of operating circuit 130. The output capacitor Cout2 has a large capacitance value similar to that of output capacitor Cout, while the output capacitor Cout1 has a capacitance value much smaller than that of output capacitor Cout2.

[0025] For example, referring to Figure 3, when the mode control signal MD changes from a logic high level to a logic low level at time t1, the LDO 510 correspondingly switches from an operating mode (e.g., performing functions similar to LDO 110) to a non-operating mode (e.g., entering a low-power mode to reduce the output voltage Vout and the power consumption of the LDO 510 itself). At this time, the switch SW is open to isolate the output capacitor Cout2 from the operating circuit 130, thus the output capacitor Cout1 buffers the instantaneous current that may be caused by the operating circuit 130. Then, when the mode control signal MD changes from a logic low level to a logic high level at time t2, the LDO 510 correspondingly switches from the non-operating mode to the operating mode.

[0026] At this time, before switch SW is turned on at time t3, the output voltage Vout rises from voltage V3 to voltage V1. Only the output capacitor Cout1 with a low capacitance value needs to be considered. Therefore, by appropriately controlling the capacitance value of output capacitor Cout1, the fast wake-up circuit 500 can avoid the situation where the input voltage Vin drops excessively when the output voltage Vout rises from voltage V3 to voltage V1, which would cause circuit errors. In addition, since the output capacitor Cout1 has a low capacitance value, according to the following relationship: I (current) t (time difference) = Q (charge) = C (capacitance) V (voltage difference) It can be deduced that although the voltage across the output capacitor Cout1 drops to voltage V3 as the output voltage Vout decreases, the capacitance of the output capacitor Cout1 is very small. Therefore, even if the voltage rises from V3 to V1, a large current or a long charging time is not required. Thus, the fast wake-up circuit 500 avoids the input voltage Vin from dropping excessively due to the use of a large current to charge the output voltage Vout, thereby achieving a power-saving effect.

[0027] Figure 6 illustrates a fast wake-up circuit 600 disclosed according to an embodiment of the present invention, including an LDO 610 and an operation circuit 130. Compared to LDOs 410 and 510, LDO 610 has multiple switching modes. Furthermore, the fast wake-up circuit 600 includes X switches SW1, SW2, ..., SWX, and X corresponding output capacitors Cout1, Cout2, ..., CoutX. Switch SW1 is coupled between node N2 and node N3a, and output capacitor Cout1 is coupled between node N3a and ground. Switch SW2 is coupled between node N2 and node N3b, and output capacitor Cout2 is coupled between node N3b and ground. Switch SWX is coupled between node N2 and node N3x, and output capacitor CoutX is coupled between node N3x and ground, and so on. Switches SW1 to SWX are controlled by switch control signal S1, which activates the required number of switches according to the current operation of operating circuit 130. At the same time, mode control signal MD controls LDO 610 to enter the mode corresponding to the current operation of operating circuit 130 (e.g., the mode possessed by LDOs 110, 120, 410, and 510, or any mode required for the current operation of operating circuit 130).

[0028] Since the switch control signal S1 controls multiple switches (e.g., switches SW1 to SWX), it can be transformed from a signal carrying single transition information (e.g., the switch control signal S1 shown in Figure 3) to one carrying complex transition information (e.g., a signal including multiple logic 0s and logic 1s) to control the on or off states of switches SW1 to SWX. For example, in one embodiment, if the current operation of the operating circuit 130 causes a drastic current change, the switch control signal S1 controls multiple (or all) switches from SW1 to SWX to be turned on to buffer the current change and provide a stable output voltage Vout. Similarly, since the LDO 610 has two or more modes, the mode control signal MD can also be transformed to carry complex transition information to control the LDO 610 to switch between different modes.

[0029] In another embodiment, as the operating circuit 130 is about to enter the ultra-low power mode, the switch control signal S1 controls some (or all) of the switches SW1 to SWX to turn off, thereby isolating the output capacitors Cout1 to CoutX corresponding to the output voltage Vout at node N2. Next, the mode control signal MD controls the LDO 610 to switch to the non-operating mode corresponding to the ultra-low power mode, causing the output voltage Vout to drop from voltage V1 to voltage V3. Then, at time t2, the mode control signal MD controls the LDO 610 to switch to the operating mode to supply power to the operating circuit 130, which is about to enter the normal operating mode, and causes the output voltage Vout to rise from voltage V3 to voltage V1. Then, the switch control signal S1 controls the corresponding number of switches SW1 to SWX to turn on, connecting the corresponding number of output capacitors Cout1 to CoutX to the operating circuit 130 to provide a stable output voltage Vout.

[0030] Furthermore, in one embodiment, the operating circuit 130 is about to enter another low-power mode, but not an ultra-low-power mode. Therefore, compared to entering the ultra-low-power mode, the switch control signal S1 may need to keep a larger number of the output capacitors Cout1 to CoutX on to provide a stable output voltage Vout when the operating circuit 130 operates at a voltage V2 higher than voltage V3. Similarly, when the operating circuit 130 leaves this mode, since the output capacitor of the coupled node N2 is larger than in the ultra-low-power mode, a larger current is required to charge the output capacitors when raising the output voltage Vout to voltage V1. However, by appropriately controlling the number of switches turned on and the capacitance values ​​of the output capacitors Cout1 to CoutX, the LDO 610 can avoid an excessive drop in the input voltage Vin when charging the output voltage Vout. In addition, the design of multiple sets of switches and output capacitors (e.g., switch SW1 corresponds to output capacitor Cout1, and so on) allows the LDO 610 to switch to more operating modes corresponding to the operating circuit 130, and makes the fast wake-up circuit 600 more responsive to changes in different operating voltages.

[0031] Figure 7A is a flowchart 700a of entering an ultra-low power mode according to an embodiment of the present invention. The following description refers to the fast wake-up circuit 400 in Figure 4. In step 702, the fast wake-up circuit 400 receives an ultra-low power mode signal from an external source (e.g., a processor or controller) and disables the portion of the operation circuit 130 that does not require the clock signal CLK (i.e., the portion other than the current operation). Next, in step 704, the mode control signal MD changes from a high logic level to a low logic level (e.g., from logic 1 to logic 0), causing the LDO 410 to switch from the operating mode to the non-operating mode. Simultaneously, the switch control signal S1 controls the switch SW to disconnect the output capacitor Cout from the operation circuit 130. Then, in step 706, the output voltage Vout drops from voltage V1 to voltage V3. At this time, since the operating voltage of the operation circuit 130 drops to the critical voltage (i.e., voltage V3), the operation circuit 130 fully enters the ultra-low power mode, and the clock signal CLK stops.

[0032] Figure 7B is a flowchart 700b of leaving the ultra-low power mode disclosed according to an embodiment of the present invention. The following description refers to the fast wake-up circuit 400 in Figure 4. In step 708, the fast wake-up circuit 400 receives a wake-up signal from a circuit that can operate without the clock signal CLK and raises the output voltage Vout from voltage V3 to voltage V1. Next, in step 710, the mode control signal MD changes from a low logic level to a high logic level (e.g., from logic 0 to logic 1), causing the LDO 410 to switch from a non-operating mode to an operating mode. Simultaneously, the switch control signal S1 controls the switch SW to turn on, connecting the output capacitor Cout to the operating circuit 130. At this time, since the voltage across the output capacitor Cout is equivalent to voltage V1, it is no longer necessary to charge the output capacitor Cout. Then, in step 712, the operating circuit 130 enables the portion required for the current operation (i.e., the portion requiring the clock signal CLK to operate). At this time, the portion of the operation circuit 130 used for the current operation is enabled, so the operation circuit 130 completely leaves the ultra-low power mode.

[0033] This invention provides a fast wake-up circuit, including an LDO (or any voltage regulator), an operating circuit, a switch, and an output capacitor. The switch is coupled between the operating circuit and the output capacitor. The LDO is configured to power the operating circuit, which performs current operation based on a clock signal. When the fast wake-up circuit receives an ultra-low power mode signal, the non-current operation portion of the operating circuit (i.e., not requiring the clock signal) is disabled. Then, the LDO switches to a non-operating mode based on a mode control signal, and a switch control signal controls the switch to disconnect the operating circuit and the output capacitor. The LDO's output voltage then drops from the normal operating voltage (e.g., voltage V1) to a threshold voltage (e.g., voltage V3), causing the operating circuit to fully enter ultra-low power mode.

[0034] In another embodiment, when the fast wake-up circuit receives a wake-up signal, the output voltage of the LDO rises from a threshold voltage to the normal operating mode. Then, the LDO switches to the operating mode according to a mode control signal and turns on the switch via a switch control signal to connect the operating circuit and the output capacitor.

[0035] As described above, the output capacitor of the present invention is isolated from the operating circuit through a switch before the operating voltage of the operating circuit drops, so that the voltage across the output capacitor remains at the normal operating voltage during the period when the operating voltage drops. Furthermore, the operating voltage has already risen back to the normal operating voltage before the switch is turned on to connect the operating voltage and the output capacitor. Therefore, when the operating voltage rises rapidly, because the output capacitor is isolated by the switch, the current used to charge the operating voltage does not need to increase due to the large capacitance value of the output capacitor, thereby preventing the input voltage from dropping excessively due to excessive current and causing circuit errors. Moreover, since the voltage across the output capacitor is equivalent to the current operating voltage of the operating circuit when the output capacitor is reconnected, there is no need to charge the output capacitor additionally, thereby achieving the effects of saving power and charging time.

[0036] 10: Low Dropout Regulator (LDO) Circuit 12:LDO 15: Operational amplifier Vref: Reference voltage Vout: Output voltage Vin: Input voltage Cout, Cout1, Cout2, CoutX: Output capacitors M0: Transistor R1, R2: Voltage divider resistors 100, 400, 500, 600: Fast wake-up circuit 110, 120, 410, 510, 610: LDO 130: Operating Circuit SW, SW1, SW2, SWX: Switches N0, N1, N2, N3, N3a, N3b, N3x: Nodes S1: Switch control signal MD: Mode Control Signal V1, V2, V3: Voltage CLK: Clock signal t0, t1, t2, t3: Time 700a, 700b: Flowchart 702, 704, 706, 708, 710, 712: Steps

Claims

1. A fast wake-up circuit, comprising: A low-dropout regulator is configured to receive an input voltage from a first node and output an output voltage from a second node. A first switch is coupled between the second node and a third node; an operating circuit is coupled to the second node and configured to operate according to a clock signal and the output voltage; The circuit includes a first output capacitor coupled between the third node and a ground terminal. When the operating circuit enters an ultra-low power mode, the output voltage transitions from a normal operating voltage to a threshold voltage. The low-dropout regulator is controlled by a mode control signal to switch to a non-operating mode. The first switch is opened by a switch control signal before the output voltage transition begins, isolating the first output capacitor from the operating circuit. When the operating circuit leaves the ultra-low power mode, the output voltage transitions from the threshold voltage to the normal operating voltage. The low-dropout regulator is controlled by the mode control signal to switch to an operating mode. The first switch is turned on by the switch control signal after the output voltage transitions to the normal operating voltage. The mode control signal is generated by the operating circuit.

2. The fast wake-up circuit as described in claim 1, wherein the low-dropout regulator further comprises: A first low-dropout regulator is coupled between the first node and the second node; And a second low-dropout regulator coupled between the first node and the second node, wherein the output capacitance of the second low-dropout regulator is lower than that of the first output capacitance, or the second low-dropout regulator has no output capacitance; wherein in the non-operating mode, the mode control signal disables the first low-dropout regulator and enables the second low-dropout regulator; and wherein in the operating mode, the mode control signal enables the first low-dropout regulator and disables the second low-dropout regulator.

3. The fast wake-up circuit as described in claim 1, wherein in the non-operating mode, the low-dropout regulator is controlled by the mode control signal to switch to a low output capacitor mode to reduce the output voltage after the first output capacitor and the operating circuit are isolated.

4. The fast wake-up circuit as described in claim 1, further comprising: A second output capacitor is coupled between the second node and the ground terminal, wherein the capacitance value of the second output capacitor is lower than the capacitance value of the first output capacitor.

5. The fast wake-up circuit as described in claim 4, wherein in the non-operating mode, the low-dropout regulator is controlled by the mode control signal to switch to a low-power mode to reduce the output voltage after the first output capacitor and the operating circuit are isolated.

6. The fast wake-up circuit as described in claim 1, further comprising: A plurality of second switches and a plurality of third output capacitors, wherein the second switches and the corresponding third output capacitors are connected in series between the second node and the ground terminal.

7. The fast wake-up circuit as described in claim 6, wherein the low-dropout regulator is controlled by the mode control signal to switch to the operating mode corresponding to the current operation of one of the operating circuits.

8. The fast wake-up circuit as described in claim 1, wherein the operating circuit includes a first part performing a current operation and a second part performing an operation other than the current operation, and the operation of entering the ultra-low power mode includes: Based on an ultra-low power mode signal, the generation of the clock signal is stopped to disable the second part of the operating circuit; After the second part of the operating circuit is disabled, the low dropout regulator is controlled to enter the non-operating mode through the mode control signal; according to the ultra-low power mode signal, the first switch is controlled to open through the switch control signal so as to isolate the first output capacitor from the operating circuit. And after the first switch is turned off, the output voltage is switched to the threshold voltage, wherein the clock signal controls the first part of the operating circuit to perform the current operation.

9. The fast wake-up circuit as described in claim 8, wherein the operation of leaving the ultra-low power mode includes: The output voltage is converted according to a wake-up signal, and the low dropout regulator is controlled to enter the operating mode through the mode control signal; After the output voltage is switched to the normal operating voltage, the first switch is turned on by the switch control signal so that the first output capacitor is connected to the operating circuit. And after the first switch is turned on and the low-dropout regulator enters the operating mode, the first part of the operating circuit generates the clock signal and enables the operating circuit, wherein when the first output capacitor is connected to the operating circuit, the voltage across the first output capacitor is maintained at the normal operating voltage.

10. The fast wake-up circuit as described in claim 9, wherein the wake-up signal is provided by a circuit system that generates the input voltage.

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