Board card detection method

Abstract

A board card detection method, for detecting whether an to-be-detected board card inserted into a motherboard is a target support card, is implemented by a first control module and a clock generation unit mounted to the motherboard. The board card detection method includes: (A) the clock generation unit outputting a first clock signal, and the first control module outputting a second clock signal to a first input-output pin of the motherboard according to the first clock signal; (B) a plurality of identification pins of the motherboard respectively receiving a plurality of input signals, and the first control module being configured to receive a to-be-detected signal corresponding to the input signals; (C) the first control module determining whether the to-be-detected signal matches the first clock signal; (D) after determining that the to-be-detected signal matches the first clock signal, the first control module determining that the to-be-detected board card is the target support card and outputting an output signal.

Description

[Technical Field]

[0001] This invention relates to the field of server technology, and in particular to a board detection method. [Previous Technology]

[0002] Server systems typically include motherboards, connectors, and cards. Cards connect to the motherboard via connectors to communicate and operate with it. However, since both OCP NIC 3.0 and OCP DC-SCM compliant cards can connect to the 4C+ connector, when an OCP DC-SCM compliant card is inserted into the connector, even if the type of the OCP DC-SCM compliant card does not match the type of the 4C+ connector on the motherboard, the motherboard may still misidentify the OCP DC-SCM compliant card inserted into the 4C+ connector as the target card (OCP NIC 3.0). The motherboard will then begin to interact with the misidentified OCP DC-SCM compliant card using the communication and operation methods corresponding to the target card, causing motherboard malfunctions or providing high voltages that the OCP DC-SCM compliant card does not support to the OCP DC-SCM compliant card, resulting in the OCP DC-SCM compliant card burning out. [Summary of the Invention]

[0003] Therefore, the object of the present invention is to provide a board detection method that can overcome the shortcomings of the prior art.

[0004] The present invention provides a board detection method for detecting whether a board to be detected inserted into a motherboard is a target support card, and is implemented by a logic device disposed on the motherboard, the logic device including a first control module and a clock generation unit; the board detection method includes: (A) the clock generation unit outputs a first clock signal, and the first control module outputs a second clock signal to a first input / output pin of the motherboard according to the first clock signal; (B) a plurality of identification pins of the motherboard respectively receive a plurality of input signals, and the first control module receives a detection signal corresponding to the input signal; (C) the first control module determines whether the detection signal matches the second clock signal; (D) after determining that the detection signal matches the second clock signal, the first control module determines that the board to be detected is the target support card and outputs an output signal.

[0005] In some embodiments of the board detection method of the present invention, when the target support card is inserted into the motherboard, the first input / output pin and at least one of the identification pins are electrically connected.

[0006] In some embodiments of the board detection method of the present invention, the motherboard is further equipped with a switching device and provides a first power supply voltage, and the first control module includes a first detection circuit, a second detection circuit, and a first logic unit; wherein: in step (C), the first detection circuit is triggered by the positive edge of the first clock signal to sample the signal to be detected to a first logic value, and the second detection circuit is triggered by the negative edge of the first clock signal to sample the signal to be detected to a second logic value. When the sampling result of the first detection circuit meets the first logic value, a first signal is output as the first logic value; when the sampling result of the first detection circuit does not meet the first logic value, the first signal is output as the second logic value; when the sampling result of the second detection circuit meets the second logic value, a first signal is output as the second logic value. The two signals are the first logic value. When the sampling result of the second detection circuit does not conform to the second logic value, the output second signal is the second logic value. In step (D), the first logic unit receives the first signal output by the first detection circuit and the second signal output by the second detection circuit, and outputs the output signal to the switching device. When the first signal is at the first logic value and the second signal is at the first logic value, the switching device turns on the first power supply voltage to supply power to the board to be detected. The switching device includes a control terminal that receives the output signal, a first terminal that receives the first power supply voltage, and a second terminal that is electrically connected to a second input / output pin. When the first signal is at the first logic value and the second signal is at the first logic value, the first terminal and the second terminal are turned on, so that the first power supply voltage supplies power to the board to be detected.

[0007] In some embodiments of the board detection method of the present invention, the logic device further includes a plurality of second control modules for receiving the input signals and a detection module electrically connected to the second control modules; the board detection method further includes, after step (D): (E) for each input signal, the second control module performs a restoration process on the input signal to obtain a restored signal corresponding to the input signal; (F) the detection module determines the type of the target support card based on the restored signals.

[0008] In some embodiments of the board detection method of the present invention, each second control module includes a third detection circuit, a fourth detection circuit, and a second logic unit; wherein, step (E) includes the following sub-steps: (E-1): For each input signal, the third detection circuit samples the input signal for a first logic value based on the positive edge of the first clock signal, and the fourth detection circuit samples the input signal for a second logic value based on the negative edge of the first clock signal. When the sampling result of the third detection circuit matches the first logic value, The output third signal is the first logic value. When the sampling result of the third detection circuit does not conform to the first logic value, the output third signal is the second logic value. When the sampling result of the fourth detection circuit conforms to the second logic value, the output fourth signal is the first logic value. When the sampling result of the fourth detection circuit does not conform to the second logic value, the output fourth signal is the second logic value. (E-2): For each input signal, the second logic unit receives the third signal output by the third detection circuit and the fourth signal output by the fourth detection circuit and outputs the restored signal.

[0009] In some embodiments of the board detection method of the present invention, the method further includes the following steps before step (C): (G) The first control module determines whether the host board and the board to be detected are in a connected state based on the detection signal; (H) When the first control module determines that the host board and the board to be detected are in a connected state, step (C) is executed.

[0010] In some embodiments of the board detection method of the present invention, in step (G), when the first control module determines that the signal to be detected has a change in voltage level (logic value), it determines that the motherboard and the board to be detected are in a connected state.

[0011] The advantage of this invention lies in that: by using the first control module to determine whether the signal to be detected matches the first clock signal, it determines whether the card to be detected is the target support card, so that the motherboard controls the power supply voltage to supply power to or not supply power to the card to be detected according to the output signal. Further, when the card to be detected is determined to be the target support card, the detection module determines the type of the target support card. In addition, when the card to be detected is not the target support card, the warning device outputs an abnormal warning notification according to the output signal to remind the user to insert the wrong card. This improves the accuracy of the motherboard in determining whether the card to be detected installed on the motherboard is the target support card, preventing the motherboard from providing the first power supply voltage and communicating with the card when an incorrect card is inserted, thus avoiding server system failure or card burnout.

Implementation Method

[0012] Before the present invention is described in detail, it should be noted that similar elements are represented by the same numbers in the following description.

[0013] Referring to FIG1, a board detection system 100 of the present invention for performing a board detection method is shown in one embodiment. The board detection system 100 includes a motherboard 1, a connector 2, a board to be detected 3, and a power module 4. The board detection method is used to detect whether the board to be detected 3 inserted into the motherboard 1 is a target support card, and is implemented by a logic device installed on the motherboard 1. The logic device includes a first control module 11, a clock generation unit 12, a plurality of second control modules 19, a gate 8, and a detection module (not shown). In other embodiments, the logic device may be, for example, a central processing unit (CPU), a system-on-a-chip (SoC), a microprocessor (MCU), a field-programmable gate array (FPGA), or a complex programmable logic device (CPLD), and is not limited thereto.

[0014] In this embodiment, the motherboard 1 includes a first input / output pin 13, multiple identification pins 14, a second input / output pin 16, a switch device 17, an alarm device 18, and multiple pull-up resistors R electrically connected to the identification pins 14 respectively. It should be noted that although this embodiment only shows the first input / output pin 13, the identification pins 14, and the second input / output pin 16 in Figure 1, this is only to illustrate the principle of the board detection method of the present invention. In reality, the number of pins of the motherboard 1, connector 2, and the board 3 to be detected is not limited to this embodiment, and will not be elaborated here.

[0015] These identification pins 14 are used to transmit a plurality of input signals B to the gate 8. In this embodiment, the number of identification pins 14 is 4, but is not limited thereto. Therefore, the number of input signals B corresponds to the number of identification pins 14, and in this embodiment, the number of input signals B is also 4. For clarity, these identification pins 14 are respectively designated as a first identification pin (PRSNTB0#), a second identification pin (PRSNTB1#), a third identification pin (PRSNTB2#), and a fourth identification pin (PRSNTB3#).

[0016] The connector 2 is electrically connected to the motherboard 1, and may be, for example, a 4C+ connector 2 conforming to the SFF-TA-1002 standard. In this embodiment, the connector 2 includes a first pin PINA10 electrically connected to the first input / output pin 13, a second pin PINB42 electrically connected to the first identification pin (PRSNTB0#), a third pin PINA42 electrically connected to the second identification pin (PRSNTB1#), a fourth pin PINA12 electrically connected to the third identification pin (PRSNTB2#), and a fifth pin PINB70 electrically connected to the fourth identification pin (PRSNTB3#).

[0017] The board to be detected 3 is electrically connected to the connector 2. In this embodiment, the board to be detected 3 may be, for example, a network interface card of a Data Center-ready Secure Control Module (DC-SCM) 1.0, a network interface card of DC-SCM 2.0, or a network interface card (OCP NIC 3.0) conforming to the Open Compute Project (OCP) 3.0, and is not limited thereto.

[0018] In this embodiment, the target support card is, for example, a network interface card that supports the OCP NIC 3.0 specification. When the target support card is electrically connected to the connector 2 of the motherboard 1, a short circuit is formed between the first input / output pin 13 and at least one of the identification pins. Specifically, when the target support card is inserted into the motherboard 1, since the pin of the target support card corresponding to the first input / output pin 13 is electrically connected to at least one of the corresponding identification pins 14, the first pin is short-circuited through the target support card to at least one of the second, third, fourth, and fifth pins, and therefore a short circuit is also formed between the first input / output pin 13 and at least one of the identification pins 14. Conversely, when the target support card is inserted into the motherboard 1, the corresponding input signal B of the identification pin 14, which is not electrically connected to the first input / output pin 13, is affected by the pull-up resistor R, and presents and maintains a constant voltage representing a high voltage level of a first logic value.

[0019] It should be further noted that, in actual implementations, the short circuit between the first input / output pin 13 and the (etc.) identification pin 14 varies depending on the subtype (option) of the target support card. For example, if the target support card is a 2x8 Option B subtype of the OCP NIC 3.0 specification, then the first pin PINA10 is short-circuited with the third pin PINA42 through the target support card; if the target support card is a 1x16 Option D subtype of the OCP NIC 3.0 specification, then the first pin PINA10 is short-circuited with the second pin PINB42 and the third pin PINA42 through the target support card, but this is not a limitation.

[0020] On the other hand, when the DC-SCM1.0 board or the DC-SCM2.0 board is inserted into the connector 2 of the motherboard 1 designed to connect to the target support card, the fifth pin PINB70 of the connector 2 is electrically connected to a ground point on the DC-SCM1.0 board or the DC-SCM2.0 board. It should be noted that, for clarity in the following explanation, both the DC-SCM1.0 board and the DC-SCM2.0 board will be referred to herein as a non-target support card.

[0021] The power module 4 is electrically connected to the motherboard 1 and is used to provide power to the motherboard 1 and the detection board 3. In this embodiment, the power module 4 outputs a first power supply voltage V1 and a second power supply voltage V2, which are, for example, equal to 12 volts and 3.3 volts respectively, but are not limited thereto; they can also be 24 volts, 18 volts, or 5 volts, etc. However, in other embodiments, the first power supply voltage V1 and / or the second power supply voltage V2 can also be provided by an external power supply different from that of the power module 4. In this embodiment, the second power supply voltage V2 is used to provide power for the operation of the internal components of the logic device.

[0022] The clock generation unit 12 is coupled to the first input / output pin 13 and includes a delay unit (not shown). The clock generation unit 12 is used to generate a first clock signal CLK1 with one of a specific frequencies.

[0023] The clock generation unit 12 delays the first clock signal CLK1 using the delay unit to generate and output a second clock signal CLK2 to the first input / output pin 13. In this embodiment, the second clock signal CLK2 output by the clock generation unit 12 has the same period as the first clock signal CLK1, and the phase difference between them is 0 or 180 degrees. In other words, the clock generation unit 12 can directly output the first clock signal CLK1 to the first input / output pin 13. However, in other embodiments, the delay unit delays the first clock signal CLK1 by a delay time (e.g., 100 milliseconds). This delay time can be preset by the user, preset by the clock generation unit 12, or generated according to the period of the first clock signal CLK1, for example, N periods of the first clock signal CLK1, where 0 < N < 0.5.

[0024] The pull-up resistors R correspond to the identification pins 14 respectively. In this embodiment, each pull-up resistor R is electrically connected between the second power supply voltage V2 and the corresponding identification pin 14. Specifically, the pull-up resistor R includes a pull-up terminal and a contact terminal, the pull-up terminal receiving the second power supply voltage V2. In this embodiment, the contact terminal of the pull-up resistor R is electrically connected to the gate 8 and the identification pin 14. However, in other embodiments, the motherboard 1 includes only a single pull-up resistor R, the pull-up terminal of which receives the second power supply voltage V2, and the contact terminal of the pull-up resistor R is electrically connected to the clock generation unit 12 and the first input / output pin 13, without limitation. The following example illustrates that the contact terminal of each pull-up resistor R is electrically connected to the gate 8 and the corresponding identification pin 14.

[0025] The gate 8 is electrically connected to the identification pins 14. The gate 8 is used to receive the input signals B and generate and output a detection signal P to the first control module 11 accordingly. In this embodiment, when the detection board 3 is electrically connected to the connector 2, the first input / output pin 13 is short-circuited through the detection board 3 and at least one of the identification pins 14. In this case, the identification pin 14 that is short-circuited to the first input / output pin 13 will transmit the second clock signal CLK2 transmitted from the first input / output pin 13 to the detection board 3 as the corresponding input signal B to the gate 8.

[0026] The first control module 11 selectively controls the first power supply voltage V1 to supply power to the target board 3 through the second input / output pin 16 of the motherboard 1. The logic value of the first power supply voltage V1 corresponds to the first logic value (e.g., logic 1).

[0027] The first control module 11 is coupled to the clock generation unit 12 and receives the first clock signal CLK1 and the signal to be detected P to generate an output signal. The first control module 11 includes a first detection circuit 111, a second detection circuit 112, and a first logic unit 113. The first detection circuit 111 and the second detection circuit 112 sample the signal to be detected P according to the period of the first clock signal CLK1.

[0028] In this embodiment, the first logic unit 113 includes an AND gate for receiving a first signal from the first detection circuit 111 and a second signal from the second detection circuit 112 to generate the output signal. In other words, when the logic values ​​of the first signal and the second signal are both high voltage levels representing the first logic value (i.e., logic 1), the logic value of the output signal is also a high voltage level representing the first logic value (i.e., logic 1); when at least one of the logic values ​​of the first signal and the second signal is a low voltage level representing the second logic value (i.e., logic 0), the logic value of the output signal is also a low voltage level representing the second logic value (i.e., logic 0).

[0029] The second control modules 19 are respectively corresponding to the identification pins 14. Each second control module 19 is coupled to the corresponding identification pin 14 and the clock generation unit 12, and receives the first clock signal CLK1 and the input signal B to generate and output a restored signal. The second control module 19 includes a third detection circuit 191, a fourth detection circuit 192 and a second logic unit 193. The third detection circuit 191 and the fourth detection circuit 192 sample the input signal B according to the period of the first clock signal CLK1.

[0030] In this embodiment, the second logic unit 193 includes a NAND gate for receiving a third signal from the third detection circuit 191 and a fourth signal from the fourth detection circuit 192, and generating the restored signal accordingly. In other words, when the logic values ​​of the third signal and the fourth signal are equal to the first logic value (i.e., logic 1), the logic value of the restored signal is equal to the second logic value (i.e., logic 0); when at least one of the logic values ​​of the third signal and the fourth signal is equal to the second logic value (i.e., logic 0), the logic value of the restored signal is equal to the first logic value (i.e., logic 1).

[0031] The detection module is electrically connected to the second control module 19 for detecting the subtype of the target support card.

[0032] It should be further noted that the specific implementation of the first control module 11, the first detection circuit 111, the second detection circuit 112, the first logic unit 113, the clock generation unit 12, the second control module 19, the third detection circuit 191, the fourth detection circuit 192, the second logic unit 193, the gate 8, and the detection module can be physical circuits or functional modules operated by the firmware of the logic device, but are not limited thereto.

[0033] The switching device 17 includes a control terminal coupled to the first control module 11, a first terminal receiving the first power supply voltage V1, and a second terminal electrically connected to the second input / output pin 16.

[0034] In this embodiment, the board detection method includes a board detection program and a target support card subtype detection program. Specifically, in this embodiment, the board detection program can identify whether the board to be detected 3 is the target support card. If the board to be detected 3 is the target support card, the target support card subtype detection program can be further executed to identify the subtype of the target support card. However, if the board to be detected 3 is not the target support card, the target support card subtype detection program does not need to be executed. Therefore, in this case, the logic device only needs to run the first control module 11 and does not need to run the second control module 19 and the detection module.

[0035] Referring to Figures 1 and 2, the board detection procedure of the board detection method will be explained below.

[0036] First, as shown in step S11, the clock generation unit 12 generates and outputs the first clock signal CLK1, and the clock generation unit 12 generates and outputs the second clock signal CLK2 to the first input / output pin 13 of the motherboard 1 according to the first clock signal CLK1.

[0037] Next, as shown in step S12, the identification pins 14 respectively receive the input signals B, and the first control module 11 receives the detection signal P corresponding to the input signals B.

[0038] In this embodiment, after the motherboard 1 is powered and the voltage is stable, if the board to be detected 3 is not electrically connected to the connector 2 of the motherboard 1, the input signals B are affected by the pull-up resistor R and present a constant voltage representing a high voltage level of the first logic value 1. The gate 8 receives the input signals B that present a constant voltage level of the high voltage level and generates and transmits the detection signal P that presents a high voltage level representing the first logic value 1 to the first detection circuit 111 and the second detection circuit 112 of the first control module 11. The sampling target of the first detection circuit 111 is the first logic value (high voltage level), and the sampling target of the second detection circuit 112 is the second logic value (low voltage level). The first detection circuit 111 and the second detection circuit 112 of the first control module 11 sample the first logic value (high voltage level) and the second logic value (low voltage level) of the signal to be detected P according to the period of the first clock signal CLK1.

[0039] At this time, the first detection circuit 111 outputs a first signal representing a high voltage level of the first logic value to the first logic unit 113 based on the sampling result that matches its corresponding sampling target, i.e., matches the first logic value. The second detection circuit 112 outputs a second signal representing a low voltage level of the second logic value to the first logic unit 113 based on the sampling result that does not match its corresponding sampling target, i.e., does not match the second logic value. Therefore, the first logic unit 113 generates an output signal corresponding to a low voltage level of the second logic value to the switching device 17 based on the mismatched first and second signals, causing the switching device 17 to not conduct the first power supply voltage V1 and the second input / output pin 16. Thus, the motherboard 1 does not provide the first power supply voltage V1 to the board to be detected 3.

[0040] In another embodiment, the first detection circuit 111 and the second detection circuit 112 may also sample the signal to be detected P a preset number of times according to the period of the first clock signal CLK1, based on their respective sampling targets. When the sampling results are all the same and all meet their respective sampling targets, the first signal and the second signal, representing the high voltage level of the first logic value, are respectively output. Conversely, the first signal and the second signal, representing the second logic value (low voltage level), are respectively generated and output to the first logic unit 113. That is, when any of the continuous samplings of the signal to be detected P by the first detection circuit 111 and the second detection circuit 112 is different from the other samplings, or does not meet its corresponding sampling target, the first signal and the second signal, representing the low voltage level of the second logic value 0, are respectively output to the first logic unit 113.

[0041] Next, as shown in step S13, the first control module 11 determines whether there is a change in the voltage level of the signal to be detected P, for example, a change from the first logic value to the second logic value or a change from the second logic value to the first logic value, to determine whether the host board 1 and the board to be detected 3 are in a connected state. If the determination result is yes, the process proceeds to step S14; if the determination result is no, the process returns to step S13. In this embodiment, the first logic value corresponding to the high voltage level is equal to logic 1, and the second logic value corresponding to the low voltage level is equal to logic 0. In other embodiments, the first logic value and the second logic value may also be equal to logic 0 and logic 1, respectively.

[0042] Specifically, if the board to be detected 3 is a DC-SCM 1.0 board or a DC-SCM 2.0 board, and when the board to be detected 3 is electrically connected to the connector 2 of the motherboard 1, the fifth pin PINB70 of the connector 2 is electrically connected to the ground point, so that the logic value of the signal to be detected P is maintained at the second logic value (i.e., logic 0); on the other hand, if the board to be detected 3 is the target support card, the first input / output pin 13 is short-circuited between the target support card and at least one of the identification pins 14, so that the second clock signal CLK2 will be transmitted back to the motherboard 1 through the target support card and at least one of the identification pins 14, as the input signal B. Since at least one of the input signals B received by the gate 8 matches the second clock signal CLK2, the detection signal P generated and transmitted by the gate 8 based on the input signals B also matches the second clock signal CLK2. Therefore, when the detection board 3 is electrically connected to the motherboard 1 through the connector 2, the detection signal P experiences a change in voltage level.

[0043] Next, as shown in step S14, the first control module 11 determines whether the signal to be detected P matches the first clock signal CLK1. If the first control module 11 determines yes, the process proceeds to step S15; if the first control module 11 determines no, the process proceeds to step S16.

[0044] Specifically, in this embodiment, the first control module 11 determines that the signal to be detected P matches the first clock signal CLK1 by having the first detection circuit 111 sample the signal to be detected P for the first logic value based on the positive edge of the first clock signal CLK1, and having the second detection circuit 112 sample the signal to be detected P for the second logic value based on the negative edge of the first clock signal CLK1. When the sampling result of the first detection circuit 111 matches the first logic value, the output first signal is the first logic value; when the sampling result of the first detection circuit 111 does not match the first logic value, the output first signal is the second logic value. On the other hand, when the sampling result of the second detection circuit 112 matches the second logic value, the output second signal is the first logic value; when the sampling result of the second detection circuit 112 does not match the second logic value, the output second signal is the second logic value.

[0045] Next, as shown in step S15, the first control module 11 outputs the output signal with the logic value of the first logic value to the control terminal of the switching device 17, so that the first power supply voltage V1 supplies power to the board 3 to be detected through the second input / output pin 16.

[0046] Referring to Figure 3, in this embodiment, step S15 includes sub-steps S151 to S152.

[0047] In sub-step S151, the first detection circuit 111 outputs the first signal, the second detection circuit 112 outputs the second signal, and both the first signal and the second signal are the first logic value.

[0048] In sub-step S152, the first logic unit 113 outputs an output signal with the logic value of the first logic value to the control terminal of the switching device 17. When the output signal is at the first logic value, the first terminal and the second terminal are turned on, so that the first power supply voltage V1 supplies power to the board 3 to be detected through the second input / output pin 16.

[0049] Specifically, in this embodiment, when the target board 3 is electrically connected to the connector 2 of the motherboard 1, and the target board 3 is the target support card, at least one of the identification pins 14 of the motherboard 1 is electrically connected to the first input / output pin 13 through the target support card, thereby receiving the second clock signal CLK2 returned by the target support card, which is then used as the corresponding input signal B and transmitted to the gate 8. Since at least one of the input signals B received by the gate 8 matches the second clock signal CLK2, the target signal P generated and transmitted by the gate 8 based on the input signals B also matches the second clock signal CLK2. Therefore, when the first control module 11 detects a change in the voltage level of the signal to be detected P, it indicates that the board to be detected 3 is electrically connected to the connector 2 of the motherboard 1. This triggers the first detection circuit 111 and the second detection circuit 112 of the first control module 11 to sample the signal to be detected P according to the period of the first clock signal CLK1, based on their respective sampling targets. The sampling target of the first detection circuit 111 is a first logic value (high voltage level), and the sampling target of the second detection circuit 112 is a second logic value (low voltage level). Furthermore, when the board to be detected 3 electrically connected to the connector 2 is the target support card, the signal to be detected P matches the second clock signal CLK2, and therefore the period of the signal to be detected P is the same as that of the first clock signal CLK1.

[0050] At this time, the first detection circuit 111 and the second detection circuit 112 respectively output the first signal and the second signal, both representing a high voltage level of the first logic value 1, to the first logic unit 113. Thereby, the first logic unit 113 generates an output signal representing a high voltage level of the first logic value 1 to the switching device 17 based on the first and second signals, both representing the first logic value 1. The switching device 17 then turns on according to the output signal corresponding to the first logic value 1 and transmits the first power supply voltage V1 to the second input / output pin 16 to power the target support card.

[0051] Referring to Figure 7, when the target support card is not inserted into the connector 2 of the motherboard 1, The signal to be detected, P, presents a high voltage level representing the first logic value. After the first detection circuit 111 and the second detection circuit 112 sample the signal to be detected, P, the first detection circuit 111 outputs the first signal representing the high voltage level of the first logic value, and the second detection circuit 112 outputs the second signal representing the low voltage level of the second logic value. The first logic unit 113 correspondingly outputs the output signal representing the low voltage level of the second logic value to the switching device 17, causing the motherboard to cut off the first power supply voltage V1 to power the target board 3. When the target support card is inserted into the motherboard 1, the signal to be detected, P, conforms to the second clock signal CLK2. After the first detection circuit 111 and the second detection circuit 112 sample the signal to be detected, P, the first detection circuit 111 outputs the first signal representing the high voltage level of the first logic value, and the second detection circuit 112 outputs the second signal representing the high voltage level of the second logic value. The detection circuit 112 outputs a second signal representing a high voltage level of the first logic value. The first logic unit 113 correspondingly outputs the output signal representing a high voltage level of the first logic value to the switching device 17, so that the first power supply voltage V1 is turned on to supply power to the target board 3. When the target support card is removed from the motherboard 1, the target signal P returns to the high voltage level representing the first logic value. After the first detection circuit 111 and the second detection circuit 112 sample the target signal P respectively, the first detection circuit 111 outputs the first signal representing a high voltage level of the first logic value, the second detection circuit 112 outputs the second signal representing a low voltage level of the second logic value, and the first logic unit 113 correspondingly outputs the output signal representing a low voltage level of the second logic value to the switching device 17, so that the motherboard turns off the first power supply voltage V1 to supply power to the target board 3.

[0052] Next, as shown in step S16, the first control module 11 outputs the output signal with the logic value of the second logic value, and the switching device 17 cuts off the first power supply voltage V1 to supply power to the board 3 to be detected.

[0053] Referring to Figure 4, in this embodiment, step S16 includes sub-steps S161 to S162.

[0054] In sub-step S161, the first detection circuit 111 outputs the first signal, the second detection circuit 112 outputs the second signal, and the first signal or the second signal is the second logic value.

[0055] In sub-step S162, the first logic unit 113 outputs the output signal with the logic value of the second logic value, and the switching device 17 cuts off the first power supply voltage V1 to supply power to the board 3 to be detected.

[0056] Specifically, in this embodiment, when the card to be detected 3 is electrically connected to the connector 2 of the motherboard 1, and the card to be detected 3 is the non-target support card, since the fifth pin PINB70 of the connector 2 is electrically connected to the ground point, the input signal B corresponding to the fourth identification pin (PRSNTB3#) presents a low voltage level representing the second logic value and is transmitted to the gate 8. Therefore, the signal to be detected P generated and transmitted by the gate 8 based on the input signal B also presents a low voltage level. At this time, the first detection circuit 111 outputs the first signal representing the low voltage level of the second logic value to the first logic unit 113 based on the sampling result that does not conform to its corresponding sampling target, that is, does not conform to the first logic value, and the second detection circuit 112 outputs the second signal representing the high voltage level of the first logic value to the first logic unit 113 based on the sampling result that conforms to its corresponding sampling target, that is, conforms to the second logic value. Therefore, the first logic unit 113 generates a low-voltage level output signal corresponding to the second logic value to the switching device 17 based on the mismatched first and second signals, causing the switching device 17 to not conduct the first power supply voltage V1 and the second input / output pin 16. Consequently, the motherboard 1 does not provide the first power supply voltage V1 to the board to be detected 3.

[0057] Referring to Figure 8, when the non-target support card is not inserted into the motherboard 1, the signal to be detected P presents a high voltage level representing the first logic value. After the first detection circuit 111 and the second detection circuit 112 sample the signal to be detected P, the first detection circuit 111 outputs the first signal representing the high voltage level of the first logic value, and the second detection circuit 112 outputs the second signal representing the low voltage level of the second logic value. The first logic unit 113 correspondingly outputs the output signal representing the low voltage level of the second logic value to the switching device 17. When the non-target support card is inserted into the motherboard 1, the signal to be detected P presents a low voltage level representing the second logic value. After the first detection circuit 111 and the second detection circuit 112 sample the signal to be detected P, the first detection circuit 111 outputs the low voltage level representing the second logic value. The first signal at the voltage level, the second detection circuit 112 outputs the second signal at the high voltage level representing the first logic value, and the first logic unit 113 correspondingly outputs the output signal at the low voltage level representing the second logic value to the switching device 17, so that the motherboard cuts off the first power supply voltage V1 to supply power to the target card 3; when the non-target support card is removed from the motherboard 1, the target signal P returns to the high voltage level representing the first logic value. After the first detection circuit 111 and the second detection circuit 112 sample the target signal P respectively, the first detection circuit 111 outputs the first signal at the high voltage level representing the first logic value, the second detection circuit 112 outputs the second signal at the low voltage level representing the second logic value, and the first logic unit 113 correspondingly outputs the output signal at the low voltage level representing the second logic value to the switching device 17.

[0058] Next, as shown in step S17, the first logic unit 113 also outputs the output signal to the warning device 18, and the warning device 18 outputs an abnormal warning notification based on the output signal. The warning device 18 may be a speaker, an LED light, a display, or other type of warning device 18. When the output signal is output to the warning device 18, the voltage level of the output signal is pulled high from the second logic value to the first logic value, and the LED light will be lit to prompt the user to check and confirm.

[0059] Referring to Figures 5 and 6, the following describes the target support card type detection procedure of the board detection method.

[0060] As shown in step S21, for each input signal B, the second control module 19 performs a restoration process on the input signal B to obtain the restored signal corresponding to the input signal B.

[0061] In this embodiment, step S21 includes sub-steps S211 to S213.

[0062] In sub-step S211, for each input signal B, the third detection circuit 191 samples the first logic value of the input signal B based on the positive edge of the first clock signal CLK1, and the fourth detection circuit 192 samples the second logic value of the input signal B based on the negative edge of the first clock signal CLK1. That is, the sampling target of the third detection circuit 191 is the first logic value (high voltage level), and the sampling target of the fourth detection circuit 192 is the second logic value (low voltage level).

[0063] In sub-step S212, the third detection circuit 191 outputs the third signal, and the fourth detection circuit 192 outputs the fourth signal. When the sampling result of the third detection circuit 191 meets the first logic value, the output third signal is the first logic value. When the sampling result of the third detection circuit 191 does not meet the first logic value, the output third signal is the second logic value. When the sampling result of the fourth detection circuit 192 meets the second logic value, the output fourth signal is the first logic value. When the sampling result of the fourth detection circuit 192 does not meet the second logic value, the output fourth signal is the second logic value. In another embodiment, the third detection circuit 191 and the fourth detection circuit 192 may also sample the input signal B a preset number of times according to the period of the first clock signal CLK1 for their respective sampling targets. When the sampling results are all the same and all meet their respective sampling targets, the third signal and the fourth signal representing the high voltage level of the first logic value are output respectively. Otherwise, the third signal and the fourth signal representing the second logic value (low voltage level) are generated and output to the second logic unit 193 respectively.

[0064] In sub-step S213, for each input signal B, the reverse gate receives the third signal output by the third detection circuit 191 and the fourth signal output by the fourth detection circuit 192 and outputs the restoration signal.

[0065] Next, as shown in step S22, the detection module determines the type of the target support card based on the restored signals.

[0066] Referring to Figure 9, the target support card is a 1x16 Option D type board. When the target support card is not inserted into the motherboard 1, the input signal B of each identification pin 14 is maintained at the first logic value (i.e., logic 1). After the third detection circuit 191 and the fourth detection circuit 192 sample the input signal B three times respectively, the third signal corresponding to the input signal B becomes the second logic value, and the fourth signal becomes the first logic value.

[0067] When the target support card is inserted into the motherboard 1, the two input signals B corresponding to the first identification pin (PRSNTB0#) and the second identification pin (PRSNTB1#) both conform to the second clock signal CLK2, while the logic values ​​of the two input signals B corresponding to the third identification pin (PRSNTB2#) and the fourth identification pin (PRSNTB3#) remain at the first logic value (i.e., logic 1), until the third detection circuit 191 and the fourth detection circuit 192 are connected. After sampling the input signals B respectively, the third and fourth signals corresponding to the first identification pin are the first logic value, and the corresponding reverse gate receives the third and fourth signals and outputs the restored signal with the logic value of the second logic value (i.e., logic 0); the third and fourth signals corresponding to the second identification pin are the first logic value, and the corresponding reverse gate receives the third and fourth signals and outputs the restored signal with the logic value of the second logic value (i.e., logic 0).

[0068] On the other hand, the third signal corresponding to the three identification pins is the first logic value, the fourth signal corresponding to the three identification pins is the second logic value, and the corresponding reverse gate receives the third signal and the fourth signal and outputs the restored signal with the logic value of the first logic value (i.e., logic 1); the third signal corresponding to the four identification pins is the first logic value, the fourth signal corresponding to the four identification pins is the second logic value, and the corresponding reverse gate receives the third signal and the fourth signal and outputs the restored signal with the logic value of the first logic value (i.e., logic 1).

[0069] In this embodiment, the logic values ​​of the restored signals corresponding to the first identification pin (PRSNTB0#), the second identification pin (PRSNTB1#), the third identification pin (PRSNTB2#), and the fourth identification pin (PRSNTB3#) are 0, 0, 1, and 1, respectively. Therefore, the detection module determines that the target support card is a 1x16 Option D subtype card based on the logic values ​​of the restored signals. In other embodiments, if the logic values ​​of the restored signals corresponding to the first identification pin (PRSNTB0#), the second identification pin (PRSNTB1#), the third identification pin (PRSNTB2#), and the fourth identification pin (PRSNTB3#) are 1, 1, 0, and 0, respectively, the detection module determines that the target support card is a 4x4 subtype card based on the logic values ​​of the restored signals, and this is not a limitation.

[0070] Thereby performing the restoration process on the input signal of each identification pin 14 to obtain the restored signal with the logic value of the first logic value or the second logic value, so as to quickly determine the type of the target support card.

[0071] It should be understood that steps S11 to S17, steps S21 to S22, and the flowcharts of Figures 2 to 6 in this embodiment are merely illustrative examples of one possible implementation of the board detection method of the present invention. It should be understood that even if the foregoing steps are combined, split, or rearranged, if the resulting process achieves substantially the same effect in substantially the same manner as the embodiment in this patent specification, it still falls within the implementable state of the board detection method of the present invention. Therefore, steps S11 to S17, steps S21 to S22, and the flowcharts of Figures 2 to 6 in this embodiment are not intended to limit the scope of implementation of the present invention.

[0072] In summary, by implementing this board detection method, the first control module 11 can determine whether the detection signal P matches the second clock signal CLK2, thereby determining whether the board 3 to be detected is the target support card. This allows the motherboard 1 to control the power supply voltage to supply power to or de-supply the board 3 according to the output signal. Furthermore, if the board 3 is determined to be the target support card, the detection module determines the type of the target support card. Additionally, if the board 3 is not the target support card, the warning device 18 outputs an abnormal warning notification according to the output signal to remind the user to insert the wrong board. This improves the accuracy of the motherboard 1's determination of whether the board 3 installed on the motherboard 1 is the target support card, preventing the motherboard 1 from continuing to supply power when an incorrect board is inserted, which could cause server system failure or board burnout.

[0073] However, the above description is only an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the scope of the patent application and the contents of the patent specification shall still fall within the scope of the patent of the present invention. [Simplified Explanation of the Diagram]

[0074] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein: FIG1 is a block diagram illustrating, by way of example, a motherboard for performing one embodiment of a board detection method, and a board to be detected connected to the motherboard by a signal; FIG2 illustrates, by way of example, how the embodiment implements a board detection method and a board detection program; FIG3 and FIG4 are flowcharts illustrating, by way of example, the detailed flow of the execution of the board detection program in the embodiment; FIG5 is a flowchart illustrating, by way of example, how the embodiment implements a target support card type detection program of a board detection method; FIG6 is a flowchart illustrating, by way of example, the detailed flow of the execution of the target support card type detection program in the embodiment; FIG7 is a timing diagram illustrating, by way of example, the embodiment conducting a first power supply voltage when a target support card is inserted; Figure 8 is another timing diagram illustrating, by way of example, the first power supply voltage being cut off when a non-target support card is inserted in this embodiment; and Figure 9 is yet another timing diagram illustrating, by way of example, the type of the target support card being determined when the target support card is inserted in this embodiment.

Claims

1. A board detection method for detecting whether a board to be detected inserted into a connector on a motherboard is a target support card, and implemented by a logic device disposed on the motherboard, the logic device including a first control module, a clock generation unit, a plurality of second control modules, and a detection module electrically connected to the second control modules; the board detection method includes: (A) the clock generation unit outputs a first clock signal to the first control module and the second control modules, and the clock generation unit outputs a second clock signal to a first input / output pin of the motherboard according to the first clock signal; (B) the plurality of identification pins of the motherboard respectively receive a plurality of input signals from the connector, and the first control module receives a detection signal corresponding to the input signals; (C) the first control module determines whether the detection signal matches the first clock signal; (D) After determining that the signal to be detected matches the first clock signal, the first control module determines that the card to be detected is the target support card; (E) The second control modules respectively receive the input signals, and for each input signal, the second control module performs a restoration process on the input signal to obtain a restored signal corresponding to the input signal; and (F) The detection module determines the type of the target support card based on the restored signals.

2. The board detection method as described in claim 1, wherein, When the target support card is inserted into the motherboard, at least one of the first input / output pins and the identification pins is electrically connected.

3. The board detection method as described in claim 1, wherein the motherboard is further equipped with a switching device and provides a first power supply voltage, and the first control module includes a first detection circuit, a second detection circuit, and a first logic unit, wherein: In step (C), the first detection circuit samples the signal to be detected for a first logic value based on the positive edge of the first clock signal, and the second detection circuit samples the signal to be detected for a second logic value based on the negative edge of the first clock signal. When the sampling result of the first detection circuit matches the first logic value, a first signal is output as the first logic value; when the sampling result of the first detection circuit does not match the first logic value, the first signal is output as the second logic value. If the second logic value is met, the output second signal is the first logic value. If the sampling result of the second detection circuit does not meet the second logic value, the output second signal is the second logic value. In step (D), the first logic unit receives the first signal output by the first detection circuit and the second signal output by the second detection circuit, and outputs an output signal to the switching device. When the first signal is at the first logic value and the second signal is at the first logic value, the switching device turns on the first power supply voltage to power the board to be detected. The switching device includes a control terminal that receives the output signal, a first terminal that receives the first power supply voltage, and a second terminal that is electrically connected to a second input / output pin. When the first signal is at the first logic value and the second signal is at the first logic value, the first terminal and the second terminal are turned on, so that the first power supply voltage powers the board to be detected.

4. The board detection method as described in claim 1, wherein each second control module includes a third detection circuit, a fourth detection circuit, and a second logic unit; wherein, Step (E) includes the following sub-steps: (E-1): For each input signal, the third detection circuit samples the input signal for a first logic value based on the positive edge of the first clock signal, and the fourth detection circuit samples the input signal for a second logic value based on the negative edge of the first clock signal. When the sampling result of the third detection circuit matches the first logic value, a third signal is output as the first logic value. When the sampling result of the third detection circuit does not match the first logic value, the third signal is output as the second logic value. When the sampling result of the fourth detection circuit matches the second logic value, a fourth signal is output as the first logic value. When the sampling result of the fourth detection circuit does not match the second logic value, the fourth signal is output as the second logic value. (E-2): For each input signal, the second logic unit receives the third signal output by the third detection circuit and the fourth signal output by the fourth detection circuit and outputs the restored signal.

5. The board detection method as described in claim 1 further includes, prior to step (C): (G) the first control module determines whether the motherboard and the board to be detected are in a connected state based on the detection signal; (H) when the first control module determines that the motherboard and the board to be detected are in a connected state, step (C) is executed.

6. The board detection method as described in claim 5, wherein, In step (G), when the first control module determines that there is a change in the voltage level of the signal to be detected, it determines that the motherboard and the board to be detected are in a connected state.

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