Chip binning system and method
Patent Information
- Application Number
- TW114106773
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2026-09-01
- Estimated Expiration
- 2045-02-23
Smart Images
Figure TWG2TA001073914_001 
Figure TWG2TA001073914_002 
Figure TWG2TA001073914_003
Abstract
Description
[Technical Field]
[0001] This disclosure relates to a wafer cascading system and method, and more particularly to a wafer cascading system and method for multiple cascading operations. [Previous Technology]
[0002] When binning chips, clustering algorithms, such as K-means, are often used to group chips based on their feature data. This is achieved by minimizing the variation within a group. However, when processing chip feature data, it is difficult to effectively control and consider the impact of power variation. Furthermore, if all groups are assumed to be similar, it is easy to fail to distinguish subtle differences or anomalies between chips. Therefore, a chip binning method is needed to take into account the impact of chip power and other factors and to distinguish subtle differences in order to improve the performance and accuracy of chip binning. [Summary of the Invention]
[0003] This disclosure proposes a wafer binning system, comprising: a wafer analysis database and a wafer binning server. The wafer analysis database stores wafer analysis data corresponding to a plurality of wafers. The wafer binning server is communicatively connected to the wafer analysis database to receive the plurality of wafer analysis data. The wafer binning server includes a feature generation module, a first binning module, a second binning module, and a bin reduction module. The feature generation module generates corresponding wafer feature data based on the plurality of wafer analysis data. The first binning module generates corresponding wafer performance based on the corresponding plurality of wafer feature data, and performs a first binning of the plurality of wafers based on the wafer performance to generate first binning data. The second binning module performs a second binning of the plurality of wafers in each bin of the first binning data based on the corresponding wafer power in the plurality of wafer analysis data to generate second binning data. The box reduction module is used to reduce the number of boxes in the second box data to generate the third box data.
[0004] In one embodiment, the first binning module repeatedly bins a plurality of wafers that have not been binned by the first binning and the second binning.
[0005] In one embodiment, the wafer binning system further includes a binning analysis server, which is communicatively connected to the wafer binning server and is used to receive and establish a wafer binning model based on the third binning data and wafer analysis data corresponding to a plurality of wafers in the third binning data. The wafer binning model is used to bin another plurality of wafers, different from the plurality of wafers, according to the corresponding plurality of wafer analysis data and generate fourth binning data.
[0006] In one embodiment, the first binning is to bin a plurality of wafers with better performance in a preset ratio according to the performance of the corresponding plurality of wafers and generate the first binning data.
[0007] In one embodiment, the first binning is to select at least one binning center chip from the plurality of chips according to the performance of the corresponding plurality of chips, and to bin the plurality of chips and generate the first binning data according to whether the performance distance between the plurality of chips and the at least one binning center chip is less than a preset performance distance.
[0008] In one embodiment, the first binning module repeatedly bins a plurality of chips that have not been binned by the first binning and the second binning, and the preset performance distance in the repeated binning is larger than that in the previous binning.
[0009] In one embodiment, the power standard deviation of the plurality of chips in each bin in the second bin data generated by the second bin is less than or equal to a preset standard deviation.
[0010] This disclosure further proposes a wafer binning method, comprising: generating corresponding wafer feature data based on wafer analysis data corresponding to a plurality of wafers; generating corresponding wafer performance based on the corresponding wafer feature data; and binning the plurality of wafers into a first binning based on the wafer performance to generate first binning data; binning the plurality of wafers in each bin of the first binning data into a second binning based on the corresponding wafer power in the wafer analysis data to generate second binning data; and reducing the number of binning in the second binning data to generate third binning data.
[0011] In one embodiment, the wafer cascading method further includes: repeatedly cascading a plurality of wafers that have not been cascaded by the first cascading and the second cascading from the first cascading.
[0012] In one embodiment, the wafer binning method further includes: establishing a wafer binning model based on third binning data and wafer analysis data corresponding to a plurality of wafers in the third binning data; wherein the wafer binning model is used to bin another plurality of wafers different from the plurality of wafers according to the corresponding plurality of wafer analysis data and generate fourth binning data.
Implementation Method
[0013] The embodiments of this disclosure are discussed in detail below. However, it will be understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific situations. The embodiments discussed and disclosed are for illustrative purposes only and are not intended to limit the scope of this disclosure.
[0014] Figure 1 is a schematic diagram of a wafer binning system 100 according to an embodiment of the present disclosure. As shown in Figure 1, the wafer binning system 100 includes a wafer binning server 110, a binning analysis server 120, and a wafer analysis database 130 that are interconnected. The wafer binning server 110 includes a feature generation module 111, a first binning module 112, a second binning module 113, and a bin count reduction module 114. Figure 2 is a flowchart of a wafer binning method 200 according to an embodiment of the present disclosure. The operation of the wafer binning system 100 of the present disclosure will be described in detail below with reference to Figures 1 and 2.
[0015] First, the wafer sorting server 110 receives wafer analysis data from the wafer analysis database 130 and performs step S201, whereby the feature generation module 111 of the wafer sorting server 110 generates corresponding wafer feature data based on the wafer analysis data. The wafer analysis data may be one or more dimensions of data used or measured by the production line or wafer inspection unit and stored in the wafer analysis database 130. The feature generation module 111 then amplifies this wafer analysis data, calculating new wafer feature data corresponding to each wafer based on the correlation between different dimensions in the original wafer analysis data and their importance for wafer performance evaluation. After generating the new wafer feature data, the subsequent sorting process can be performed based on the wafer feature data.
[0016] In detail, the wafer analysis data may include manufacturing parameters, sensing parameters (such as preset and actual temperatures, production line speeds, etc.) corresponding to each wafer on the production line, and voltage, current, power, maximum frequency, speed, accuracy, etc., measured by the wafer probe on the wafer. Any parameter related to wafer production and / or wafer performance can be used as wafer analysis data and used for subsequent binning processes. This disclosure does not particularly limit this. In addition, in one embodiment, the wafer analysis data can be preprocessed before step S201, such as screening to remove outliers to make binning more accurate. Other data preprocessing can also be used. This disclosure does not particularly limit this.
[0017] After obtaining the chip feature data, step S202 is performed, in which the first binning module 112 generates the corresponding chip performance based on the corresponding chip feature data, so as to perform the first binning in the subsequent binning based on the corresponding chip performance of each chip. It is also possible to generate data other than chip performance based on other criteria to be used for binning, such as chip analysis data and / or chip feature data, and this disclosure does not particularly limit this.
[0018] The chip performance can be calculated from the chip feature data corresponding to each chip. For example, a performance analysis model can be used to comprehensively calculate the features of different dimensions in the chip feature data to assign an evaluation score or vector to each chip performance. Compared to directly using chip analysis data to obtain chip performance, the chip feature data obtained after step S201 can make the chip performance analysis and subsequent binning results closer to the quality target to be obtained in production. As long as the chip performance can be obtained from the chip analysis data and / or chip feature data, this disclosure does not particularly limit the specific types of chip analysis data, chip feature data, and algorithms or models used to calculate chip performance.
[0019] After obtaining the chip performance of each chip, step S203 is performed, in which the first binning module 112 performs the first binning, that is, binning the chips according to the chip performance corresponding to each chip. In one embodiment, the chips can be sorted according to their chip performance, and the chips with better performance and within a preset proportion, such as the chips whose chip performance is ranked in the top 5%, can be grouped into the same bin. In another embodiment, the chip performance distance of each chip can also be calculated, such as the difference between numerical values or the distance between vectors, to determine whether to group these chips into the same bin.
[0020] In detail, one or more representative chips can be selected from the chips based on their performance, such as those with better performance, as the center chip for binning. The performance of the center chip is used as the center to calculate the performance of other chips and their corresponding chip performance distances. A preset performance distance can be set, and chips whose performance distance from the center chip is less than the preset performance distance are grouped into the same bin. The preset performance distance can be estimated by referring to the preliminary binning results of other machine learning methods. As long as these chips can be reasonably classified according to their performance, this disclosure does not particularly limit the method of obtaining the preset chip distance.
[0021] In one embodiment, the first binning can first separate the chips with better performance within a preset proportion according to the chip performance ranking as described above, and then bin the remaining chips according to chip performance distance in the same manner as described above. For example, the top 5% of chips in the performance ranking are placed in the same bin, and the remaining 95% of chips are then selected from the bin center chips and binned according to chip performance distance. In step S204, the first binning module 112 performs step S205 to generate first binning data based on whether the chips have been binned or not, using the binning information corresponding to the binned chips (e.g., chip serial number and label indicating binning result). Among them, the chips that have not been binned, that is, those that cannot be assigned to a suitable bin in this first binning, will be binned again in step S203 along with the chips that have not been binned in other steps S207.
[0022] Next, after obtaining the first binning data, step S206 is performed, whereby the second binning module 113 performs a second binning of the chips in each bin of the first binning data. Since chip power has better distinguishability for chip binning and is more related to the final chip specifications, in one embodiment, the second binning is performed based on the chip power in the chip analysis data corresponding to the chip. However, any data or feature that can identify chip differences or specification requirements can be used as the basis for the second binning, and this disclosure does not particularly limit this.
[0023] The second binning is performed based on chip power. Specifically, the chips in each bin are divided into multiple segments according to their chip power, for example, into 100 or more segments, depending on the required level of precision. The segment containing the most chips is selected as a bin segment, and then the chip power corresponding to this bin segment is expanded outwards, for example, by increasing or decreasing the chip power corresponding to half or a whole segment, so that more chips are included in the bin segment. After each change in the chip power corresponding to the bin segment, the standard deviation of the chip power of the chips contained in the bin segment is calculated, and the bin segment expansion and power standard deviation calculation are repeated. When the power standard deviation is equal to or greater than a preset standard deviation, for example, the preset standard deviation is 0.25, it means that the second binning of this bin segment is completed, and the chips in the bin segment with the most chips and a power standard deviation equal to or less than the preset standard deviation are taken as the binning result of the second binning of this bin segment. In other words, each bin in the first binning data is subjected to second binning to obtain the second binning result of each bin segment.
[0024] Since the same standard deviation has different degrees of leniency or strictness for data with different dispersion, it is necessary to set a preset standard deviation according to the characteristics of the data. The preset standard deviation can be estimated by referring to the preliminary binning results of other clustering models. For example, the K-means algorithm can be used to perform preliminary binning of the chips to determine the preset standard deviation. As long as a reasonable chip power range for such chip binning can be obtained, this disclosure does not particularly limit the method of determining the preset standard deviation.
[0025] Next, step S207 is performed, where the second binning module 113, based on whether the chip was binned in step S206, uses the binning information corresponding to the binned chips (e.g., chip serial number and label indicating binning result) to perform step S208 to generate second binning data. Chips that were not binned, i.e., not covered in the final binning segment, will be binned again in step S203 along with the chips that were also not binned in the first binning. Both the first and second binning data can be stored in the chip analysis database 130 for future analysis.
[0026] After steps S203-S208, the second binning data contains binning information for the binned chips. Chips not binned in steps S204 and S207 are binned again, and the first and second binning processes are repeated starting from step S203. In the repeated binning stage, chips can be binned directly based on their performance distance. Furthermore, the preset performance distance for the first binning can be increased compared to the previous binning. This means that the conditions for grouping chips into the same bin in the first binning of the repeated binning are more lenient than in the previous binning, allowing the remaining chips to be successfully binned and reducing the number of unbinded chips. In one embodiment, the preset standard deviation in the second binning can also be increased to increase the number of chips in the same bin. Moreover, the leniency of the first and second binning in the repeated binning stage can be adjusted according to the number or proportion of chips to be retained and discarded; this disclosure does not impose any particular limitations on this.
[0027] After the second binning is completed, the number of bins obtained after the second binning may be large because all the chips in the first binning and the second binning are binned as much as possible. Therefore, in one embodiment, after obtaining the second binning data, step S209 can be continued, in which the bin number reduction module 114 reduces the number of chips in the second binning data.
[0028] In detail, the number of bins in the second bin data can be reduced using an unsupervised learning algorithm, such as the K-means algorithm, based on corresponding chip performance and power analysis data and / or chip characteristic data, to meet a preset number of bins, such as the number of bins required by the customer. Specifically, for example, the top five bins with the best average chip performance can be merged into one bin, and the next best five bins can be merged into one bin. As long as the number of bins can be reduced, the number of bins can also be reduced based on, for example, the maximum power of the chip, the average chip performance, or the cumulative chip performance. This disclosure does not impose any particular restrictions on the reduction method, the number of bins reduced, or the chip analysis data or chip characteristic data on which the reduction is based.
[0029] After the bin reduction module 114 reduces the number of chips in the second binning data, step S210 is performed to generate the third binning data. The third binning data includes binning information corresponding to the binned chips (e.g., chip serial number and labels indicating the binning result), and the number of bins in the third binning data is less than that in the first and second binning data. Furthermore, the third binning data can also be stored in the chip analysis database 130 for future analysis needs.
[0030] Figure 3 is a schematic diagram comparing the binning performance of wafer binning method 200 and K-average algorithm in one embodiment of this disclosure. Here, taking 30 bins as an example, the solid line L1 represents the cumulative binning performance under multiple simulations of binning the wafer into 30 bins using steps S201-S210 of wafer binning method 200, i.e., reducing the number of bins and dividing it into 30 bins. The dashed line L2 represents the binning performance under multiple simulations of binning the wafer into 30 bins directly based on wafer analysis data using the K-average algorithm based on wafer performance data and wafer power. As shown in Figure 3, the binning performance of wafer binning method 200 is better as the number of simulations increases. Furthermore, the number of bins applicable to the wafer binning method 200 of this disclosure is not limited to this; that is, wafer binning method 200 can achieve better binning performance than the K-average algorithm under different numbers of bins.
[0031] In addition, in one embodiment, since each batch of wafers may have the same binning requirement during multiple production runs, in order to accelerate the binning efficiency, the third binning data and the corresponding wafer analysis data and / or wafer feature data of the included wafers, as well as the labels of the binning results, can be analyzed to obtain a binning policy, which can be applied to subsequent batches of wafers for rapid binning. Therefore, as shown in FIG2, step S211 can be continued, whereby the binning analysis server 120 directly obtains the third binning data and the corresponding wafer analysis data and / or wafer feature data from the wafer binning server 110 or the wafer analysis database 130, and then uses a supervised learning model, such as random forest, support vector machine, or neural network, to find the binning policy hidden in the third binning data and establish a wafer binning model. The trained wafer binning model can then be used to rapidly bin the wafers in subsequent batches. Specifically, the chip binning model can be used to quickly bin the chips in subsequent batches to generate fourth binning data. That is, the fourth binning data will contain the correspondence between each chip in this batch and each bin in the third binning data, thereby obtaining which bins in the corresponding third binning data each chip can be binned into, and labeling each chip in this batch with the corresponding bin number.
[0032] The wafer binning system and method disclosed herein screens wafer analysis data and adds wafer feature data for binning by data amplification. Then, the first binning and the second binning perform two-stage binning based on wafer performance and wafer power, ultimately reducing the number of bins to make the binning results more refined and meet the binning quantity requirements. Compared with using only clustering algorithms such as K-means algorithm, it can fully consider the influence of wafer power and distinguish wafers with slight differences to obtain more accurate binning results.
[0033] Although this disclosure has been disclosed above with reference to embodiments, it is not intended to limit this disclosure. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims. [Simplified Explanation of the Diagram]
[0034] To gain a more complete understanding of the embodiments and their advantages, the following description is now made in conjunction with the accompanying drawings, in which: Figure 1 is a schematic diagram of a wafer binning system according to an embodiment of the present disclosure; Figure 2 is a flowchart of a wafer binning method according to an embodiment of the present disclosure; and Figure 3 is a schematic diagram comparing the binning performance of the wafer binning method and the K-average algorithm according to an embodiment of the present disclosure.
Claims
1. A wafer binning system, comprising: a wafer analysis database for storing a plurality of wafer analysis data corresponding to a plurality of wafers; and a wafer binning server communicatively connected to the wafer analysis database to receive the plurality of wafer analysis data, the wafer binning server comprising: a feature generation module for generating a plurality of corresponding wafer feature data based on the plurality of wafer analysis data; a first binning module for generating a plurality of corresponding wafer performance based on the corresponding plurality of wafer feature data, and performing a first binning on the plurality of wafers based on the plurality of wafer performance to generate a first binning data; a second binning module for performing a second binning on the plurality of wafers in each bin of the first binning data based on the power of the plurality of wafers corresponding to the plurality of wafers in the plurality of wafer analysis data to generate a second binning data; and a binning reduction module for reducing the number of bins in the second binning data to generate a third binning data.
2. The wafer cascading system as described in claim 1, wherein the first cascading module performs a repetitive cascading of the plurality of wafers that have not been cascaded by the first cascading and the second cascading.
3. The wafer binning system as described in claim 1 further comprises: a binning analysis server, communicatively connected to the wafer binning server, the binning analysis server being configured to receive and establish a wafer binning model based on the third binning data and the wafer analysis data corresponding to the plurality of wafers in the third binning data; wherein the wafer binning model is configured to bin another plurality of wafers different from the plurality of wafers according to the corresponding plurality of wafer analysis data and generate a fourth binning data.
4. The wafer binning system as described in claim 1, wherein the first binning is generated by binning the plurality of wafers with the best performance of one of the plurality of wafers according to the corresponding performance of the plurality of wafers and generating the first binning data.
5. The wafer binning system as described in claim 1, wherein the first binning is performed by selecting at least one binning center wafer from the plurality of wafers based on the performance of the corresponding plurality of wafers, and binning the plurality of wafers and generating the first binning data based on whether the performance distance between the plurality of wafers and the at least one binning center wafer is less than a preset performance distance.
6. The wafer binning system as described in claim 5, wherein the first binning module performs a repetitive binning of the plurality of wafers that have not been binned by the first binning and the second binning, and the preset performance distance in the repetitive binning is larger than that in the previous binning.
7. The wafer binning system as described in claim 1, wherein the power standard deviation of one of the plurality of wafers in the second binning data generated by the second binning is less than or equal to a preset standard deviation.
8. A wafer binning method, comprising: generating corresponding plurality of wafer feature data based on plurality of wafer analysis data corresponding to a plurality of wafers; generating corresponding plurality of wafer performance based on the corresponding plurality of wafer feature data, and performing a first binning on the plurality of wafers based on the plurality of wafer performance to generate a first binning data; performing a second binning on the plurality of wafers in each bin of the first binning data based on the corresponding plurality of wafer power in the plurality of wafer analysis data to generate a second binning data; and reducing the number of bins in the second binning data to generate a third binning data.
9. The wafer cascading method as described in claim 8 further comprises: performing a duplicate cascading of the plurality of wafers that have not been cascaded by the first cascade and the second cascade from the first cascade.
10. The wafer binning method as described in claim 8 further comprises: establishing a wafer binning model based on the third binning data and the wafer analysis data corresponding to the plurality of wafers in the third binning data; wherein the wafer binning model is used to bin another plurality of wafers different from the plurality of wafers according to the corresponding plurality of wafer analysis data and generate a fourth binning data.