Anti-attack circuit system

Abstract

An anti-attack circuit system including a power supply, an operation switch, current sources, control switches, a control loop, and a neural-network processing unit (NPU) is provided. The power supply outputs an output voltage at a first node. The operation switch is coupled between the first node and a second node. The current sources are coupled to the second node through the corresponding control switches. The control loop controls the operation switch to open or close based on an operation voltage, a target voltage, and a control voltage. The control loop changes the operation voltage by controlling the current sources and the control switches. The NPU is coupled to the second node. In response to the operation switch being opened, the NPU is supplied by at least one of the current sources.

Description

Technical Field

[0001] This invention relates to anti-attack circuitry systems, and more particularly to anti-attack circuitry systems for protecting neural network processing units (NPUs). Prior Technology

[0002] Power supply bypass attacks are a common type of circuit attack. This method involves exploiting the timing information, power consumption, and electromagnetic field changes specific to the operating circuitry reflected at the power supply. Generally, protection circuits are added to prevent information and data leakage via bypass attacks. However, the information and data requiring protection may only be available for a portion of the operating circuit's time; if the protection circuit remains active for extended periods, it may consume more power. Therefore, a solution is needed to address the problems described above. Summary of the Invention

[0003] According to some embodiments of the present invention, an anti-attack circuit system is provided, including a power supply, an operating switch, multiple current sources, multiple control switches, a control loop, and a neural network processor. The power supply is configured to output an output voltage at a first node. The operating switch is configured to be coupled between the first node and a second node. The current sources are coupled to the second node through corresponding control switches. The control loop is configured to control the operating switch to be turned on or off according to an operating voltage, a target voltage, and a control voltage, and to control the current sources and control switches to change the operating voltage. The neural network processor is configured to be coupled to the second node, wherein in response to the operating switch being turned off, the neural network processor is powered by at least one of the current sources.

[0004] The control loop generates a first control signal and a second control signal based on the operating voltage, target voltage, and control voltage. In response to the neural network processor operating according to the operating voltage, a start signal is set to a first logic level. In response to the first control signal, second control signal, and start signal having the first logic level, the operation switch is turned on.

[0005] According to some embodiments of the present invention, the control loop includes a first comparator, a second comparator, a counter, and a logic circuit. The first comparator is configured to compare an operating voltage and a first comparison voltage to generate a first control signal. The second comparator is configured to compare the operating voltage and a second comparison voltage to generate a second control signal. The counter is configured to increase or decrease a count value according to the first and second control signals, and generate a corresponding third control signal based on the count value. The logic circuit is configured to drive the counter according to a clock signal to increase or decrease the count value. The third control signal adjusts the number of switches turned on in the control switch in response to the operating voltage being greater than the first comparison voltage or less than the second comparison voltage.

[0006] Specifically, when the operating voltage is between the first comparison voltage and the second comparison voltage, the control loop keeps the number of switches in the control switch that are turned on unchanged and controls the operating switch to be turned off. When the operating voltage is greater than the first comparison voltage, the control loop reduces the number of switches in the control switch that are turned on and controls the operating switch to be turned on. When the operating voltage is less than the second comparison voltage, the control loop increases the number of switches in the control switch that are turned on and controls the operating switch to be turned on. Simple Explanation of the Diagram

[0007] Figure 1 is a schematic diagram of an anti-attack circuit system according to an embodiment of the present invention. Figure 2 is a partial schematic diagram of an anti-attack circuit system according to an embodiment of the present invention. Figure 3 is a flowchart illustrating the operation of a control loop according to an embodiment of the present invention. Figure 4 is a timing diagram showing the operation of an operating circuit according to an embodiment of the present invention. Implementation

[0008] To make the above and other objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings:

[0009] The following outlines some embodiments to facilitate a better understanding of the embodiments of the present invention by those skilled in the art. However, these embodiments are merely exemplary and not intended to limit the scope of the present invention. It is understood that those skilled in the art can modify the embodiments described below as needed, such as changing the process sequence and / or including more or fewer steps than described herein, and these modifications do not exceed the scope of the embodiments of the present invention.

[0010] Figure 1 is a schematic diagram of an anti-attack circuit system 100 according to an embodiment of the present invention. The anti-attack circuit system 100 includes a power supply 110, a control loop 120, multiple current supply units 130, multiple switching units 140, an operating circuit 150, and an operating switch SW1. The current supply units 130 include current sources I1, I2, ... In, while the switching units 140 include control switches S1, S2, ... Sn. Referring to Figure 1, the power supply 110 provides an output voltage VLDO at a node N1 to provide the voltage required by the operating circuit 150 during normal operation. The control loop 120 is configured to output control signals OUT1, OUT2, and SC to control the operation switch SW1 to be turned on or off, and to control the number of switches turned on in the switching units 140. The current supply units 130 are coupled to a node N2 through the switching units 140 to provide an operating voltage VDIG at node N2.

[0011] When the operating circuit 150 performs operations requiring protection (e.g., training or computing artificial intelligence (AI) models as a neural network processing unit (NPU), a start signal ST is set to a logic high level and output to the operating switch SW1. The control loop 120 outputs control signals OUT1 and OUT2 to the operating switch SW1 and a control signal SC to the switch unit 140, thereby controlling the operating switch SW1 to open and turning on one or more of the control switches S1, S2, ... Sn. When the operating circuit 150 performs normal operations (e.g., ordinary operating procedures or calculations) without requiring special protection, the start signal ST is set to a logic low level. Simultaneously, since the operating circuit 150 no longer needs protection, the control loop 120 is deactivated, causing the control signals OUT1 and OUT2 to change from a logic high level (e.g., logic 1) to a logic low level (e.g., logic 0) (or stopping the output of control signals OUT1 and OUT2). Therefore, the operation switch SW1 is turned on, the switching unit 140 is turned off, and the operation circuit 150 is powered by the output voltage VLDO. The start signal ST can also be generated by a central processing unit (not shown) controlling the operation circuit (or NPU) 150.

[0012] Referring to Figure 1, power supply 110 is described as a low dropout regulator (LDO) including a transistor ML, an operational amplifier 115, and a resistor RL. The source terminal of transistor ML receives a supply voltage VDD, the drain terminal is coupled to node N1, and the gate terminal is coupled to the output of operational amplifier 115. Operational amplifier 115 has a first input and a second input (denoted as "+" and "-"), wherein the first input is coupled to node N1, and the second input receives a reference voltage VREF. Resistor RL is coupled between node N1 and ground. However, power supply 110 can also provide DC voltage to any DC-DC voltage converter or system power line to power the anti-attack circuit system 100.

[0013] Furthermore, referring to Figure 1, the anti-attack circuit system 100 further includes a buffer capacitor CDIG and a leakage transistor MB. When the operating circuit 150 operates at the operating voltage VDIG, depending on the operating procedure, the operating circuit 150 may generate a momentary current peak (e.g., instantaneous current). At this time, such instantaneous current is absorbed by the buffer capacitor CDIG with an appropriate capacitance value, thereby providing a more stable operating voltage VDIG and protecting the operating circuit 150 from damage due to the instantaneous large current.

[0014] Similarly, the leakage current transistor MB also protects the operating circuit 150 from damage due to instantaneous current by releasing current. For example, after the operating circuit 150 finishes the operation requiring protection, the control circuit 120 needs time to detect and react. Therefore, for a period of time afterward, the current supply unit 130 and the switching unit 140 continue to supply the operating voltage VDIG to the operating circuit 150. However, at this time, the operating circuit 150 is no longer operating (i.e., the required current is very low). If the same current as before the end of the operation is supplied, the operating circuit 150 may be damaged. Therefore, through an appropriate control voltage VB, the leakage current transistor MB can act as a channel for excess current, thereby protecting the operating circuit 150 from damage.

[0015] Figure 2 is a partial schematic diagram of an anti-attack circuit system 100 according to an embodiment of the present invention, and Figure 3 is a flowchart 300 showing the operation of a control loop 120 according to an embodiment of the present invention. Referring to Figure 2, the control loop 120 includes comparators 122a and 122b, a logic circuit 124, and a counter 126. The negative input of comparator 122a and the positive input of comparator 122b are coupled to node N2 to receive an operating voltage VDIG. The positive input of comparator 122a receives the sum of a target voltage VTAR and a control voltage VC, while the negative input of comparator 122b receives the difference between the target voltage VTAR and the control voltage VC. That is, through comparators 122a and 122b, the operating voltage VDIG can be controlled between a first comparison voltage (i.e., VTAR + VC) and a second comparison voltage (i.e., VTAR - VC).

[0016] Logic circuit 124 is configured to output a logic signal L to counter 126 to drive counter 126 to increment or decrement a count value. Logic circuit 124 and comparators 122a and 122b are all controlled by a clock signal CLK. For example, each positive edge of the clock signal CLK triggers comparators 122a and 122b and logic circuit 124 to perform an operation. Therefore, after detecting a positive edge of the clock signal CLK, comparators 122a and 122b compare the operating voltage VDIG, the first comparison voltage, and the second comparison voltage, and output control signals OUT1 and OUT2. Simultaneously, after detecting a positive edge of the clock signal CLK, logic circuit 124 outputs a logic signal L to drive counter 126 to increment or decrement the count value. The count value changes the control signal SC, causing a change in the number of control switches S1, S2, ... Sn turned on in switching unit 140.

[0017] Furthermore, referring to Figure 2, the operating switch SW1 includes a transistor T1 and a logic gate 260. The source terminal of transistor T1 is coupled to node N2, the drain terminal is coupled to node N1, and the gate terminal is coupled to logic gate 260 (e.g., a gate). When any of the control signals OUT1, OUT2, and the start signal ST has a logic low level (e.g., logic 0), transistor T1 is turned on, thereby turning on the operating switch SW1. Conversely, when the control signals OUT1, OUT2, and the start signal ST all have a logic high level (e.g., logic 1), transistor T1 is not turned on, thereby turning off the operating switch SW1. It should be noted that the transistor T1 and logic gate 260 here are only examples; other switching elements and logic gates can also be used to achieve the same or similar effects.

[0018] The following description, in conjunction with Figures 2 and 3, illustrates the operation of control loop 120 detecting the operating voltage VDIG to change the number of control switches S1, S2, ... Sn that are turned on. Furthermore, since control loop 120 is only activated when the operating circuit 150 performs an operation requiring protection, the following procedures assume that the start signal ST has a logic high level. In step 302, comparator 122a determines the relationship between the operating voltage VDIG and the first comparison voltage (i.e., the sum of the target voltage VTAR and the control voltage VC), while comparator 122b determines the relationship between the operating voltage VDIG and the second comparison voltage (i.e., the difference between the target voltage VTAR and the control voltage VC).

[0019] If the condition is determined to be state 315a, i.e., the operating voltage VDIG is less than the difference between the target voltage VTAR and the control voltage VC, then comparator 122a outputs a control signal OUT1 with a logic high level (e.g., logic 1), while comparator 122b outputs a control signal OUT2 with a logic low level (e.g., logic 0). Since control signal OUT2 has a logic low level, logic gate 260 controls transistor T1 to conduct, causing operating switch SW1 to conduct, thereby rapidly raising the operating voltage VDIG to the voltage level of output voltage VLDO. Furthermore, counter 126 increments the count value (e.g., by 1) based on the control signals OUT1 and OUT2, which have logic high and logic low levels respectively, to change the control signal SC, thereby increasing the number of activated control switches S1, S2, ... Sn (e.g., by 1). Increasing the number of activated control switches S1, S2, ... Sn will increase the current flowing from current sources I1, I2, ... In to the operating circuit 150, thereby causing the operating voltage VDIG to rise.

[0020] If the condition is determined to be state 315c, that is, the operating voltage VDIG is greater than the sum of the target voltage VTAR and the control voltage VC, then comparator 122a outputs a control signal OUT1 with a logic low level (e.g., logic 0), and comparator 122b outputs a control signal OUT2 with a logic high level (e.g., logic 1). Since the control signal OUT1 has a logic low level, logic gate 260 controls transistor T1 to conduct, causing operating switch SW1 to conduct, thereby rapidly reducing the operating voltage VDIG to the voltage level of output voltage VLDO. In addition, counter 126 reduces the count value (e.g., decrement by 1) according to the control signals OUT1 and OUT2 with logic low and logic high levels, respectively, to change the control signal SC, thereby reducing the number of conducting control switches S1, S2, ... Sn (e.g., decrement by 1). Reducing the number of active control switches S1, S2, ... Sn will reduce the current flowing from current sources I1, I2, ... In to operating circuit 150, thereby causing the operating voltage VDIG to drop.

[0021] If the condition is determined to be state 315b (or state 315d), that is, the operating voltage VDIG is between the first comparison voltage (VTAR+VC) and the second comparison voltage (VTAR-VC), then comparators 122a and 122b output control signals OUT1 and OUT2 with logic high levels (e.g., logic 1), respectively. Next, step 304 is entered (or step 310 if in state 315d). Since control signals OUT1, OUT2, and the start signal ST all have logic high levels, logic gate 260 controls transistor T1 to turn off, thereby disconnecting operating switch SW1 and isolating the operating voltage VDIG from the output voltage VLDO. Furthermore, counter 126 maintains its count value unchanged based on the logic high-level control signals OUT1 and OUT2, ensuring that the number of active control switches S1, S2, ... Sn remains constant, and maintaining the current operating voltage VDIG.

[0022] It should be noted that since the response speed of the control circuit 120 adjusting the switching unit 140 is limited by the clock signal CLK (e.g., by incrementing the count value of the clock signal CLK by 1 with each positive edge trigger, the number of control switches S1, S2, ... Sn that are turned on increases by 1), it may not react in time when encountering drastic voltage changes (e.g., the operating voltage VDIG instantly becomes much lower than the difference between the target voltage VTAR and the control voltage VC, or much higher than the sum of the target voltage VTAR and the control voltage VC), causing the operating circuit 150 to malfunction. Therefore, the present invention provides a stable operating voltage VDIG by briefly turning on the operating switch SW1 when a drastic voltage change occurs, so that the operating voltage VDIG quickly reaches the voltage level of the output voltage VLDO (i.e., between the first comparison voltage (VTAR+VC) and the second comparison voltage (VTAR-VC)) and then turning off the operating switch SW1.

[0023] For example, if the condition is determined to be state 315a and the operating voltage VDIG is much lower than the difference between the target voltage VTAR and the control voltage VC, then referring to the description of state 315a above, the operating switch SW1 is turned on, causing the operating voltage VDIG to rise rapidly to the output voltage VLDO. Simultaneously, the control signal SC increases the number of turned-on control switches S1, S2, ... Sn, thereby adjusting the switching unit 140 to a state where the operating voltage VDIG is between the first comparison voltage (e.g., VTAR + VC) and the second comparison voltage (e.g., VTAR - VC). At this time, the control loop 120 detects that the operating voltage VDIG is between the first and second comparison voltages, and thus controls the operating switch SW1 to turn off. Furthermore, since the switching unit 140 has been adjusted to a state where the operating voltage VDIG is between the first and second comparison voltages, the control loop 120 will maintain the number of turned-on switching units 140 and keep the operating switch SW1 off during the next detection.

[0024] Similarly, if the operating voltage VDIG is much higher than the sum of the target voltage VTAR and the control voltage VC, the control loop 120 controls the operating switch SW1 to turn on, so that the operating voltage VDIG drops rapidly to the output voltage VLDO, and adjusts the number of turned-on switching units 140. Thus, when the control loop 120 detects again, the operating voltage VDIG can be maintained between the first comparison voltage and the second comparison voltage. In this way, the anti-attack circuit system 100 can quickly return to the protected operating mode where the output voltage VLDO and the operating voltage VDIG are isolated, without being limited by the clock signal CLK to slowly raise or lower the operating voltage VDIG. This also prevents the operating circuit 150 from malfunctioning due to a prolonged insufficient operating voltage VDIG, or from being damaged due to a prolonged excessively high operating voltage VDIG.

[0025] Figure 4 is a timing diagram 400 illustrating the operation of the operating circuit 150 according to an embodiment of the present invention. Referring to Figure 4, during a time period t1, the operating circuit 150 performs a normal operating procedure. Therefore, the start signal ST is at a low logic level (e.g., logic 0), the control loop 120 is in a disabled state, and the operating switch SW1 is turned on. Consequently, the operating voltage VDIG rises with the output voltage VLDO. Then, during a time period t2, the operating circuit 150 performs a protected operation. Therefore, the start signal ST has a high logic level (e.g., logic 1), the control loop 120 is enabled, and the operating switch SW1 is turned off. Consequently, the operating voltage VDIG fluctuates within a certain range. That is, during time period t2, the operating voltage VDIG is controlled by the current supply unit 130 through different numbers of turned-on switching units 140, switching between states 315a, 315b, 315c, and 315d. Then, during a time period t3, the operating circuit 150 returns to the normal operating state. Therefore, when the start signal ST recovers to the low level of the logic (e.g., logic 0), control loop 120 is disabled, causing operating switch SW1 to turn on. Consequently, the operating voltage VDIG remains stable along with the output voltage VLDO.

[0026] This invention provides an anti-attack circuit system. When the NPU performs an operation requiring protection, the connection between the power supply and the NPU is disconnected via a control loop. Instead, the required operating voltage for the NPU is provided through a current source and a control switch. If the operating voltage is significantly lower than the difference between the target voltage and the control voltage (i.e., the second comparison voltage), or if the operating voltage is significantly higher than the sum of the target voltage and the control voltage (i.e., the first comparison voltage), the control loop can briefly turn on the operating switch to quickly bring the operating voltage to the same level as the power supply's output voltage. Simultaneously, the control loop adjusts the number of on control switches to ensure that the operating voltage is between the first and second comparison voltages. This ensures that the NPU will not malfunction or be damaged due to drastic changes in the operating voltage, and also allows the control loop sufficient time to adjust the current source and control switch to provide the appropriate operating voltage.

[0027] Furthermore, by using buffer capacitors and leakage transistors, the anti-attack circuit system provided by this invention can further enhance the protection mechanism for the NPU. The buffer capacitors and leakage transistors guide excessive current to the ground terminal, preventing damage to the NPU due to instantaneous current. Moreover, since the control loop is only activated when the NPU performs operations requiring protection, unnecessary power consumption can be reduced.

[0028] 100: Anti-attack circuit system 110: Power Supply 115: Operational amplifier 120: Control loop 130: Current supply unit 140: Switching Unit 150: Operating Circuit VREF: Reference Voltage VLDO: Output voltage VDD: Supply voltage N1, N2: Nodes RL: Resistance ML,T1: Transistor MB: Leakage Transistor SW1: Operation switch VDIG: Operating voltage SC, OUT1, OUT2: Control signals CDIG: Buffer capacitor VB, VC: Control voltage ST: Start Signal I1, I2, I3, In: Current sources S1, S2, S3, Sn: Control switches 122a, 122b: Comparators 124: Logic Circuits 126: Counter 260: Logic Gate VTAR: Target Voltage CLK: Clock signal L: Logic signal 300: Flowchart 302, 304, 306, 308, 310: Steps 315a, 315b, 315c, 315d: Status 400: Timing Diagram t1, t2, t3: Time periods

Claims

1. An anti-attack circuit system, comprising: A power supply is configured to output an output voltage at a first node; An operating switch is configured to be coupled between the first node and a second node; a plurality of current sources and a plurality of control switches, wherein the current sources are coupled to the second node through corresponding control switches; a control loop is configured to control the operating switch to be turned on or off according to an operating voltage, a target voltage and a control voltage, and to control the current sources and control switches to change the operating voltage. A neural network processor is configured to be coupled to the second node, wherein, in response to the operation switch being turned off, the neural network processor is powered by at least one of the current sources.

2. The anti-attack circuit system as described in claim 1, wherein: The control loop generates a first control signal and a second control signal based on the operating voltage, the target voltage, and the control voltage; in response to the neural network processor operating according to the operating voltage, it sets a start signal to a first logic level; and in response to the first control signal, the second control signal, and the start signal having the first logic level, the operation switch is turned on.

3. The anti-attack circuitry system as described in claim 2, wherein the operating switch comprises: A logic gate is configured to receive the first control signal, the second control signal, and the start signal; The transistor has a first terminal, a second terminal, and a control terminal, the first terminal being coupled to the first node, the second terminal being coupled to the second node, and the control terminal being coupled to an output terminal of the logic gate, wherein the logic gate controls the transistor to conduct in response to at least one of the first control signal, the second control signal, and the start signal being a second logic level different from the first logic level.

4. The anti-attack circuitry system as described in claim 1, wherein the control loop comprises: A first comparator is configured to compare the operating voltage with a first comparison voltage to generate a first control signal; A second comparator is configured to compare the operating voltage with a second comparison voltage to generate a second control signal; a counter is configured to increase or decrease a count value according to the first control signal and the second control signal, and to generate a corresponding third control signal according to the count value; and a logic circuit is configured to drive the counter to increase or decrease the count value according to a clock signal, wherein, in response to the operating voltage being greater than the first comparison voltage or less than the second comparison voltage, the third control signal adjusts the number of switches turned on among the control switches.

5. The anti-attack circuit system as described in claim 4, wherein: In response to the operating voltage being between the first comparison voltage and the second comparison voltage, the control loop controls the number of switches turned on in the control switches to remain unchanged and controls the operating switch to be turned off; in response to the operating voltage being greater than the first comparison voltage, the control loop controls the number of switches turned on in the control switches to decrease and controls the operating switch to be turned on; and in response to the operating voltage being less than the second comparison voltage, the control loop controls the number of switches turned on in the control switches to increase and controls the operating switch to be turned on.

6. The anti-attack circuitry system as described in claim 1 further includes a buffer capacitor coupled between the second node and a ground terminal, configured to buffer instantaneous current generated during the operation of the neural network processor.

7. The anti-attack circuitry system as described in claim 1 further includes a leakage transistor coupled between the second node and a ground terminal, and configured to draw redundant current beyond the current sources required by the neural network processor.

8. The anti-attack circuit system as described in claim 1, wherein the power supply is a low-dropout regulator, a DC-DC voltage converter, or a system power line.

9. The anti-attack circuitry system as described in claim 1, wherein the output voltage is used to power the neural network processor when it is performing an operation that does not require protection or when it is not performing an operation.

10. The anti-attack circuit system as described in claim 1, wherein: The control loop connects the current source and the neural network processor when the neural network processor is operating; and connects the voltage supply and the neural network processor when the neural network processor is deactivated.

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