Design method of semiconductor structure

Abstract

A design method of a semiconductor structure is provided. The semiconductor structure includes n conductive layers and a via. The n conductive layers are separated from each other. There is an opening in the semiconductor structure. The via is located in the opening. The opening penetrates through the n conductive layers to form n holes in the n conductive layers. The via and the top surfaces of the n-1 conductive layers have n-1 annular overlapping regions. The n is an integer greater than

Description

[Technical Field]

[0001] This invention relates to a method for designing a semiconductor structure, and more particularly to a method for designing a semiconductor structure including vias. [Previous Technology]

[0002] Currently, in some semiconductor structures, multiple metal layers are electrically connected by vias that pass through multiple conductive layers. In the fabrication process of these vias, openings are formed to accommodate the vias, and these openings pass through multiple conductive layers, creating multiple holes within those layers. However, optimizing the interfacial resistance between the conductive layers and the vias, as well as the size of the holes within the conductive layers, remains a continuous research goal. [Summary of the Invention]

[0003] The present invention provides a semiconductor structure design method that can optimize the interface resistance between the conductive layer and the via as well as the size of the holes in the conductive layer.

[0004] This invention proposes a design method for a semiconductor structure. The semiconductor structure includes n conductive layers and vias. The n conductive layers are separated from each other. An opening is present in the semiconductor structure. The via is located within the opening. The opening passes through the n conductive layers, forming n holes in the n conductive layers. The vias and the top surfaces of the n-1 conductive layers have n-1 annular overlapping regions. n is an integer greater than 1. The design method for the semiconductor structure includes the following steps: Providing the (n-1)th minimum diameter of the top of the (n-1)th via. Defining the distance between the bottom of the (n-1)th conductive layer and the bottom of the nth conductive layer, the interface resistance between the (n-1)th conductive layer and the via, the angle between the top surface of the (n-1)th conductive layer and the sidewall of the via, and the thickness of the (n-1)th conductive layer. Calculating the side resistance between the sidewall of the (n-1)th conductive layer exposed by the (n-1)th via and the via. Calculating the overlap resistance of the (n-1)th annular overlapping region. The width of the (n-1)th annular overlapping region is calculated using the (n-1)th minimum diameter, the thickness, the side resistance, and the overlapping resistance. The nth minimum diameter of the top of the nth hole is calculated using the included angle, the (n-1)th minimum diameter, the width, and the distance.

[0005] According to an embodiment of the present invention, in the above-described semiconductor structure design method, in response to n being 2, the method for providing the (n-1)th minimum diameter may include calculating the (n-1)th minimum diameter by means of etch margin.

[0006] According to an embodiment of the present invention, in the above-described semiconductor structure design method, the side resistance calculation method may include calculating the side resistance by means of the (n-1)th minimum diameter and the thickness.

[0007] According to an embodiment of the present invention, in the above-described semiconductor structure design method, the method for calculating the overlapping resistance may include calculating the overlapping resistance by means of the interface resistance and the side resistance.

[0008] According to an embodiment of the present invention, in the above-described semiconductor structure design method, the width can be calculated by the following formula 1.

[0009] Wn-1 is the width of the (n-1)th annular overlapping region, hn-1 is the (n-1)th minimum diameter of the top of the (n-1)th hole, Tn-1 is the thickness of the (n-1)th conductive layer, RSn-1 is the side resistance between the sidewall of the (n-1)th conductive layer exposed by the (n-1)th hole and the via, and ROn-1 is the overlap resistance of the (n-1)th annular overlapping region.

[0010] According to an embodiment of the present invention, in the above-described semiconductor structure design method, the nth minimum diameter can be calculated by the following formula 2.

[0011] Where, hn is the nth minimum diameter at the top of the nth hole, hn-1 is the nth minimum diameter at the top of the (n-1)th hole, θn-1 is the angle between the top surface of the (n-1)th conductive layer and the sidewall of the through hole, Wn-1 is the width of the (n-1)th annular overlapping region, and Hn-1 is the distance between the bottom of the (n-1)th conductive layer and the bottom of the nth conductive layer.

[0012] According to an embodiment of the present invention, in the above-described semiconductor structure design method, the semiconductor structure further includes a first conductive layer. The bottom of the via is connected to the first conductive layer.

[0013] According to an embodiment of the present invention, in the above-described semiconductor structure design method, the semiconductor structure further includes a second conductive layer. The top of the via is connected to the second conductive layer.

[0014] According to an embodiment of the present invention, in the above-described semiconductor structure design method, the n conductive layers can be multiple metal layers.

[0015] According to an embodiment of the present invention, in the above-described semiconductor structure design method, the material of the through hole is, for example, a metal.

[0016] Based on the above, in the semiconductor structure design method proposed in this invention, the width of the (n-1)th annular overlapping region and the nth minimum diameter of the top of the nth hole can be calculated. Therefore, the width of the (n-1)th annular overlapping region and the nth minimum diameter of the top of the nth hole can be adjusted according to requirements, thereby optimizing the interface resistance between the conductive layer and the via and the size of the hole in the conductive layer.

[0017] In order to make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are given in conjunction with the accompanying drawings.

Implementation Method

[0018] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. Additionally, features in the cross-sectional views are not drawn to the same scale as those in the perspective views. In fact, for clarity of explanation, the dimensions of various features may be arbitrarily increased or decreased.

[0019] FIG1 is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention. FIG2 is a perspective view of region RR in FIG1. ​​In FIG2, some components in FIG1 are omitted to clearly illustrate the arrangement relationship between the components in FIG2.

[0020] The semiconductor structure design method of this embodiment is applicable to the semiconductor structure 10 shown in Figures 1 and 2. Referring to Figures 1 and 2, the semiconductor structure 10 includes n conductive layers 100 and vias 102. The n conductive layers 100 are separated from each other. An opening 104 is provided in the semiconductor structure 10. The vias 102 are located in the opening 104. The opening 104 passes through the n conductive layers 100, forming n holes 106 in the n conductive layers 100. The vias 102 and the top surfaces of the n-1 conductive layers 100 have n-1 annular overlapping regions R1. n is an integer greater than 1. In some embodiments, the n conductive layers 100 may be multiple metal layers. In some embodiments, the material of the vias 102 is, for example, metal. Furthermore, although not shown in the figures, the n conductive layers 100 may be located on a substrate structure, and their description is omitted here. In addition, the number of conductive layers 100 and the number of holes 106 are not limited to the numbers shown in the figures. As long as there are multiple conductive layers 100 and multiple holes 106, they fall within the scope of this invention.

[0021] In some embodiments, the semiconductor structure 10 may further include a conductive layer 108. The bottom 102A of the via 102 is connected to the conductive layer 108. In some embodiments, the semiconductor structure 10 may further include a conductive layer 110. The top 102B of the via 102 is connected to the conductive layer 110. In some embodiments, the conductive layer 108 and the conductive layer 110 may be an interconnect structure or a redistribution layer (RDL).

[0022] In some embodiments, the n conductive layers 100 may be conductive layers on different wafers or conductive layers on the same wafer. In some embodiments, the semiconductor structure 10 may further include a plurality of intermediate structures 112. The plurality of intermediate structures 112 are located between the plurality of conductive layers 100, between the conductive layer 100 and the conductive layer 108, and between the conductive layer 100 and the conductive layer 110. In some embodiments, the intermediate structure 112 may include a dielectric layer, an interconnect structure, a semiconductor element, a semiconductor substrate, or a combination thereof.

[0023] In this embodiment, n is described using 3 as an example, but the present invention is not limited thereto. For example, when n is 3, the n conductive layers 100 may include conductive layer 100A, conductive layer 100B and conductive layer 100C, the n holes 106 may include hole 106A, hole 106B and hole 106C, and the n-1 annular overlapping regions R1 may include annular overlapping region R11 and annular overlapping region R12.

[0024] The conductive layer 100A may have a thickness T1. The conductive layer 100B may have a thickness T2. The conductive layer 100C may have a thickness T3. The top of the hole 106A may have a minimum diameter h1. The top of the hole 106B may have a minimum diameter h2. The top of the hole 106C may have a minimum diameter h3. The distance between the bottom of the conductive layer 100A and the bottom of the conductive layer 100B is H1. The distance between the bottom of the conductive layer 100B and the bottom of the conductive layer 100C is H2. The via 102 and the top surface of the conductive layer 100A have an annular overlapping region R11. The width of the annular overlapping region R11 is W1. The via 102 and the top surface of the conductive layer 100B have an annular overlapping region R12. The width of the annular overlapping region R12 is W2. The angle between the top surface of the conductive layer 100A and the sidewall of the via 102 is θ1. The angle between the top surface of the conductive layer 100B and the sidewall of the through hole 102 is θ2.

[0025] Figure 3 is a flowchart of a semiconductor structure design method according to some embodiments of the present invention. Hereinafter, the semiconductor structure design method according to some embodiments of the present invention will be described with reference to Figures 1 to 3.

[0026] Referring to Figures 1 to 3, step S100 is performed to provide the (n-1)th minimum diameter of the top of the (n-1)th hole. In some embodiments, in response to n being 2, the method for providing the (n-1)th minimum diameter may include calculating the (n-1)th minimum diameter using an etching margin. For example, in Figures 1 and 2, the minimum diameter h1 of the top of the first hole 106A may be calculated using an etching margin.

[0027] Proceed to step S102, defining the distance between the bottoms of the (n-1)th conductive layer and the bottom of the nth conductive layer, the interface resistance between the (n-1)th conductive layer and the via, the angle between the top surface of the (n-1)th conductive layer and the sidewall of the via, and the thickness of the (n-1)th conductive layer. That is, the distance between the bottoms of the (n-1)th conductive layer and the bottom of the nth conductive layer, the interface resistance between the (n-1)th conductive layer and the via, the angle between the top surface of the (n-1)th conductive layer and the sidewall of the via, and the thickness of the (n-1)th conductive layer are known parameters. For example, in Figures 1 and 2, the distance H1, the interface resistance between conductive layer 100A and via 102, the angle θ1, and the thickness T1 are known parameters.

[0028] Proceed to step S104 to calculate the side resistance between the sidewall of the (n-1)th conductive layer exposed by the (n-1)th hole and the via. In some embodiments, the method for calculating the side resistance may include calculating the side resistance using the (n-1)th minimum diameter and the thickness. For example, in Figures 1 and 2, the side resistance between the sidewall of the conductive layer 100A exposed by the hole 106A and the via 102 can be calculated using the minimum diameter h1 and the thickness T1.

[0029] Proceed to step S106 to calculate the overlap resistance of the (n-1)th annular overlapping region. In some embodiments, since the interface resistance is the parallel resistance of the side resistance and the overlap resistance, the method for calculating the overlap resistance may include calculating the overlap resistance using the interface resistance and the side resistance. For example, in Figures 1 and 2, the overlap resistance of the annular overlapping region R11 can be calculated using the interface resistance between the conductive layer 100A and the via 102 and the side resistance between the sidewall of the conductive layer 100A exposed by the hole 106A and the via 102.

[0030] Proceed to step S108, whereby the width of the (n-1)th annular overlapping region is calculated using the (n-1)th minimum diameter, the thickness, the side resistance, and the overlapping resistance. In some embodiments, the width can be calculated using the following formula 1.

[0031] Wn-1 is the width of the (n-1)th annular overlapping region, hn-1 is the (n-1)th minimum diameter of the top of the (n-1)th hole, Tn-1 is the thickness of the (n-1)th conductive layer, RSn-1 is the side resistance between the sidewall of the (n-1)th conductive layer exposed by the (n-1)th hole and the via, and ROn-1 is the overlap resistance of the (n-1)th annular overlapping region. For example, in Figures 1 and 2, the width W1 of the annular overlapping region R11 can be calculated using the minimum diameter h1, the thickness T1, the side resistance between the sidewall of the conductive layer 100A exposed by the hole 106A and the via 102, and the overlap resistance of the annular overlapping region R11.

[0032] Proceed to step S110, calculate the nth minimum diameter of the top of the nth hole using the included angle, the (n-1)th minimum diameter, the width, and the distance. In some embodiments, the nth minimum diameter can be calculated using the following formula 2.

[0033] Where hn is the nth minimum diameter at the top of the nth hole, hn-1 is the (n-1)th minimum diameter at the top of the (n-1)th hole, θn-1 is the angle between the top surface of the (n-1)th conductive layer and the sidewall of the through hole, Wn-1 is the width of the (n-1)th annular overlapping region, and Hn-1 is the distance between the bottom of the (n-1)th conductive layer and the bottom of the nth conductive layer. For example, in Figures 1 and 2, the minimum diameter h2 at the top of hole 106B can be calculated using the minimum diameter h1, the angle θ1, the width W1, and the distance H1.

[0034] In some embodiments, after calculating the width W1 and the minimum diameter h2, steps S102, S104, S106, S108, and S110 can be repeated to calculate the width W2 of the annular overlapping region R12 and the minimum diameter h3 of the top of the hole 106C. In this embodiment, the top surface of the through hole 102 and the conductive layer 100C does not have an annular overlapping region, but the present invention is not limited thereto. In other embodiments, the top surface of the through hole 102 and the conductive layer 100C may have an annular overlapping region (not shown).

[0035] Based on the above embodiments, it is known that in the semiconductor structure design method, the width of the (n-1)th annular overlapping region and the nth minimum diameter of the top of the nth hole can be calculated. Therefore, the width of the (n-1)th annular overlapping region and the nth minimum diameter of the top of the nth hole can be adjusted according to requirements, thereby optimizing the interface resistance between the conductive layer and the via and the size of the hole in the conductive layer. For example, in Figures 1 and 2, by using the semiconductor structure design method of the above embodiments, the interface resistance between the conductive layer 100A and the via 102 and the minimum diameter h2 of the top of the hole 106B in the conductive layer 100B can be optimized.

[0036] In summary, by means of the semiconductor structure design method of the above embodiments, the width of the (n-1)th annular overlapping region and the nth minimum diameter of the top of the nth hole can be adjusted according to the requirements, thereby optimizing the interface resistance between the conductive layer and the via and the size of the hole in the conductive layer.

[0037] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0038] Figure 1 is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention. Figure 2 is a perspective view of region RR in Figure 1. Figure 3 is a flowchart of a design method for a semiconductor structure according to some embodiments of the present invention.

Claims

1. A method for designing a semiconductor structure, wherein the semiconductor structure includes n conductive layers and vias, the n conductive layers are separated from each other, the semiconductor structure has an opening, the vias are located in the openings, the openings pass through the n conductive layers to form n holes in the n conductive layers, the vias have n-1 annular overlapping regions with the top surfaces of the n-1 conductive layers, n is an integer greater than 1, and the method for designing the semiconductor structure includes: Provide the (n-1)th minimum diameter at the top of the (n-1)th hole; Define the distance between the bottom of the (n-1)th conductive layer and the bottom of the nth conductive layer, the interface resistance between the (n-1)th conductive layer and the via, the angle between the top surface of the (n-1)th conductive layer and the sidewall of the via, and the thickness of the (n-1)th conductive layer; calculate the side resistance between the sidewall of the (n-1)th conductive layer exposed by the (n-1)th hole and the via; calculate the overlap resistance of the (n-1)th annular overlapping region; calculate the width of the (n-1)th annular overlapping region using the (n-1)th minimum diameter, the thickness, the side resistance, and the overlap resistance; and calculate the nth minimum diameter of the top of the nth hole using the angle, the (n-1)th minimum diameter, the width, and the distance.

2. The method for designing a semiconductor structure as claimed in claim 1, wherein the method for providing the (n-1)th minimum diameter in response to n being 2 includes calculating the (n-1)th minimum diameter by means of an etch margin.

3. The method for designing a semiconductor structure as claimed in claim 1, wherein the method for calculating the side resistance includes calculating the side resistance using the (n-1)th minimum diameter and the thickness.

4. The method for designing a semiconductor structure as claimed in claim 1, wherein the method for calculating the overlapping resistance includes calculating the overlapping resistance using the interface resistance and the side resistance.

5. A method for designing a semiconductor structure as claimed in claim 1, wherein the width is calculated by the following formula 1, wherein, Wn-1 is the width of the (n-1)th annular overlapping region, hn-1 is the (n-1)th minimum diameter at the top of the (n-1)th hole, Tn-1 is the thickness of the (n-1)th conductive layer, RSn-1 is the side resistance between the sidewall of the (n-1)th conductive layer exposed by the (n-1)th hole and the via, and ROn-1 is the overlap resistance of the (n-1)th annular overlapping region.

6. A method for designing a semiconductor structure as claimed in claim 1, wherein the nth minimum diameter is calculated by the following formula 2, wherein, hn is the nth minimum diameter at the top of the nth hole, hn-1 is the n-1th minimum diameter at the top of the (n-1)th hole, θn-1 is the angle between the top surface of the (n-1)th conductive layer and the sidewall of the through hole, Wn-1 is the width of the (n-1)th annular overlapping region, and Hn-1 is the distance between the bottom of the (n-1)th conductive layer and the bottom of the nth conductive layer.

7. A method for designing a semiconductor structure as described in claim 1, wherein the semiconductor structure further comprises: A first conductive layer, wherein the bottom of the through-hole is connected to the first conductive layer.

8. A method for designing a semiconductor structure as described in claim 7, wherein the semiconductor structure further comprises: A second conductive layer, wherein the top of the through-hole is connected to the second conductive layer.

9. A method for designing a semiconductor structure as claimed in claim 1, wherein the n conductive layers comprise a plurality of metal layers.

10. A method for designing a semiconductor structure as claimed in claim 1, wherein the material of the via includes metal.

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