Memory circuits and methods for forming the same

Abstract

A circuit includes a memory array including memory cells; and input / output (I / O) circuits, each of the I / O circuits including a corresponding sense amplifier that is operatively coupled to a corresponding subset of the memory cells. Each of the I / O circuits includes a first input level shifter, a second input level shifter, and an output level shifter, each of the first input level shifter, the second input level shifter, and the output level shifter being coupled between a first voltage domain and a second voltage domain. The output level shifter has an input directly coupled to an output of a first multiplexer, the first multiplexer operating in the second voltage domain and configured to select one of a first signal present on a first input of the first multiplexer or a second signal present on a second input of the first multiplexer based on a first control signal.

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