Memory device

Abstract

dimensions, bitlines connected to the memory cells, wordlines connected to the memory cells, main wordline select lines, inverted wordline select lines, sub-wordline select lines, ground select lines, main select transistors having a drain connected to one of the sub-wordline select lines, a source connected to one of the wordlines, and a gate connected to one of the main wordline select lines, and complementary select transistors having a drain connected to one of the wordlines, a source connected to one of the ground select lines, and a gate connected to one of the inverted wordline select lines; and a second semiconductor layer including first driver circuits driving sub-wordline select lines, second driver circuits driving the main wordline select lines, and third driver circuits driving the inverted wordline select lines. The second semiconductor layer is on the first semiconductor layer.

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