Built-in self-trim device and system and operating method thereof

Abstract

Systems, devices, and methods of operating said systems and devices are disclosed. In one aspect, a system includes a memory circuit, a plurality of bias generator circuits each corresponding to a respective input of the memory circuit, and a built-in self-trim circuit. The built-in self-trim circuit can receive a feedback signal from a first bias generator circuit of the plurality of bias generator circuits. The built-in self-trim circuit can generate a trim code for the first bias generator circuit based on the feedback signal and a voltage reference, causing the first bias generator circuit to generate an output voltage for the respective input of the memory array.

Description

Technical Field

[0001] One embodiment of this disclosure provides a built-in self-adjusting voltage regulator device, a system with a built-in self-adjusting voltage regulator, and a method for operating the built-in self-adjusting voltage regulator device. Prior Technology

[0002] Integrated circuits (ICs) can contain various hardware circuit devices or logic types, including FPGAs, application-specific integrated circuits (ASICs), logic gates, registers, or transistors, as well as various interconnections between circuit devices. ICs can be manufactured using or composed of semiconductor materials, for example, as part of electronic devices such as computers, portable devices, smartphones, and Internet of Things (IoT) devices. The development and increasing complexity of ICs have driven higher demands for computing efficiency and speed. More specifically, ICs can be configurable and / or programmable to perform calculations in a sequence or variation required by the manufacturer, developer, technician, or programmer. Summary of the Invention

[0003] One embodiment of this disclosure discloses a system with a built-in self-adjusting device. The system includes memory circuitry, a plurality of bias generator circuits, and a built-in self-adjusting circuit, each bias generator circuit corresponding to an individual input of the memory circuitry. The built-in self-adjusting circuit receives a feedback signal from a first bias generator circuit among the plurality of bias generator circuits. Based on the feedback signal and a voltage reference, the built-in self-adjusting circuit generates a fine-tuning code for the first bias generator circuit, causing the first bias generator circuit to generate an output voltage for an individual input of the memory array.

[0004] In another embodiment of this disclosure, a built-in self-adjusting device is disclosed. The built-in self-adjusting device includes a comparator circuit, a first search circuit coupled to the comparator circuit, and a second search circuit for generating a trim code for a bias generator circuit based on the output of the comparator circuit, wherein the output is generated based on a feedback signal from the bias generator circuit.

[0005] In yet another embodiment of this disclosure, a method for operating a built-in self-adjusting device is disclosed. The method includes calibrating the built-in self-adjusting circuitry of a memory device using a first search operation. The method includes using the built-in self-adjusting circuitry and a second search operation to determine a trimming code for a bias generator circuitry of the memory device. The method includes using the bias generator circuitry to generate a voltage for at least one control input in a memory array of the memory device. Simple Explanation of the Diagram

[0006] The features disclosed herein are best understood when studied in conjunction with the accompanying figures, and are described in the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 is a block diagram of an example memory system with a built-in self-tuning circuit for a voltage regulator circuit, according to some embodiments of the present disclosure. Figure 2 illustrates a block diagram of an example of a built-in self-tuning circuit used to calibrate a voltage regulator circuit according to some embodiments of the present disclosure. Figure 3 illustrates a block diagram of an example of the configuration of Figure 2 for calibrating multiple voltage regulator circuits according to some embodiments of the present disclosure, showing a built-in self-tuning circuit. Figure 4 illustrates a block diagram of another example of a built-in self-tuning circuit used to calibrate a voltage regulator circuit based on direct voltage output, according to some embodiments of this disclosure. Figure 5 illustrates a block diagram of a built-in self-tuning circuit, an example of Figure 4, for calibrating multiple voltage regulator circuits according to some embodiments of this disclosure. Figure 6 illustrates a block diagram of another example memory system that implements a built-in self-tuning circuit for a voltage regulator circuit using a one-time programmable memory circuit according to some embodiments of the present disclosure. Figure 7 illustrates a block diagram of an example of a built-in self-tuning circuit for calibrating multiple voltage regulator circuits using a one-time programmable memory circuit, according to some embodiments of the present disclosure. Figure 8 illustrates a schematic diagram of an example binary search process that can be implemented via one or more circuits described herein, according to some embodiments of the present disclosure. Figure 9 illustrates a schematic diagram of an example linear search process that can be implemented via one or more circuits described herein, according to some embodiments of the present disclosure. Figure 10 illustrates a flowchart of an example method of operating the disclosed circuit described herein according to some embodiments of this disclosure. Implementation

[0007] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," "top," "bottom," and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted similarly accordingly.

[0009] Voltage regulators can be used in memory devices to generate precise bias voltages for memory operation. However, achieving accurate voltage bias often requires fine-tuning within the memory circuitry, which introduces additional testing costs and requires additional chip area for storing on-chip fine-tuning bits. Conventional methods to alleviate fine-tuning requirements (such as auto-zeroing or chopper stabilizer designs) can mitigate some of these problems, but lead to several drawbacks, including slower circuit operation, increased circuit area, or the introduction of clock noise.

[0010] Fine-tuning voltage regulators involves generating "trim codes," which are numerical representations of adjustments to the voltage output determined to achieve the desired output voltage. Fine-tuning multiple voltage regulators on a single chip using conventional methods results in significant test time because the correct trim code must be determined for each regulator within the memory chip. Additionally, a large amount of on-chip eFuse storage is required to hold these trim codes. Conventional methods involve using external tester circuitry to set the trim codes. This involves loading trim bits into on-chip registers, measuring an analog voltage with the tester, comparing the measured voltage to an accurate voltage reference, and adjusting the trim bits based on the comparison. This iterative process (including waiting for the voltage to stabilize and repeating the measurement and comparison until the voltage substantially approaches the target reference voltage) is inherently slow and has a significant impact on overall die cost.

[0011] To address these and other challenges, the techniques described herein introduce a built-in self-tuning engine designed to reduce testing time and cost while minimizing the need for one-time programmable (OTP) storage of the tuner codes. The circuitry described herein can incorporate multiple self-calibrating comparators or operational amplifiers, enabling on-chip tuning without external calibration tools. In some implementations, a single tuning circuit can be used to set the tuner codes for all regulators in the memory device. The tuning circuitry described herein can execute automatically upon device power-on or reset, allowing the memory device to be completely powered off after tuning is complete.

[0012] For example, the trimming circuit described herein is designed to automatically calibrate all voltage regulators to the required accuracy by adjusting their trim codes during the initial power-on sequence. To this end, the built-in self-trimming circuit described herein can automatically iterate via each memory device, using feedback from the voltage regulators to update the trim codes and store them in the voltage regulator's trim register. In some implementations, OTP circuitry (such as eFuse or other memory elements) can be used to continuously store the generated trim codes after calibration, which may reduce the overall device power-on time in some implementations.

[0013] Figure 1 illustrates a block diagram of an example memory system 100 implementing a built-in self-trimming (BIST) circuit 106 according to some embodiments of the present disclosure. The memory system 100 is shown as including a bandgap voltage generator circuit 102, a voltage reference generator circuit 104, an analog BIST circuit 106, a collection of bias generator circuits 108A-108C (sometimes generally referred to as "(multiple) bias generator circuits 108" or "(multiple) voltage regulator circuits 108"), and a memory array circuit 110. Each of the components of the memory system 100 may be part of a single memory device, for example, provided on a single semiconductor die or multiple semiconductor dies communicating with each other. The analog BIST circuit 106 may be a built-in component of the memory system rather than an external component.

[0014] The memory system 100 may include one or more logic gates and various sub-circuits that may be composed of one or more logic gates. A logic gate is an electronic device that performs logical operations on one or more input signals to generate a single output signal. Various embodiments of the circuitry and logic gates implementing the memory system 100 may include various transistors. The transistors described herein may have a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistor can be any suitable type of transistor, including but not limited to metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductors (CMOS) transistors, P-channel metal-oxide semiconductors (PMOS), N-channel metal-oxide semiconductors (NMOS), bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, P-channel and / or N-channel field effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, or similar.

[0015] The memory system 100 is shown to include a bandgap voltage generator 102. The bandgap voltage generator 102 provides a stable reference voltage, sometimes referred to as the bandgap voltage, which is relatively insensitive to temperature variations. The bandgap voltage generator 102 may include any suitable circuitry for generating the bandgap voltage. In some embodiments, the bandgap voltage generator 102 may include a combination of a transistor and resistor network connected to a forward-biased diode, which together generate a voltage proportional to the bandgap voltage of the semiconductor material of the bandgap voltage generator 102. In some embodiments, the bandgap voltage generator 102 may be incorporated into a current mirror circuit to ensure that the generated voltage remains consistent under different operating conditions. The generated bandgap voltage can then be provided to a voltage reference generator 104 to facilitate the generation of an accurate and stable reference voltage.

[0016] Memory system 100 is shown to include a bandgap voltage generator 102. A voltage reference generator 104 may receive a bandgap voltage from the bandgap voltage generator 102 and may generate one or more reference voltages, which are provided to analog BIST circuit 106 and one or more bias generator circuits 108. The voltage reference generator 104 may include various components such as operational amplifiers, resistor networks, and voltage divider circuits. In some embodiments, the voltage reference generator 104 may utilize operational amplifiers or similar circuitry that amplify the bandgap voltage and generate one or more stable reference voltages. The operational amplifier may be coupled to a resistor network to scale the bandgap voltage to a desired reference voltage level. In some embodiments, the voltage reference generator 104 may incorporate voltage divider circuitry to further refine the generated reference voltage to conform to the reference voltage inputs of analog BIST circuit 106 and bias generator circuit 108. In some embodiments, the voltage reference generator 104 may include temperature compensation circuitry to maintain the stability of the reference voltage under varying operating temperatures.

[0017] The memory system is shown as including an analog BIST circuit 106. As shown, the analog BIST circuit 106 receives a reference voltage from a voltage reference generator 104 and can generate an output trimming code (shown as "TRIM OUT") for one or more bias generator circuits 108. In some implementations, the analog BIST circuit 106 may include control circuitry that outputs a block selection signal (shown as "Block SEL") to select one or more of the bias generator circuits 108 for trimming. Further details relating to the structure of the analog BIST circuit 106 are described in conjunction with Figure 2.

[0018] The analog BIST circuit 106 facilitates the automatic generation of trim codes for one or more of the bias generator circuits 108, such that the generated bias voltage satisfies the requirement of producing an output voltage compatible with the memory array circuit 110. As shown, the analog BIST circuit 106 can receive one or more feedback voltages (here shown as "Voltage In") from the selected bias generator circuit 108, which can be used in conjunction with the trimming operation described in further detail herein. The analog BIST circuit 106 can use the received feedback voltage to iteratively generate trim codes for the selected bias generator circuit 108. The iterative process may involve adjusting the trim codes until the feedback voltage matches the reference voltage within a specified tolerance.

[0019] In some implementations, the analog BIST circuit 106 can automatically perform a fine-tuning process when the device is powered on or reset (e.g., by receiving a corresponding reset signal, power-on signal, or initialization signal). For this purpose, the control circuitry within the analog BIST circuit 106 can use a block select signal to isolate and adjust individual bias generator circuits 108, thereby sequentially selecting each of the bias generator circuits 108 for fine-tuning. The analog BIST circuit 106 can generate a fine-tuning code for each selected bias generator circuit 108 and store it in a corresponding fine-tuning register for those bias generator circuits 108.

[0020] The memory system 100 is shown to include one or more bias generator circuits 108. As shown, each bias generator circuit 108 can generate a corresponding bias voltage for a corresponding input signal of the memory array circuit 110. For this purpose, each bias generator circuit 108 can receive a corresponding reference voltage from a voltage reference generator 104, which can correspond to an individual input of the memory array circuit 110. For example, bias generator circuit 108A can receive a reference voltage corresponding to the input voltage of the write bit line of the memory array circuit 110. The bias generator circuits 108 can generate bias voltages for one or more voltage signals of the memory array circuit (including but not limited to write bit line voltage, read bit line voltage, write word line voltage, or read word line voltage, etc.). Further details related to the structure and functionality of each bias generator circuit 108 are described in conjunction with Figure 2.

[0021] As described further in detail herein, each bias generator circuit 108 may include one or more registers storing trimming codes generated by the analog BIST circuit 106. These trimming codes can be used to adjust the generated bias voltage to meet the requirements of the memory array circuit 110. In one example, the bias generator circuit 108 may include a voltage regulator circuit comprising an operational amplifier or similar component that receives trimming codes to modify the output bias voltage. As shown, each of the bias generator circuits 108 can provide voltage feedback to the analog BIST circuit 106 to facilitate trimming operations. In some implementations, a block select signal can be used to select which of the bias generator circuits 108 to be trimmed.

[0022] The memory system 100 is shown to include at least one memory array circuit 110, which can receive bias voltage signals from one or more bias generator circuits 108. The memory array circuit 110 may include an array of any number of memory elements, including but not limited to dynamic random-access memory (DRAM) cells, static random-access memory (SRAM) cells, flash memory cells, eFuse memory cells, or other types of memory cells capable of electronically storing information. The memory array circuit 110 can perform read and write operations to store and retrieve data. In some implementations, the memory array circuit 110 may include additional components, such as sense amplifiers, decoders, and input / output circuitry, to support various memory operations.

[0023] Figure 2 illustrates a block diagram of an example of a built-in self-tuning circuit 200 for calibrating a voltage regulator circuit according to some embodiments of this disclosure. The built-in self-tuning circuit 200 is shown to include a bias generator circuit 202 and an analog BIST circuit 210. The bias generator circuit 202 may be similar to the bias generator circuit 108 of Figure 1, and includes any of its structures and implements any of its functions. The analog BIST circuit 210 may be similar to the analog BIST circuit 106 of Figure 1, and includes any of its structures and implements any of its functions.

[0024] The built-in self-tuning circuit 200 may include one or more logic gates and various sub-circuits that may be composed of one or more logic gates. A logic gate is an electronic device that performs logical operations on one or more input signals to generate a single output signal. Various embodiments of the circuitry and logic gates implementing the built-in self-tuning circuit 200 may include various transistors. The transistors described herein may have a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistor may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, or the like.

[0025] The bias generator circuit 202 is shown as including a voltage regulator circuit 204, a feedback circuit 206, and a fine-tuning register circuit 208. The bias generator circuit 202 can receive a selection input (shown here as "SEL"), which is activated (e.g., in a logic high state, an active logic state, etc.) when the bias generator circuit 202 is selected for the fine-tuning operation described herein. As shown, the bias generator circuit 202 may include switches at the inputs of the fine-tuning register circuit, which close when the selection input is activated, thereby enabling modification of the fine-tuning code stored in the fine-tuning register circuit 208. The bias generator circuit 202 includes another switch at the output of the feedback circuit 206, which closes when the selection input is active, enabling the bias generator circuit 202 to output feedback from the feedback circuit 206 to the analog BIST circuit 210, as shown. The bias generator circuit 202 includes a fourth switch coupled to a voltage reference input (shown as "VREF") that, when closed (e.g., when the select input is activated), provides the voltage reference as an output to the analog BIST circuit 210, as shown.

[0026] The voltage regulator circuit 204 can be any type of voltage generation circuit, including but not limited to low-drop-out (LDO) buck converters, charge pumps, or other voltage generators. The voltage regulator circuit 204 can generate an output voltage signal (displayed as "VOUT"), which can be used as a bias voltage for memory circuits, such as the memory array circuit 110 in Figure 1. The voltage regulator circuit 204 can receive a voltage reference input and a feedback signal (displayed as "FB") generated by the feedback circuit 206. The voltage regulator circuit 204 can receive trimming codes from the trimming register circuit 208, which can be used to fine-tune the output voltage signal, as described in further detail herein.

[0027] Voltage regulator circuit 204 generates an output voltage such that the feedback signal generated by feedback circuit 206 based on the output voltage is equal to a reference voltage when affected by a trimming code. The trimming code received by voltage regulator circuit 204 can adjust internal parameters of voltage regulator circuit 204, thereby modifying the output voltage of voltage regulator circuit 204. For example, the trimming code can modify the input offset voltage of the operational amplifier within voltage regulator circuit 204, the gain of the operational amplifier within voltage regulator circuit 204, or any other parameter of any component of voltage regulator circuit 204. In some implementations, the trimming code can adjust the resistance value of resistive elements within voltage regulator circuit 204, which can affect the voltage division and thus the output voltage.

[0028] Feedback circuit 206 receives the voltage output (VOUT) of voltage regulator circuit 204 and generates a feedback signal (FB). Feedback circuit 206 may include a voltage divider or another type of circuit to precisely reduce the output voltage. For example, feedback circuit 206 may include a resistive voltage divider network that proportionally reduces the output voltage to a level suitable for comparison with a reference voltage. Feedback circuit 206 may have circuit elements (e.g., resistive voltage dividers, etc.) selected such that when the desired output voltage is generated, the resulting feedback signal is equal to the reference voltage. In some implementations, feedback circuit 206 may include additional components, such as operational amplifiers or comparators, to further refine the feedback signal and ensure its matching with the reference voltage under various operating conditions.

[0029] The trimming register circuit 208 may include one or more storage elements, such as flip-flops, latches, or other storage elements, to store trimming codes for the voltage regulator circuit 204. The trimming register circuit 208 may receive a trimming load signal (displayed as "TRIM LOAD") from the analog BIST circuit 210, indicating that trimming codes are to be written to the trimming register circuit 208. The trimming register circuit 208 may receive trimming codes (displayed as "TRIM OUT") from the analog BIST circuit 210 and store them in a flip-flop, latch, or other memory element. The trimming register circuit 208 may provide the stored trimming codes to the voltage regulator circuit 204 to adjust the output voltage.

[0030] The analog BIST circuit 210 is shown as including a first search circuit 212, a second search circuit 214, and a comparator circuit 216. Although shown herein as a comparator, it should be understood that the comparator circuit 216 may include any type of circuit capable of comparing two inputs, including but not limited to operational amplifiers. The analog BIST circuit 210 may receive a clock signal (shown as "CLK") that can synchronize the various logic components in the analog BIST circuit 210. The analog BIST circuit 210 may receive a feedback signal and a voltage reference signal from the bias generator circuit 202 as a target input (shown as "TARGET") and a reference input (shown as "REF"), respectively. The analog BIST circuit 210 may use the techniques described herein to generate trim codes via the TRIM OUT and TRIM LOAD signals.

[0031] Before generating the trim code, the analog BIST circuit 210 can perform a self-calibration process to calibrate the output of the comparator circuit 216. As shown, the analog BIST circuit 210 includes two switches at the second input of the comparator circuit 216. The first switch can be closed during the self-calibration process and can be controlled by a first calibration signal (displayed as "CAL_A"). When the first switch is closed, the second switch is open, and the first switch sets both inputs of the comparator circuit 216 to the reference voltage. The second switch can be closed during the trimming process of the bias generator circuit 202 and can be controlled by a second calibration signal (displayed as "CAL_B"). When the second switch is closed, the first switch is open (after calibration), and the second switch sets the second input of the comparator circuit 216 to the feedback voltage.

[0032] For example, the first and second calibration circuits may be provided from a control circuit, which may be part of or communicate with the analog BIST circuit 210. In some implementations, the comparator circuit 216 may include an enable input that can receive an enable signal that enables the comparator circuit 216 to generate an output. The comparator circuit 216 may operate as an error amplifier to amplify a small voltage difference between its first and second inputs into an output error signal (shown herein as "UP") for self-calibration and / or generating trimming codes according to the techniques described herein.

[0033] To perform calibration, the first calibration signal can be set to an active logic state, and the second calibration signal can be set to an inactive logic state, so that both inputs of the comparator circuit 216 receive a voltage reference signal (e.g., an equal voltage signal). During the self-calibration process, the output of the comparator circuit 216 can indicate the internal error of the comparator circuit 216, which will be compensated by a second trimming code (shown here as "TRIM2") generated using the second search circuit 214.

[0034] The first search circuit 212 and the second search circuit 214 may each be a circuit that performs a search operation to generate a trim code. In some embodiments, the first search circuit 212 and the second search circuit 214 may be decision tree circuits that perform a binary search operation. Further details of the binary search operation are described in conjunction with Figure 8. In some embodiments, the first search circuit 212 and the second search circuit 214 may each be a counter circuit that performs a linear search operation. Further details of the linear search operation are described in conjunction with Figure 9.

[0035] To perform self-calibration, the second search circuit 214 can iteratively apply a search algorithm (e.g., binary search, linear search) to converge to the trim code for the comparator circuit 216. At the start of the self-calibration process, the second search circuit 214 can be initialized to include an initial set of trim codes (e.g., stored in an internal register and provided as output), which can be iteratively adjusted based on the output of the comparator circuit 216 over various clock cycles (or sets of clock cycles). If the comparator circuit 216 outputs logic high, the second search circuit 214 can adjust the trim code to decrease the detected voltage difference. Conversely, if the comparator circuit 216 outputs logic low, the second search circuit 214 can adjust the trim code to increase the detected voltage difference. The second search circuit 214 can update a second trim value (e.g., the trim code) until the comparator circuit 216 alternates between logic high and logic low outputs, indicating that the detected voltage difference of the input detected by the comparator circuit 216 has been minimized. Once this situation is detected, the second search circuit 214 and / or control circuit can generate a signal indicating that the comparison circuit 216 has been calibrated.

[0036] Once the self-calibration of the comparator circuit 216 has been performed, the first search circuit 212 can be used to generate a trim code for the voltage regulator circuit 204. For this purpose, the first calibration signal can be set to an inactive logic state, and the second calibration signal can be set to an active logic state. This causes the first input of the comparator circuit 216 to receive a voltage reference signal, and the second input of the comparator circuit 216 to receive a feedback signal (e.g., via the TARGET input port of the analog BIST circuit 210). During the calibration process of the voltage regulator circuit 204, the output of the comparator circuit 216 can indicate an internal error of the comparator circuit 216, which will be compensated for by using the trim code generated by the second search circuit 214 as a TRIM OUT signal.

[0037] To perform calibration of the voltage regulator circuit 204, the first search circuit 212 can iteratively apply a search algorithm (e.g., binary search, linear search) to converge to a trim code for the voltage regulator circuit 204. At the start of the calibration process, the first search circuit 212 can be initialized to store an initial trim code (e.g., stored in an internal register and provided as an output), which can be iteratively adjusted based on the output of the comparator circuit 216 over various clock cycles (or sets of clock cycles). The first search circuit 212 can generate a trim code for the search operation over various clock cycles (or sets of clock cycles) and can automatically assert a trim load (displayed as "TRIM LOAD") signal to write the trim code to the storage element of the trim register circuit 208.

[0038] The trim code written to the trim register circuit 208 causes the voltage regulator circuit 204 to change its output voltage, thereby causing a corresponding change in the feedback signal generated by the feedback circuit 206. The feedback signal is then provided to the comparator circuit 216 for comparison over one or more subsequent clock cycles. If the comparator circuit 216 outputs a logic high, the first search circuit 212 can adjust the trim code to reduce the detected voltage difference. Conversely, if the comparator circuit 216 outputs a logic low, the first search circuit 212 can adjust the trim code to increase the detected voltage difference. The second search circuit 214 can iteratively update the trim code provided to the bias generator circuit 202 until the comparator circuit 216 alternates between logic high and logic low outputs, indicating that the detected voltage difference of the input detected by the comparator circuit 216 has been minimized. Once this condition is detected, the first search circuit 212 and / or the control circuit can generate a signal indicating that the voltage regulator 204 has been calibrated.

[0039] Figure 3 illustrates a block diagram of an example memory system 300, including the example of the built-in fine-tuning circuitry of Figure 2, configured for calibrating multiple voltage regulator circuits according to some embodiments of the present disclosure. The memory system 300 is shown as including an analog BIST circuit 302 and one or more bias generator circuits 304A-304B (sometimes generally referred to as "(multiple) bias generator circuits 304"). The analog BIST circuit 302 may be similar to the analog BIST circuit 210 of Figure 2, and includes any of its structure and implements any of its functionality. Each of the bias generator circuits 304 may be similar to the bias generator circuit 202 of Figure 2, and includes any of its structure and implements any of its functionality. The analog BIST circuit 302 may perform iterative calibration of each of the bias generator circuits 304. In some implementations, analog BIST circuit 302 may perform a self-calibration process similar to that described in conjunction with Figure 2 before performing calibration of bias generator circuit 304.

[0040] The memory system 300 may include one or more logic gates and various sub-circuits that may be composed of one or more logic gates. A logic gate is an electronic device that performs logical operations on one or more input signals to generate a single output signal. Various embodiments of the circuitry and logic gates implementing the memory system 300 may include various transistors. The transistors described herein may have a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, or the like.

[0041] Each of the bias generator circuits 304 may include an individual selection signal (shown here as "SEL1" for bias generator circuit 304A and "SEL2" for bias generator circuit 304B). Although two bias generator circuits 304 are shown here, it should be understood that any number of bias generator circuits 304 may exist, each with a corresponding selection signal and voltage reference signal. After calibrating the analog BIST circuit 302, one of the bias generator circuits 304 can be selected, while the others can be deselected. For example, the selection of the bias generator circuit 304 can be performed by control circuitry or by the analog BIST circuit 302. As described in conjunction with Figure 2, the selection of a bias generator circuit 304 allows the feedback signal and voltage reference from that bias generator circuit 304 to serve as the target input and voltage reference for the calibration process.

[0042] The analog BIST circuit 302 can perform calibration using the technique described in conjunction with Figure 2, where a feedback signal is compared to a reference voltage, generating appropriate trim codes for the selected bias generator circuit 304. Once the calibration process for the selected bias generator circuit 304 is complete, the calibrated bias generator circuit 304 can be deselected, and the next uncalibrated bias generator circuit 304 can be selected for calibration. This iterative process can be repeated until all bias generator circuits 304 have been calibrated. During each iteration, the analog BIST circuit 302 can generate and store appropriate trim codes for the selected bias generator circuit 304. The trim codes can be used to adjust the output voltage of each bias generator circuit 304 to ensure that the feedback signal matches the voltage reference within a specified tolerance.

[0043] Figure 4 illustrates a block diagram of an example of a built-in self-tuning circuit 400 for calibrating a voltage regulator circuit based on a direct voltage output, according to some embodiments of this disclosure. The built-in self-tuning circuit 400 is shown to include a bias generator circuit 402 and an analog BIST circuit 410. The bias generator circuit 402 may be similar to the bias generator circuit 202 of Figure 2, and includes any of its structures and implements any of its functionalities. The analog BIST circuit 410 may be similar to the analog BIST circuit 210 of Figure 2, and includes any of its structures and implements any of its functionalities.

[0044] The built-in self-tuning circuit 400 may include one or more logic gates and various sub-circuits that may be composed of one or more logic gates. A logic gate is an electronic device that performs logical operations on one or more input signals to generate a single output signal. Various embodiments of the circuitry and logic gates implementing the built-in self-tuning circuit 400 may include various transistors. The transistors described herein may have a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistor may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, or the like.

[0045] The bias generator circuit 402 is shown as including a voltage regulator circuit 404, a feedback circuit 406, and a trimmer register circuit 408, which may be similar to the voltage regulator circuit 204, feedback circuit 206, and trimmer register circuit 208 of Figure 2, and may include any of these structures and implement any of these functions. The analog BIST circuit 410 is shown as including a comparator circuit 416, a first search circuit 412, and a second circuit 414, each of which may be similar to the comparator circuit 216, first search circuit 212, and second circuit 214 of Figure 2, and may include any of these structures and implement any of these functions.

[0046] In the example's built-in fine-tuning circuit 400, the output voltage of the voltage regulator circuit 404 can be provided as a feedback / target input signal, rather than providing the output of the feedback circuit 406 as a feedback signal (e.g., a target input signal) to the analog BIST circuit 410. To compensate for voltage differences, two reference voltages can be used. A first voltage reference (shown as "VREF1") can be used as an input to the bias generator circuit 402, to be compared with the feedback signal generated by the feedback circuit 406, similar to the voltage reference described in conjunction with Figure 2. A second voltage reference (shown as "VREF2") can be provided to the analog BIST circuit 410 for comparison with the output voltage of the bias generator circuit 402. As shown, the output of the voltage regulator circuit 404, in addition to providing the output voltage of the bias generator circuit 402, is also coupled to a switch controlled by a selection signal. If the selection signal is active, the switch closes, thereby providing an output voltage to the analog BIST circuit 410 as a target input signal.

[0047] Figure 5 illustrates a block diagram of an example memory system 500, including the built-in fine-tuning circuitry of Figure 4, for calibrating multiple voltage regulator circuits according to some embodiments of the present disclosure. The memory system 500 is shown as including an analog BIST circuit 502 and one or more bias generator circuits 504A-504B (sometimes generally referred to as "(multiple) bias generator circuits 504"). The analog BIST circuit 502 may be similar to the analog BIST circuit 410 of Figure 4, and includes any of its structure and implements any of its functionality. Each of the bias generator circuits 504 may be similar to the bias generator circuit 402 of Figure 4, and includes any of its structure and implements any of its functionality. The analog BIST circuit 502 may perform iterative calibration of each of the bias generator circuits 504. In some implementations, analog BIST circuit 502 may perform a self-calibration process similar to that described in conjunction with Figure 2 before performing calibration of bias generator circuit 504.

[0048] Memory system 500 may include one or more logic gates and various sub-circuits that may be composed of one or more logic gates. A logic gate is an electronic device that performs logical operations on one or more input signals to generate a single output signal. Various embodiments of the circuitry and logic gates implementing memory system 500 may include various transistors. The transistors described herein may have a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, and the like.

[0049] Memory system 500 may be similar to memory system 300 in Figure 3, except that it includes the analog BIST circuit and bias generator circuit described in conjunction with Figure 4. Similar to the configuration shown in Figure 3, each of the bias generator circuits 504 may include an individual selection signal (shown here as "SEL1" for bias generator circuit 504A and "SEL2" for bias generator circuit 504B). Although two bias generator circuits 504 are shown here, it should be understood that any number of bias generator circuits 504 may exist, each with a corresponding selection signal and voltage reference signal. After calibrating the analog BIST circuit 502, one of the bias generator circuits 504 can be selected, while the others are deselected. For example, the selection of the bias generator circuits 504 can be performed by control circuitry or by the analog BIST circuit 502. As illustrated in Figure 4, the selection of bias generator circuit 504 allows its output voltage to serve as the target input for analog BIST circuit 502 (shown here as "Vout_1_FB" for bias generator circuit 504A and "Vout_2_FB" for bias generator circuit 504B). Additionally, the control circuitry can match the voltage reference provided as input to analog BIST circuit 502 with the target voltage to be calibrated by the selected bias generator circuit 504.

[0050] The analog BIST circuit 502 can perform calibration using the technique described in conjunction with Figure 2, wherein the voltage output of the selected bias generator circuit 504 is compared with an input voltage reference to generate appropriate trim codes for the selected bias generator circuit 504. Once the calibration process for the selected bias generator circuit 504 is complete, the calibrated bias generator circuit 504 can be deselected, and the next uncalibrated bias generator circuit 504 can be selected for calibration. This iterative process can be repeated until all of the bias generator circuits 504 have been calibrated. During each iteration, the analog BIST circuit 502 can generate and store appropriate trim codes for the selected bias generator circuit 504. The trim codes can be used to adjust the output voltage of each bias generator circuit 504 to ensure that the feedback signal matches the voltage reference within a specified tolerance, as described herein.

[0051] Figure 6 illustrates a block diagram of another example of a memory system 600 implementing a built-in self-tuning circuit for a voltage regulator circuit using a one-time programmable memory circuit according to some embodiments of the present disclosure. The memory system 600 may be similar to the memory system 100 of Figure 1. The memory system 600 is shown as including a bandgap voltage generator circuit 602, a voltage reference generator circuit 604, an analog BIST circuit 606, a collection of bias generator circuits 608A-608C (sometimes generally referred to as "(multiple) bias generator circuits 608" or "(multiple) voltage regulator circuits 608"), a memory array circuit 610, a data circuit 612, an OTP circuit 614, and a controller 616.

[0052] Memory system 600 may include one or more logic gates and various sub-circuits that may be composed of one or more logic gates. A logic gate is an electronic device that performs logical operations on one or more input signals to generate a single output signal. Various embodiments of the circuitry and logic gates implementing memory system 600 may include various transistors. The transistors described herein may have a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, or the like.

[0053] Each of the bandgap voltage generator circuit 602, voltage reference generator circuit 604, analog BIST circuit 606, bias generator circuit set 608, and memory array circuit 610 may resemble the bandgap voltage generator circuit 102, voltage reference generator circuit 104, analog BIST circuit 106, bias generator circuit set 108, and memory array circuit 110 of Figure 1, and may include any of their structures and implement any of their functionalities. In the configuration shown in Figure 6, the analog BIST circuit 606 may access the voltage output of the bias generator circuit in a manner similar to that described in conjunction with Figure 4. However, it should be understood that in some implementations, the analog BIST circuit 606 may use a feedback signal from a feedback circuit, as described in conjunction with Figure 2.

[0054] Memory system 600 can operate in a similar manner to memory system 100 of Figure 1, and additionally includes persistent memory to store calculated trim codes for one or more of the bias generator circuits 608. Storing the trim codes in persistent memory allows memory system 600 to initialize bias generator circuits 608 with the trim codes during startup / reset without recalibrating bias generator circuits 608. This method reduces the time required to initialize bias generator circuits 608 for use with memory array circuits 610, because the trim codes can be provided from persistent memory instead of being generated each time memory system 600 is reset or reinitialized.

[0055] To implement these techniques, the analog BIST circuit 606 can perform initial calibration on each of the bias generator circuits 608 to generate trim codes for storage in persistent memory elements. Calibration can be performed using methods similar to those described herein. In this example, the controller 616 can control a block selection signal (e.g., a "Block SEL" signal) to iteratively select each of the bias generator circuits 608. The analog BIST circuit 606 can perform the calibration techniques described herein to iteratively generate adjustment trim codes (shown here as "TRIM OUT") to the selected bias generator circuit 608. The trim codes can be provided from the analog BIST circuit 606 through data circuitry 612, which also controls read / write operations to the OTP circuit 614. In addition to providing the block selection signal, the controller 616 can also provide an address signal corresponding to the selected bias generator circuit 608 as an input to the OTP circuit 614.

[0056] Once the optimal trim code for the selected bias generator 608 is determined, the data circuit 612 can automatically perform a write operation (e.g., in response to a signal from the controller 616 and / or the analog BIST circuit 606 indicating that the calibration process is complete). The write operation allows the persistent memory elements of the OTP circuit 614 to be updated with the trim code determined for the selected bias generator circuit 608. The controller 616 can then select the next uncalibrated bias generator circuit 608 and repeat the calibration process until all bias generator circuits 608 have been calibrated and the corresponding trim code has been written to the OTP circuit 614.

[0057] OTP circuit 614 may include any type of persistent memory element, including but not limited to OTP memory elements, eFuse memory elements, flash memory, or any other type of memory that can store trim codes for bias generator circuit 608. OTP circuit 614 may include a control circuitry system to facilitate read and write operations through data circuit 612 and controller 616. Once OTP circuit 614 has been updated to include trim codes for each of the bias generator circuits 608, subsequent resets and / or initializations of bias generator circuit 608 do not necessarily require calibration.

[0058] For example, to initialize bias generator circuit 608 with a trim code, controller 616 may iteratively provide block selection signals to each of the bias generator circuits 608 and provide corresponding address signals to OTP circuit 614. To initialize the selected bias generator circuit 608, data circuit 612 may issue a read operation to retrieve the trim code stored in OTP circuit 614 and provide the retrieved trim code to the selected bias generator circuit 608 to update its trim register circuitry. This may be repeated until all trim registers in bias generator circuit 608 are updated to include the previously generated trim code stored in OTP circuit 614. In some implementations, OTP circuit 614 may include rewritable memory elements. In such implementations, bias generator circuit 608 may be recalibrated in response to a corresponding signal (e.g., from external circuitry) to update OTP circuit 614 with the updated trim code of bias generator circuit 608.

[0059] Figure 7 illustrates a block diagram of an example memory system 700 for calibrating multiple voltage regulator circuits using a one-time programmable memory circuit according to some embodiments of the present disclosure. The memory system 700 may be similar to the memory system 500 of Figure 5. The memory system 700 is shown as including an analog BIST circuit 702 and one or more bias generator circuits 704A-704B (sometimes generally referred to as "(multiple) bias generator circuits 704"). The analog BIST circuit 702 may be similar to the analog BIST circuit 510 of Figure 5, and includes any of its structure and implements any of its functionality. Each of the bias generator circuits 704 may be similar to the bias generator circuit 504 of Figure 5, and includes any of its structure and implements any of its functionality. The analog BIST circuit 702 may perform iterative calibration of each of the bias generator circuits 704. In some implementations, analog BIST circuit 702 may perform a self-calibration process similar to that described in conjunction with Figure 2 before performing calibration of bias generator circuit 704.

[0060] The memory system 700 may include one or more logic gates and various sub-circuits that may be composed of one or more logic gates. A logic gate is an electronic device that performs logical operations on one or more input signals to generate a single output signal. Various embodiments of the circuitry and logic gates implementing the memory system 700 may include various transistors. The transistors described herein may have a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, or the like.

[0061] Memory system 700 is similar to memory system 500, and further includes data / controller circuitry 706 and OTP circuitry 708. Data / controller circuitry 706 may be similar to controller circuitry 616 and / or data circuitry 612 of memory circuitry 600 in Figure 6, and includes any of its structure and implements any of its functionality. OTP circuitry 708 may be similar to OTP circuitry 614 of memory system 600 in Figure 6, and includes any of its structure and implements any of its functionality. As shown, analog BIST circuitry 702 provides trim codes (displayed as "TRIM OUT", and corresponding to the "TRIM LOAD" signal indicating write) to data / controller circuitry 706, rather than directly providing output trim codes to one of the selected bias generator circuits 704.

[0062] As described in conjunction with Figure 6, during the calibration phase for bias generator circuit 704 (e.g., before the trim code is written to OTP circuit 708), data / controller circuit 706 may provide trim codes to the selected bias generator circuit 704. Once the optimal trim code for the selected bias generator circuit 704 is identified, data / controller circuit 706 may write the trim code to the corresponding memory element in OTP circuit 708. This process may be repeated for each of the bias generator circuits 704. Data / controller circuit 706 may automatically retrieve the stored trim codes from OTP circuit 708 and provide them to the corresponding bias generator circuit 704 (e.g., for storage in trim register circuits as described herein), rather than recalibrating the bias generator circuits 704 during device reset or startup.

[0063] Figure 8 illustrates a schematic diagram of an example binary search process 800 that can be implemented via one or more circuits described herein, according to some embodiments of this disclosure. For example, the binary search process 800 can be implemented as any of the search circuits described herein (e.g., first search circuit 212 or second search circuit 214, first search circuit 412 or second search circuit 414, etc.). For example, the binary search process 800 can be implemented using a decision tree circuit.

[0064] The schematic diagram shown in Figure 8 illustrates a binary search process 800 over five clock cycles, as illustrated by individual values ​​of the CLK signal. Each clock cycle of the binary search process 800 is represented as a number row. The "X" provided on the number row indicates the "target" value being searched (the number determined by the binary search process 800). The search value (displayed as "TRIM") is illustrated in binary and decimal format below the number row, representing the search operation value for the corresponding clock cycle. In this example, the trim code has a four-bit resolution, so the search space (represented by the number rows) can include up to sixteen values, ranging from zero to fifteen. However, it should be understood that any suitable resolution of the trim code described herein can be used.

[0065] In the first iteration of the binary search process 800 (where CLK has a value of zero), the trim code is initialized to the midpoint of the search space (in binary representation, the most significant bit is set to one, and all other bits are set to zero), which in this instance is the value eight. In Figure 8, the search values ​​for each clock cycle are represented as circles on the number row. As described herein, the trim code for eight is provided to a trim register circuit (e.g., trim register circuit 208) to adjust the output voltage of a voltage regulator (e.g., voltage regulator 204).

[0066] In the next iteration (e.g., CLK=1), the output voltage (or the resulting feedback signal) is compared with the reference voltage. If the output voltage is less than the reference voltage, the most significant bit of the trim code (e.g., a bit from the previous clock cycle) can remain binary "1", and the next most significant bit can be set to one. If the output voltage is less than the reference voltage, the most significant bit of the trim code (e.g., a bit from the previous clock cycle) can be set to binary "0", and the next most significant bit can be set to binary "1". In this example, the output voltage is less than the reference voltage, and the trim code is set to twelve (binary "1100").

[0067] In the next iteration (e.g., CLK=2), the output voltage (or the resulting feedback signal) is again compared to the reference voltage. If the output voltage is less than the reference voltage, the bit modified in the previous clock cycle of the trim code (e.g., the second most significant bit) can remain binary "1", and the next most significant bit can be set to one. If the output voltage is greater than the reference voltage, the bit modified in the previous clock cycle of the trim code (e.g., the second most significant bit) can be set to binary "0", and the next most significant bit can be set to binary "1". In this example, the output voltage is again less than the reference voltage, and the trim code is set to fourteen (binary "1110").

[0068] In the next iteration (e.g., CLK=3), the output voltage (or the resulting feedback signal) is again compared to the reference voltage. If the output voltage is less than the reference voltage, the bit modified in the previous clock cycle of the trim code (e.g., the third most significant bit) remains binary "1", and the next most significant bit is set to one. If the output voltage is greater than the reference voltage, the bit modified in the previous clock cycle of the trim code (e.g., the third most significant bit) is set to binary "0", and the next most significant bit is set to binary "1". In this example, the output voltage is greater than the reference voltage (as shown by the circle above "X"), and the trim code is set to thirteen (binary "1101").

[0069] This process is repeated in subsequent iterations until the least significant bit of the trim code switches between iterations, as shown by clock cycles CLK=4 and CLK=5, indicating that the search is complete. The binary search process 800 for 2N trim codes can be completed within N clock cycles as the binary search operation iteratively modifies the values ​​of each bit in the trim code. In this example, since there may be sixteen trim codes, the search is completed in four clock cycles (e.g., at CLK=4), where the trim code is set to 12 (binary "1100").

[0070] Figure 9 illustrates a schematic diagram of an example linear search process 900 that can be implemented via one or more circuits described herein, according to some embodiments of this disclosure. For example, the linear search process 900 can be implemented as any of the search circuits described herein (e.g., first search circuit 212 or second search circuit 214, first search circuit 412 or second search circuit 414, etc.). For example, the linear search process 900 can be implemented using a counter circuit.

[0071] Figure 9 illustrates a linear search process 900 over five clock cycles, as shown by individual values ​​of the CLK signal. Each clock cycle of the linear search process 900 is represented as a number row. The "X" provided on the number row indicates the "target" value being searched (the number determined by the linear search process 900). The search value (displayed as "TRIM") is illustrated in binary and decimal format below the number row, representing the value generated from the search operation (e.g., a trim code) for the corresponding clock cycle. In this example, the trim code has a four-bit resolution, so the search space (represented by the number rows) can include up to sixteen values, ranging from zero to fifteen. However, it should be understood that any suitable resolution of the trim code described herein can be used.

[0072] In the first iteration of the linear search process 900 (where CLK has a value of zero), the trim code is initialized to the midpoint of the search space (in binary representation, the most significant bit is set to one, and all other bits are set to zero), which in this instance is the value eight. In Figure 9, the search values ​​for each clock cycle are represented as circles on the number row. As described herein, the trim code for eight is provided to a trim register circuit (e.g., trim register circuit 208) to adjust the output voltage of a voltage regulator (e.g., voltage regulator 204).

[0073] In the next iteration (e.g., CLK=1), the output voltage (or the resulting feedback signal) is compared with the reference voltage. If the output voltage is less than the reference voltage, the trim code is incremented by one. If the output voltage is greater than the reference voltage, the trim code is decremented by one. In this example, the output voltage is less than the reference voltage, and the trim code is set to nine (binary "1001"). This process is repeated iteratively until the search direction changes. This indicates that the linear search process 900 has been completed. In this example, the linear search operation continued for five clock cycles, incrementing the trim code to thirteen (binary "1101"), after which the search direction changed (e.g., the output voltage is greater than the reference voltage).

[0074] Referring to Figure 10, a flowchart illustrating an example method 1000 of operating the disclosed circuitry described herein according to some embodiments of this disclosure is shown. Method 1000 can be used to perform self-fine-tuning of a bias generator circuitry according to the techniques described herein. Method 1000 can be performed in conjunction with any of the systems, devices, circuits, or components described herein. It should be understood that additional operations may be provided before, during, and after method 1000 in Figure 10, and only a few other operations may be briefly described herein.

[0075] In brief, method 1000 begins with operation 1002, which includes calibrating a built-in self-adjusting circuit (e.g., analogous to BIST circuits 106, 210, 302, 410, 502, 606, 702, etc.) using a first search operation (e.g., in conjunction with the search operations described in Figures 8 and 9). Method 1000 continues with operation 1004, which includes determining a fine-tuning value (e.g., a fine-tuning code) for a bias generator circuit (e.g., bias generator circuits 108, 202, 304, 402, 504, 608, 704, etc.) using the built-in self-adjusting circuit and a second search operation. Method 1000 continues with operation 1006, which includes generating a voltage (e.g., WBL, RBL, WWL, RWL, etc.) for at least one control input in the memory array of the memory device using the bias generator circuit.

[0076] Referring to operation 1002, method 1000 may include calibrating a built-in self-adjusting circuit (e.g., analogous to BIST circuits 106, 210, 302, 410, 502, 606, 702, etc.) using a first search operation (e.g., the search operation described in conjunction with Figures 8 and 9). By performing a self-calibration process, the built-in self-calibrating circuit can be used to calibrate the built-in self-adjusting circuit, as described in conjunction with Figure 2. For this purpose, the built-in self-adjusting circuit can use a comparator circuit (e.g., comparator circuit 216, comparator circuit 416, etc.) to compare the same voltage to determine if there is an offset. The search operation (e.g., the binary search operation described in conjunction with Figure 8, the linear search operation described in conjunction with Figure 9) can be performed using a search circuit (e.g., second search circuit 214, second search circuit 414, etc.) to determine an adjustment code for the comparator circuit of the built-in self-adjusting circuit, which minimizes the voltage offset between the inputs of the comparator circuit, as described herein.

[0077] Referring to operation 1004, method 1000 may include using a built-in self-adjusting circuit and a second search operation to determine a fine-tuning value (e.g., a fine-tuning code) for a bias generator circuit (e.g., bias generator circuits 108, 202, 304, 402, 504, 608, 704, etc.). Once the built-in self-adjusting circuit has been calibrated, it can be used to determine the adjustment code for one or more bias generator circuits. As described herein, the bias generator circuit may include a voltage regulator that generates a stable output voltage based on an input reference voltage. A fine-tuning code may be provided to the voltage regulator (e.g., stored in a fine-tuning register circuit 208, 408, etc.) to tune the output of the voltage regulator. For example, an input voltage offset of the voltage regulator's comparator circuit (e.g., an operational amplifier, etc.) may cause the voltage regulator's output voltage to deviate from a target value. A fine-tuning code provided to the voltage regulator may be selected to compensate for this offset, thereby enabling the voltage regulator to generate a target output voltage.

[0078] To determine the trim code for the voltage regulator, the built-in self-tune circuitry can perform a search operation (e.g., using first search circuits 212, 412, etc.), as described in conjunction with Figure 2. The search operation can be a binary search operation as described in conjunction with Figure 8, a linear search operation as described in conjunction with Figure 9, or any other type of search operation. The search operation can iteratively generate candidate trim codes for the voltage regulator, causing the voltage regulator output to receive the voltage (or feedback signal) by the built-in self-tune circuitry. The built-in self-tune circuitry can use the comparator circuitry (e.g., comparator circuits 216, 416) calibrated in step 1002 to compare the output of the bias generator circuitry with a voltage reference. The built-in self-tune circuitry can automatically update the trim code as described herein to minimize comparisons, as described herein. This process can be repeated until a stopping condition is met. In some implementations, the trim code of the bias generator circuitry can be stored in persistent memory elements (e.g., OTP circuitry 614, OTP circuitry 708). In some implementations, as described herein, the built-in self-tuning circuitry can iteratively generate tuning codes for multiple bias generator circuits.

[0079] Referring to operation 1006, method 1000 may include using a bias generator circuit to generate a voltage (e.g., WBL, RBL, WWL, RWL, etc.) for at least one control input in the memory array of the memory device. As described in conjunction with Figure 1, once calibrated, the bias generator circuit can be used to generate a bias voltage for the control input of the memory array circuit. For this purpose, the bias generator circuit may receive one or more corresponding reference voltages. The bias generator circuit may use the reference voltage to generate an output voltage using a voltage regulator tuned according to the trim code generated at step 1004. The output voltage may be provided to at least one control input in the memory device (e.g., memory array circuits 110, 610) to facilitate memory operation.

[0080] One embodiment of this disclosure discloses a system with a built-in self-adjusting device. The system includes memory circuitry, a plurality of bias generator circuits, and a built-in self-adjusting circuit, each bias generator circuit corresponding to an individual input of the memory circuitry. The built-in self-adjusting circuit receives a feedback signal from a first bias generator circuit among the plurality of bias generator circuits. Based on the feedback signal and a voltage reference, the built-in self-adjusting circuit generates a fine-tuning code for the first bias generator circuit, causing the first bias generator circuit to generate an output voltage for an individual input of the memory array.

[0081] In some embodiments, a voltage reference generator circuit is further included, which is used to generate a plurality of voltage references respectively corresponding to the bias generator circuit.

[0082] In some embodiments, the built-in self-adjusting circuitry is further used to iteratively generate a plurality of adjustment codes for the first bias generator circuitry using a search operation.

[0083] In some embodiments, the search operation includes a binary search operation or a linear search operation.

[0084] In some embodiments, a one-time programmable (OTP) memory circuit is further included, wherein a built-in self-tuning circuit is further used to provide a tuning code for storage in the one-time programmable memory circuit.

[0085] In some embodiments, the first bias generator circuit includes a feedback circuit for generating a feedback signal based on the output voltage of the first bias generator circuit.

[0086] In some embodiments, the first bias generator circuit includes a switch for providing the output voltage of the first bias generator circuit as a feedback signal.

[0087] In some embodiments, the built-in self-adjusting circuitry is further used to perform a self-calibration process before generating the adjustment code.

[0088] In some embodiments, the built-in self-adjusting circuitry is used to generate a write signal to store the adjustment code in the adjustment register of the first bias generator circuit.

[0089] In some embodiments, the built-in self-adjusting circuitry and the memory circuitry are defined on the same semiconductor die.

[0090] In another embodiment of this disclosure, a built-in self-adjusting device is disclosed. The built-in self-adjusting device includes a comparator circuit, a first search circuit coupled to the comparator circuit, and a second search circuit for generating a trim code for a bias generator circuit based on the output of the comparator circuit, wherein the output is generated based on a feedback signal from the bias generator circuit.

[0091] In some embodiments, the first search circuit is used to generate a second trim code for the comparison circuit during the self-calibration process.

[0092] In some embodiments, a first switch is further included, which is configured to enable a first input and a second input of the comparator circuit to receive a voltage reference signal during the self-calibration process.

[0093] In some embodiments, a second switch is further included, which is configured to cause the first input of the comparator circuit to receive a voltage reference signal and the second input of the comparator circuit to receive a feedback signal during a calibration process for the bias generator circuit.

[0094] In some embodiments, the comparison circuitry includes either a comparator or an operational amplifier.

[0095] In some embodiments, the comparator circuit includes an input port for receiving a second trimming code corresponding to a voltage offset of the comparator circuit.

[0096] In some embodiments, the second search circuit is further configured to generate a write signal for the fine-tuning register of the bias generator circuit.

[0097] In some embodiments, the second search circuit is further configured to generate a plurality of candidate trim codes for the bias generator circuit.

[0098] In yet another embodiment of this disclosure, a method for operating a built-in self-adjusting device is disclosed. The method includes calibrating the built-in self-adjusting circuitry of a memory device using a first search operation. The method includes using the built-in self-adjusting circuitry and a second search operation to determine a trimming code for a bias generator circuitry of the memory device. The method includes using the bias generator circuitry to generate a voltage for at least one control input in a memory array of the memory device.

[0099] In some embodiments, the method further includes the step of generating a plurality of candidate trim codes for the bias generator circuit based on a feedback signal from the bias generator circuit using a built-in self-tune circuit.

[0100] As used herein, the terms "about" and "approximately" generally mean plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0101] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

[0102] 100: Memory System 100: Memory System 102: Bandgap voltage generator circuit 104: Voltage Reference Generator Circuit 106: Analogous to BIST circuits 108A~108C: Bias Generator Circuit 110: Memory Array Circuit 200: Built-in self-adjusting circuit 202: Bias Generator Circuit 204: Voltage Regulator Circuit 206: Feedback Circuit 208: Fine-tuning register circuit 210: Analogous to BIST circuits 212: First search circuit 214: Second Search Circuit 216: Comparator Circuit 300: Memory System 302: Analogous BIST Circuit 304A~304B: Bias Generator Circuit 400: Built-in self-adjusting circuit 402: Bias Generator Circuit 404: Voltage Regulator Circuit 406: Feedback Circuit 408: Fine-tuning register circuit 410: Analogous to BIST circuits 412: First search circuit 414: Second Search Circuit 416: Comparator Circuit 500: Memory System 502: Analogous BIST Circuit 504A~504B: Bias Generator Circuit 600: Memory System 602: Bandgap voltage generator circuit 604: Voltage Reference Generator Circuit 606: Analogous to BIST circuits 608A~608C: Bias Generator Circuit 610: Memory Array Circuit 612: Data Circuit 614: OTP circuit 616: Controller 700: Memory System 702: Analogous BIST Circuit 704A~704B: Bias Generator Circuit 706: Data / Controller Circuit 708: OTP circuit 800: Binary Search Process 900: Linear Search Process 1000: Method 1002~1006: Operation Block SEL: Block Select Signal CAL_A: First calibration signal CAL_B: Second calibration signal CLK: Clock signal / clock cycle EN: Enable signal FB: Feedback Signal REF: Reference Input SEL: Select Input SEL1: Individual Selection Signal SEL2: Individual Selection Signal TARGET: Target Input TRIM: Microcode / Search Value TRIM LOAD: Fine-tuning the load signal TRIM OUT: Trimmer code / Output trimmer code / Adjust trimmer code TRIM2: Second fine-tuning code UP: Output error signal VBG: Voltage Voltage Input: Voltage input Vout_1: Output voltage Vout_1_FB: Target Input Vout_2: Output voltage Vout_2_FB: Target Input VREF: Voltage Reference Input VREF Input: Voltage Reference Input VREF1: First voltage reference VREF2: Second voltage reference WBL, RBL, WWL, RWL: Voltage

Claims

1. A system with a built-in self-adjusting device, comprising: a memory circuit; a plurality of bias generator circuits, each of the bias generator circuits corresponding to an individual input of the memory circuit; and a built-in self-adjusting circuit for: receiving a feedback signal from a first bias generator circuit of the bias generator circuits; generating a trimming code for the first bias generator circuit based on the feedback signal and a voltage reference, causing the first bias generator circuit to generate an output voltage for the individual input of the memory circuit; and iteratively generating a plurality of trimming codes for the first bias generator circuit using a search operation, wherein the search operation includes a binary search operation.

2. The system as described in claim 1, further comprising a voltage reference generator circuit for generating a plurality of voltage references respectively corresponding to the bias generator circuits.

3. The system as claimed in claim 1, wherein the built-in self-adjusting circuitry is further configured to: perform a self-calibration process before generating the adjustment code; and generate a write signal to store the adjustment code in an adjustment register of the first bias generator circuit.

4. The system as described in claim 1, further comprising a one-time programmable memory circuit, wherein the built-in self-adjusting circuitry is further configured to provide the adjustment code for storage in the one-time programmable memory circuit.

5. The system as claimed in claim 1, wherein the first bias generator circuit includes a feedback circuit for generating the feedback signal based on the output voltage of the first bias generator circuit.

6. The system as claimed in claim 1, wherein the first bias generator circuit includes a switch for providing the output voltage of the first bias generator circuit as the feedback signal.

7. The system as described in claim 1, wherein the built-in self-adjusting circuitry is further used to perform a self-calibration process before generating the adjustment code.

8. The system as described in claim 1, wherein the built-in self-tuning circuitry and the memory circuitry are defined on the same semiconductor die.

9. A built-in self-adjusting device comprising: a comparator circuit; a first search circuit coupled to the comparator circuit; and a second search circuit configured to: generate a trim code for a bias generator circuit based on an output of the comparator circuit, wherein the output is generated based on a feedback signal from the bias generator circuit; and iteratively generate a plurality of trim codes for the bias generator circuit using a search operation, wherein the search operation includes a binary search operation.

10. A method of operating a built-in self-tuning device, comprising the steps of: calibrating a built-in self-tuning circuit of a memory device using a first search operation, wherein the first search operation includes a binary search operation; determining a tuning code for a bias generator circuit of the memory device using the built-in self-tuning circuit and a second search operation; and generating a voltage for at least one control input in a memory array of the memory device using the bias generator circuit.

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