Semiconductor devices

Abstract

This invention provides a semiconductor device that operates reliably. The semiconductor device includes: electrodes; pull-up and pull-down circuits that control the voltage of the electrodes in accordance with input data; internal circuitry that outputs data; a control circuitry capable of performing operations of the internal circuitry and calibration operations of the pull-up and pull-down circuits; and a clock signal control circuitry that supplies a first clock signal to the control circuitry when performing a calibration operation. The clock signal control circuitry includes: a clock signal generation circuitry that outputs a second clock signal when performing at least one of the internal circuitry operation and the calibration operation; a clock signal output circuitry that outputs the second clock signal as the first clock signal in accordance with a gate signal; and a gate signal output circuitry that outputs a signal indicating the execution state of the calibration operation as a gate signal in accordance with the switching of the second clock signal.

Description

Technical Field

[0001] This embodiment relates to a semiconductor device. Prior Technology

[0002] A semiconductor device is known, comprising electrodes, pull-up and pull-down circuits that control the voltage of the electrodes in accordance with input data, and internal circuitry for outputting data to be supplied to the pull-up and pull-down circuits. Summary of the Invention

[0003] The present invention provides a semiconductor device that operates reliably.

[0004] A semiconductor device according to one embodiment includes: electrodes; pull-up and pull-down circuits, which control the voltage of the electrodes in accordance with input data; internal circuitry that outputs data to be supplied to the pull-up and pull-down circuits; a control circuitry capable of performing operations of the internal circuitry and calibration operations such as adjusting the output impedance of the pull-up and pull-down circuits; and a clock signal control circuitry that supplies a first clock signal to the control circuitry when performing calibration operations. The clock signal control circuitry includes: a clock signal generation circuitry that outputs a second clock signal when performing at least one of the operations of the internal circuitry and calibration operations; a clock signal output circuitry that outputs the second clock signal as the first clock signal in accordance with a gate signal; and a gate signal output circuitry that outputs a signal indicating the execution state of the calibration operation as a gate signal in accordance with the switching of the second clock signal. Simple Explanation of the Diagram

[0005] Figure 1 is a block diagram showing the configuration of the memory system 10. Figure 2 is a schematic side view showing an example of the configuration of the memory system 10. Figure 3 is a schematic top view showing an example of the configuration of the memory system 10. Figure 4 is a schematic circuit diagram showing a portion of the structure of a bare memory die (MD). Figure 5 is a schematic three-dimensional diagram showing a portion of the memory cell array (MCA). Figure 6 is a schematic cross-sectional view used to illustrate the readout action. Figure 7 is a schematic cross-sectional view used to illustrate the write operation. Figure 8 is a schematic cross-sectional view used to illustrate the erasure action. Figure 9 is a block diagram showing the configuration of the peripheral circuit PC. Figure 10 is a schematic circuit diagram showing the configuration of the terminal resistor adjustment circuit in the input / output control circuit (I / O). Figure 11 is a table used to illustrate the terminal resistor adjustment circuit in the input / output control circuit (I / O). Figure 12 is a schematic circuit diagram showing the configuration of the calibration circuit. Figure 13 is a schematic circuit diagram showing the configuration of the calibration circuit. Figure 14 is a timing diagram used to illustrate the timing of the calibration actions that can be performed. Figure 15 is a timing diagram used to illustrate the timing of the calibration actions that can be performed. Figure 16 is a schematic circuit diagram showing the configuration of the clock signal control circuit in the first embodiment. Figure 17 is a schematic circuit diagram showing a portion of the clock signal control circuit in the first embodiment. Figure 18 is a schematic circuit diagram showing a portion of the clock signal control circuit in the first embodiment. Figure 19 is a pattern waveform diagram used to illustrate the operation of the clock signal control circuit in the first embodiment. Figure 20 is a pattern waveform diagram used to illustrate the operation of the clock signal control circuit in the first embodiment. Figure 21 is a pattern waveform diagram used to illustrate the operation of the clock signal control circuit in the first embodiment. Figure 22 is a schematic circuit diagram showing the configuration of the clock signal control circuit in the second embodiment. Figure 23 is a schematic circuit diagram showing a portion of the clock signal control circuit in the second embodiment. Figure 24 is a pattern waveform diagram used to illustrate the operation of the clock signal control circuit in the second embodiment. Figure 25 is a pattern waveform diagram used to illustrate the operation of the clock signal control circuit in the second embodiment. Figure 26 is a timing diagram used to explain the timing points at which calibration operations can be performed in the semiconductor device of the third embodiment. Implementation

[0006] Secondly, the semiconductor device of the embodiment will be described in detail with reference to the drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention.

[0007] Furthermore, when referred to as "semiconductor device" in this specification, it sometimes means semiconductor memory device, and sometimes it also means integrated circuits for computing, integrated circuits for communication, etc., other than semiconductor memory devices.

[0008] Furthermore, when referred to as a "semiconductor memory device" in this specification, it sometimes means a memory die (memory chip), and sometimes it also means a memory system including a controller die, such as a memory card or SSD. Moreover, it sometimes refers to a device including a host computer, such as a smartphone, tablet, or personal computer. Also, in this specification, NAND flash memory is illustrated as a semiconductor memory device. However, a semiconductor memory device can also be any type of memory other than NAND flash memory.

[0009] Furthermore, when referred to as "internal circuitry" in this specification, it sometimes means memory cell array, and sometimes it also means arithmetic circuits, communication circuits, etc.

[0010] Furthermore, when it is referred to in this specification as the first component being "electrically connected" to the second component, the first component may be directly connected to the second component, or the first component may be connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is still "electrically connected" to the third transistor.

[0011] Furthermore, when referred to in this specification as the first component being "electrically connected" between the second and third components, it sometimes means that the first, second, and third components are connected in series and the second component is electrically connected to the third component via the first component.

[0012] Furthermore, when referred to in this specification as a circuit or the like "conducting" two wirings, it may mean, for example, that the circuit or the like includes a transistor or the like, and that the transistor or the like is placed in the current path between the two wirings, and that the transistor or the like is in an ON state.

[0013] [First Implementation] [Memory System 10] Figure 1 is a block diagram showing the configuration of the memory system 10.

[0014] The memory system 10 performs tasks such as reading, writing, and erasing user data in response to signals sent from the host computer 20. The memory system 10 may be, for example, a memory card, an SSD, or other system capable of storing user data. The memory system 10 includes a plurality of memory wafers (MDs) for storing user data, and a controller wafer (CD) connected to the plurality of memory wafers (MDs) and the host computer 20. The controller wafer (CD) may include, for example, a processor and RAM, and performs processes such as logical address to physical address conversion, bit error detection / correction, garbage collection (compression), and wear averaging.

[0015] Figure 2 is a schematic side view showing an example of the configuration of the memory system 10. Figure 3 is a schematic top view showing the example of the configuration. For ease of explanation, some components are omitted in Figures 2 and 3.

[0016] As shown in Figure 2, the memory system 10 of this embodiment includes a mounting substrate (MSB), a plurality of memory dies (MDs) deposited on the MSB, and a controller die (CD) deposited on the memory dies. A solder pad electrode P is provided at the Y-direction end of the upper surface of the MSB, and other areas are bonded to the lower surface of the memory dies (MDs) via adhesive or the like. A solder pad electrode P is provided at the Y-direction end of the upper surface of the memory dies (MDs), and other areas are bonded to the lower surfaces of other memory dies (MDs) or controller dies (CDs) via adhesive or the like. A solder pad electrode P is provided at the Y-direction end of the upper surface of the controller die (CD).

[0017] As shown in Figure 3, the mounting substrate MSB, the plurality of memory die MDs, and the controller die CD each have a plurality of bonding pad electrodes P arranged along the X direction. The plurality of bonding pad electrodes P disposed on the mounting substrate MSB, the plurality of memory die MDs, and the controller die CD are interconnected via bonding wires B.

[0018] Furthermore, the configurations shown in Figures 2 and 3 are merely examples, and the specific configurations can be adjusted accordingly. For instance, in the examples shown in Figures 2 and 3, the controller die CD is stacked on a plurality of memory die MDs, and these configurations are connected by bonding wires B. In this configuration, the plurality of memory die MDs and the controller die CD are contained within a single package. However, the controller die CD may also be contained within a different package than the memory die MDs. Additionally, the plurality of memory die MDs and the controller die CD may also be interconnected via through electrodes, etc., instead of bonding wires B.

[0019] [Composition of Memory Chip Metal] Figure 4 is a schematic circuit diagram showing a portion of the structure of a memory die MD. As shown in Figure 4, the memory die MD includes a memory cell array (MCA) for storing user data and peripheral circuitry (PC) connected to the MCA.

[0020] [Composition of Memory Cell Array (MCA)] The memory cell array (MCA) has a plurality of memory blocks (BLK). Each of the plurality of memory blocks (BLK) has a plurality of string cells (SU). Each of the plurality of string cells (SU) has a plurality of memory strings (MS). One end of each of the plurality of memory strings (MS) is connected to the peripheral circuit (PC) via a bit line (BL). The other end of each of the plurality of memory strings (MS) is connected to the peripheral circuit (PC) via a common source line (SL).

[0021] The memory string (MS) has drain-side select transistors (STDT, STD), multiple memory cells (MC) (memory cell transistors) connected in series between the bit line (BL) and the source line (SL), and source-side select transistors (STS, STSB). Hereinafter, the drain-side select transistors (STDT, STD) and the source-side select transistors (STS, STSB) will sometimes be referred to simply as select transistors (STDT, STD, STS, STSB, etc.).

[0022] A memory cell (MC) is a field-effect transistor comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a charge storage film. The threshold voltage of the memory cell (MC) varies accordingly with the amount of charge in the charge storage film. The memory cell (MC) stores 1 bit or multiple bits of user data. Furthermore, word lines (WL) are connected to the gate electrodes of multiple memory cells (MC) corresponding to one memory string (MS). These word lines (WL) are respectively configured to correspond to memory blocks (BLK) and are collectively connected to all memory strings (MS) within the memory block (BLK).

[0023] Select transistors STDT, STD, STS, and STSB are field-effect transistors with a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. Select gate lines SGDT, SGD, SGS, and SGSB are respectively connected to the gate electrodes of the select transistors STDT, STD, STS, and STSB. The drain-side select gate line SGD corresponds to the serial cell SU and is connected to all memory strings MS within the serial cell SU. The drain-side select gate line SGDT and the source-side select gate lines SGS and SGSB correspond to the memory block BLK and are connected to all memory strings MS within the memory block BLK.

[0024] Figure 5 is a schematic perspective view showing a portion of the structure of the memory cell array (MCA). The memory cell array (MCA) is disposed above the semiconductor substrate 100. Furthermore, a plurality of transistors (Tr) constituting a peripheral circuit (PC) are disposed on the upper surface of the semiconductor substrate 100. Each of these transistors (Tr) has a channel region comprising a portion of the upper surface of the semiconductor substrate 100, a gate insulating film formed on the upper surface of the semiconductor substrate 100, and a gate electrode that is separated from the gate insulating film and faces the channel region.

[0025] The memory cell array (MCA) has a plurality of memory blocks (BLK) arranged along the Y direction. Furthermore, an inter-block insulating layer (ST) of silicon oxide (SiO2) or similar material is disposed between two adjacent memory blocks (BLK) in the Y direction. Additionally, a plurality of bit lines (BL) arranged along the X direction and extending along the Y direction are disposed above the memory cell array (MCA).

[0026] The memory block BLK has a plurality of conductive layers 110 arranged along the Z direction, a plurality of semiconductor pillars 120 extending along the Z direction, and a plurality of gate insulating films 130 respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120.

[0027] The conductive layer 110 is a generally plate-shaped conductive layer extending along the X direction. The conductive layer 110 may include a barrier conductive film such as titanium nitride (TiN) and a laminated film of metal films such as tungsten (W). Furthermore, the conductive layer 110 may also include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged along the Z direction.

[0028] One or more of the bottommost conductive layers 110 among the plurality of conductive layers 110 function as the gate electrode of the source-side selected gate line SGSB (Figure 4) and the plurality of source-side selected transistors STSB (Figure 4) connected thereto.

[0029] Furthermore, one or more conductive layers 110 located above it function as source-side selected gate lines SGS (Fig. 4) and gate electrodes of multiple source-side selected transistors STS (Fig. 4) connected thereto.

[0030] Furthermore, the multiple conductive layers 110 located above it function as gate electrodes for the word lines WL (Figure 4) and the multiple memory cells MC (Figure 4) connected to them.

[0031] Furthermore, one or more conductive layers 110 located above it function as gate electrodes for drain-side selective gate lines SGD (Fig. 4) and multiple drain-side selective transistors STD (Fig. 4) connected thereto.

[0032] Furthermore, one or more conductive layers 110 located above it function as gate electrodes for drain-side selected gate lines SGDT (Fig. 4) and multiple drain-side selected transistors STDT (Fig. 4) connected thereto.

[0033] A semiconductor layer 112 is disposed below a plurality of conductive layers 110. The semiconductor layer 112 may contain, for example, polycrystalline silicon containing N-type impurities such as phosphorus (P). Furthermore, an insulating layer 101 such as silicon oxide (SiO2) is disposed between the semiconductor layer 112 and the conductive layers 110.

[0034] Semiconductor layer 112 functions as source line SL (Figure 4). Source line SL is a common setting for all memory blocks BLK contained in the memory cell array MCA, for example.

[0035] Semiconductor pillars 120 are arranged in a prescribed pattern in the X and Y directions. Semiconductor pillars 120 function as channel regions for multiple memory cells MC contained in a memory string MS (Figure 4) and for select transistors STDT, STD, STS, and STSB. Semiconductor pillars 120 are, for example, semiconductor layers such as polycrystalline silicon (Si). Semiconductor pillars 120 have, for example, a generally cylindrical shape, with an insulating layer 125 such as silicon oxide disposed in the central portion. Furthermore, the outer peripheral surfaces of semiconductor pillars 120 are surrounded by conductive layers 110, and the pillars face the conductive layers 110.

[0036] An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the end of the bit line BL side of the semiconductor pillar 120. The impurity region 121 is connected to the bit line BL via contact electrode Ch and contact electrode Cb.

[0037] The gate insulating film 130 has a generally cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. The gate insulating film 130 may include, for example, a tunnel insulating film, a charge storage film, and a barrier insulating film deposited between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film and the barrier insulating film may be insulating films such as silicon oxide (SiO2). The charge storage film may be a film capable of storing charge, such as silicon nitride (SiN). The tunnel insulating film, the charge storage film, and the barrier insulating film have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120, excluding the contact portion between the semiconductor pillar 120 and the semiconductor layer 112.

[0038] Furthermore, the gate insulating film 130 may also have a floating gate, for example, containing polycrystalline silicon with N-type or P-type impurities.

[0039] A plurality of contact electrodes CC are connected to a plurality of conductive layers 110. The plurality of conductive layers 110 are electrically connected to a peripheral circuit PC via the plurality of contact electrodes CC. As shown in FIG5, the plurality of contact electrodes CC extend along the Z direction and are connected to the conductive layers 110 at their lower ends. The contact electrodes CC may comprise, for example, a barrier conductive film such as titanium nitride (TiN) and a multilayer film of metal such as tungsten (W).

[0040] Furthermore, the memory cell array (MCA) can also be formed by inverting its orientation. For example, bit lines (BL) can be positioned below a plurality of memory blocks (BLK). Also, semiconductor layer 112 can be positioned above a plurality of conductive layers 110.

[0041] [Meaning of the Memory Cell Array (MCA)] Next, the operation of the memory cell array (MCA) will be explained. The MCA of this embodiment is configured to perform read, write, and erase operations. Furthermore, in the following description, the read, write, and erase operations of the MCA will sometimes be referred to as "core operations".

[0042] Figure 6 is a schematic cross-sectional view used to illustrate the readout action. In the following description, the character line WL that is the object of the action is sometimes referred to as the selected character line WLS, and other character lines WL are referred to as the non-selected character lines WLU.

[0043] During the readout operation, for example, an operating voltage VDD is supplied to the bit line BL. Also, a voltage VSRC is supplied to the source line SL. The voltage VSRC can be greater than or equal to the ground voltage VSS. The operating voltage VDD is greater than the voltage VSRC.

[0044] Furthermore, during the readout operation, a voltage VSG is supplied to the drain-side selective gate lines SGDT and SGD. The voltage VSG is greater than the operating voltage VDD. Also, the voltage difference between VSG and VDD is greater than the threshold voltage of the drain-side selective transistors STDT and STD. Therefore, an electron channel is formed in the channel region of the drain-side selective transistors STDT and STD, transmitting the operating voltage VDD.

[0045] Furthermore, during the readout operation, voltage VSG is supplied to the source-side selective gate lines SGS and SGSB. Voltage VSG is greater than voltage VSRC. Also, the voltage difference between VSG and VSRC is greater than the threshold voltage of the source-side selective transistors STS and STSB. Therefore, an electron channel is formed in the channel region of the source-side selective transistors STS and STSB, transmitting voltage VSRC.

[0046] Furthermore, during the readout operation, a readout path voltage VREAD is supplied to the non-selected word line WLU. The readout path voltage VREAD is greater than the operating voltage VDD and voltage VSRC. Also, the voltage difference between the readout path voltage VREAD and the operating voltage VDD and voltage VSRC is greater than the threshold voltage of the memory cell MC, and is independent of the data recorded in the memory cell MC. Therefore, an electron channel is formed in the channel region of the non-selected memory cell MC, transmitting the operating voltage VDD and voltage VSRC to the selected memory cell MC.

[0047] Furthermore, during the read operation, a read voltage VCGR is supplied to the select word line WLS. The read voltage VCGR is less than the read path voltage VREAD. The voltage difference between VCGR and VSRC is greater than the threshold voltage of the memory cell MC that records a portion of the data. Therefore, the memory cell MC that records a portion of the data is turned on. Consequently, current flows in the bit line BL connected to this memory cell MC. On the other hand, the voltage difference between VCGR and VSRC is less than the threshold voltage of the memory cell MC that records a portion of the data. Therefore, the memory cell MC that records a portion of the data is turned off. Consequently, current does not flow in the bit line BL connected to this memory cell MC.

[0048] Furthermore, during the readout process, the current or voltage of each bit line BL is detected by the sensing amplifier SA, saved as user data, and output to the cache memory CM.

[0049] Figure 7 is a schematic cross-sectional view used to illustrate the write operation.

[0050] During a write operation, for example, a voltage VSRC is supplied to the bit line BLW connected to one of the plurality of select memory cells MC that performs threshold voltage adjustment. Also, an operating voltage VDD is supplied to the bit line BLP connected to one of the plurality of select memory cells MC that does not perform threshold voltage adjustment. Hereinafter, the one of the plurality of select memory cells MC that performs threshold voltage adjustment is sometimes referred to as a "write memory cell MC," and the one that does not perform threshold voltage adjustment is sometimes referred to as a "disable memory cell MC."

[0051] Furthermore, during the write operation, voltage VSGD is supplied to the gate lines SGDT and SGD on the drain side.

[0052] The voltage VSGD is greater than the voltage VSRC. Furthermore, the voltage difference between VSGD and VSRC is greater than the threshold voltage of the drain-side selective transistors STDT and STD. Therefore, an electron channel is formed in the channel region of the drain-side selective transistors STDT and STD connected to the bit line BLW, thus transmitting the voltage VSRC.

[0053] On the other hand, the voltage difference between the voltage VSGD and the operating voltage VDD is less than the threshold voltage of the drain-side selective transistors STDT and STD. Therefore, the drain-side selective transistors STDT and STD connected to the bit line BLP are in the off state.

[0054] Furthermore, during the write operation, a voltage VSRC is supplied to the source line SL, and a ground voltage VSS is supplied to the source-side select gate lines SGS and SGSB. This causes the source-side select transistors STS and STSB to be in the off state.

[0055] Furthermore, during the write operation, a write path voltage VPASS is supplied to the non-selected word line WLU. The write path voltage VPASS is greater than the read path voltage VREAD. Also, the voltage difference between the write path voltage VPASS and the voltage VSRC is greater than the threshold voltage of the memory cell MC, and is independent of the data recorded in the memory cell MC. Therefore, an electron channel is formed in the channel region of the non-selected memory cell MC, transmitting the voltage VSRC to the write memory cell MC.

[0056] Furthermore, during the write operation, a programming voltage VPGM is supplied to the select word line WLS. The programming voltage VPGM is greater than the write path voltage VPASS.

[0057] Here, a voltage VSRC is supplied to the channel of the semiconductor pillar 120 connected to the bit line BLW. A relatively large electric field is generated between this semiconductor pillar 120 and the select word line WLS. As a result, electrons in the channel of the semiconductor pillar 120 tunnel to the charge storage film in the gate insulating film 130 (Figure 5). As a result, the threshold voltage for writing to the memory cell MC increases.

[0058] On the other hand, the channel of the semiconductor pillar 120 connected to the bit line BLP becomes electrically floating. The potential of this channel rises to around the write path voltage VPASS through capacitive coupling with the non-select word line WLU. Only a smaller electric field than the aforementioned electric field is generated between the semiconductor pillar 120 and the select word line WLS. Therefore, electrons in the channel of the semiconductor pillar 120 do not tunnel to the charge storage film in the gate insulating film 130 (Figure 5). Therefore, the threshold voltage of the disable memory cell MC does not increase.

[0059] Figure 8 is a schematic cross-sectional view used to illustrate the erasure action.

[0060] During the erase operation, an erase voltage VERA is supplied to the bit line BL and the source line SL. The erase voltage VERA can be greater than the programming voltage VPGM, or it can be equal to the programming voltage VPGM.

[0061] Furthermore, during the erase operation, a voltage VSG' is supplied to the drain-side selective gate line SGDT. This voltage VSG' is less than the erase voltage VERA. Consequently, GIDL (Gate Induced Drain Leakage) is generated in the drain-side selective transistor STDT, thus creating electron-hole pairs. Electrons then move towards the bit line BL, and holes move towards the memory cell MC.

[0062] Furthermore, during the erase operation, a voltage VSG" is supplied to the drain-side selective gate line SGD. The voltage VSG" is less than the erase voltage VERA but greater than the voltage VSG'. In this way, a hole channel is formed in the channel region of the drain-side selective transistor STD, and the hole is transmitted to the memory cell MC side.

[0063] Furthermore, during the erasure operation, a voltage VSG' is supplied to the source-side selected gate line SGSB. This generates a GIDL in the source-side selected transistor STSB, thereby creating electron-hole pairs. Electrons then move towards the source line SL, and holes move towards the memory cell MC.

[0064] Furthermore, during the erasure operation, a voltage VSG is supplied to the source-side selective gate line SGS. This forms a hole channel in the channel region of the source-side selective transistor STS, allowing the hole to be transmitted to the memory cell MC side.

[0065] Furthermore, during the erase operation, a ground voltage VSS is supplied to the character line WL. This allows electrical holes in the channels of the semiconductor pillar 120 to tunnel to the charge storage film in the gate insulating film 130 (Figure 5). Consequently, the threshold voltage of the memory cell MC decreases.

[0066] [Composition of Peripheral Circuit PC] Figure 9 is a block diagram showing the configuration of the peripheral circuit PC.

[0067] Furthermore, Figure 9 illustrates a plurality of control terminals. These control terminals may be represented as control terminals corresponding to high-level signals (positive logic signals), control terminals corresponding to low-level signals (negative logic signals), or control terminals corresponding to both high-level and low-level signals. In Figure 9, the symbol for the control terminal corresponding to the low-level signal includes an overline (top line). In this specification, the symbol for the control terminal corresponding to the low-level signal includes a slash (" / "). Furthermore, Figure 9 is an example, and the specific configuration can be adjusted accordingly. For example, some or all of the high-level signals may be set as low-level signals, and some or all of the low-level signals may be set as high-level signals.

[0068] Furthermore, arrows indicating the input / output directions are shown next to the plurality of control terminals shown in Figure 9. In Figure 9, control terminals marked with arrows from left to right can be used for inputting data or other signals from the controller die CD to the memory die MD. In Figure 9, control terminals marked with arrows from right to left can be used for outputting data or other signals from the memory die MD to the controller die CD. In Figure 9, control terminals marked with bidirectional arrows can be used for both inputting data or other signals from the controller die CD to the memory die MD and outputting data or other signals from the memory die MD to the controller die CD.

[0069] The peripheral circuitry PC includes a column decoder RD and a sense amplifier SA connected to the memory cell array MCA, as well as a cache memory CM connected to the sense amplifier. Furthermore, the peripheral circuitry PC includes a voltage generation circuit VG and a sequencer SQC. Additionally, the peripheral circuitry PC includes input / output control circuitry I / O, logic circuitry CTR, address register ADR, instruction register CMR, and status register STR.

[0070] The column decoder RD includes, for example, a block decoder that decodes the block address in the column address RA contained in the address data Add; and a voltage transmission circuit that, in accordance with the output signal of the block decoder, turns on the plurality of word lines WL (Figure 4) contained in one of the plurality of memory blocks BLK and the plurality of voltage supply lines (not shown).

[0071] The sense amplifier SA includes multiple sensing circuits and multiple voltage transfer circuits connected to multiple bit lines BL, as well as a data latch circuit. For example, the sensing circuit latches "0" or "1" data based on the voltage or current of bit line BL into the data latch circuit according to a control signal from the sequencer SQC. For example, the voltage transfer circuit adjusts the voltage of bit line BL to "H" or "L" based on the "0" or "1" data latched in the data latch circuit according to the control signal from the sequencer SQC. User data Dat in the data latch circuit is output to the input / output control circuit (I / O) via cache memory CM and data bus DB. Furthermore, user data Dat output from the input / output control circuit (I / O) is latched into the data latch circuit in the sense amplifier SA via data bus DB and cache memory CM.

[0072] The voltage generation circuit VG includes, for example, a boost circuit such as a charge pump circuit and a buck circuit such as a regulator. These boost and buck circuits are respectively connected to the voltage supply lines of the supplied power supply voltage VCC and the ground voltage VSS. These voltage supply lines are, for example, connected to the pad electrode P as illustrated with reference to Figures 2 and 3. The voltage generation circuit VG generates, for example, multiple operating voltages applied to the bit line BL, source line SL, word line WL, and select gate lines SGD and SGS during read, write, and erase operations on the memory cell array MCA, based on control signals from the sequencer SQC. These operating voltages are then supplied to the bit line BL, source line SL, word line WL, and select gate lines SGDT, SGD, SGS, and SGSB via multiple voltage supply lines. The operating voltages output from the voltage supply lines are appropriately adjusted according to the control signals from the sequencer SQC.

[0073] The sequencer SQC outputs internal control signals to the column decoder RD, sense amplifier module SAM, and voltage generation circuit VG based on the instruction data Cmd input to the instruction register CMR. Furthermore, the sequencer SQC appropriately outputs the status data Stt, representing the state of the bare memory die MD, to the status register STR.

[0074] Furthermore, the sequencer SQC generates a ready / busy signal and outputs it to the RY / / BY terminal. For example, during operations such as read, write, and erase operations that supply voltage to the memory cell array MCA, the RY / / BY terminal is in the "L" state; otherwise, it is in the "H" state. During the period when the RY / / BY terminal is in the "L" state (busy period), access to the memory die MD is essentially disabled. During the period when the RY / / BY terminal is in the "H" state (ready period), access to the memory die MD is permitted. Moreover, the RY / / BY terminal is implemented, for example, by the pad electrode P described with reference to Figures 2 and 3.

[0075] Address registers (ADRs) are connected to the input / output control circuit (I / O) and store address data (Add) input from the I / O circuit. An ADR may have multiple 8-bit register rows. Each register row stores the address data (Add) corresponding to an internal operation being performed, such as read, write, or erase.

[0076] Furthermore, the address data Add includes, for example, row address CA and column address RA. The column address RA includes, for example, the block address of a specific memory block BLK (Figure 4), the page address of a specific serial unit SU and word line WL, the memory surface address of a specific memory cell array MCA, and the chip address of a specific memory die MD.

[0077] The instruction register CMR is connected to the input / output control circuit (I / O), and the instruction data Cmd is input from the I / O. When the instruction data Cmd is input to the instruction register CMR, a control signal is sent to the sequencer SQC.

[0078] The status register STR is connected to the input / output control circuit (I / O) and stores the status data Stt output to the I / O circuit. The status register STR may have multiple 8-bit register rows. Each register row, for example, saves the status data Stt related to the internal operation being performed, such as read, write, or erase operations. Furthermore, the register row may store the ready / busy information of the memory cell array (MCA).

[0079] The input / output control circuit (I / O) includes data signal input / output terminals DQ0~DQ7, data strobe signal input / output terminals DQS and / DQS, a plurality of input circuits and drive circuits connected to the data signal input / output terminals DQ0~DQ7 respectively, and shift registers connected to the plurality of input circuits and output circuits respectively. The input circuits are, for example, comparators or other input receivers. The drive circuit functions as an OCD (Off-Chip Driver) circuit for outputting data and adjusting the output impedance during data output. It also functions as a circuit for adjusting the input impedance during data input. In the following description, this drive circuit will be referred to as the termination resistor adjustment circuit.

[0080] The data input / output terminals DQ0~DQ7 and the data strobe signal input / output terminals DQS and / DQS are implemented, for example, by the pad electrodes P described with reference to Figures 2 and 3. Data input via the data input / output terminals DQ0~DQ7 is input to the cache memory CM, the address register ADR, or the instruction register CMR, corresponding to the internal control signals from the logic circuit CTR. Furthermore, data output via the data input / output terminals DQ0~DQ7 is output from the cache memory CM or the status register STR, corresponding to the internal control signals from the logic circuit CTR.

[0081] Signals input via data strobe input / output terminals DQS and / DQS (e.g., data strobe signals and their complementary signals) are used when data is input via data signal input / output terminals DQ0 to DQ7. Data input via data signal input / output terminals DQ0 to DQ7 is captured into the shift register in the input / output control circuit I / O at the points when the voltage of data strobe input / output terminal DQS rises and the voltage of data strobe input / output terminal / DQS falls, and when the voltage of data strobe input / output terminal DQS falls and the voltage of data strobe input / output terminal / DQS rises.

[0082] The logic circuit CTR has a plurality of external control terminals / CE, CLE, ALE, / WE, / RE, RE, and logic circuits connected to these external control terminals / CE, CLE, ALE, / WE, / RE, RE. The logic circuit CTR receives external control signals from the controller die CD via the external control terminals / CE, CLE, ALE, / WE, / RE, RE, and outputs internal control signals to the input / output control circuit (I / O) accordingly. In the following description, the external control terminal / CE is sometimes referred to as the "chip enable signal input terminal / CE".

[0083] Furthermore, the external control terminals / CE, CLE, ALE, / WE, / RE, and RE are implemented, for example, by the pad electrode P as illustrated in Figures 2 and 3.

[0084] Signals input via the external control terminal / CE (e.g., chip enable signal) are used when selecting the memory die (MD). A memory die inputting "L" to the external control terminal / CE becomes capable of inputting and outputting user data (Dat), instruction data (Cmd), and address data (Add, hereinafter sometimes simply referred to as "data"). A memory die inputting "H" to the external control terminal / CE becomes in a state where data input and output are not possible.

[0085] Signals input via the external control terminal CLE (such as the instruction latch enable signal) are used when the instruction register CMR is used. When "H" is input to the external control terminal CLE, the data input via the data signal input / output terminals DQ0~DQ7 is stored as instruction data Cmd in the buffer memory of the input / output control circuit I / O and transmitted to the instruction register CMR.

[0086] Signals input via the external control terminal ALE (such as address latch enable signals) are used when the address register ADR is used. When "H" is input to the external control terminal ALE, the data input via the data signal input / output terminals DQ0~DQ7 is stored as address data Add in the buffer memory of the input / output control circuit I / O and transmitted to the address register ADR.

[0087] Furthermore, when an "L" signal is input to either the external control terminals CLE or ALE, the data input via the data signal input / output terminals DQ0~DQ7 is stored as user data Dat in the shift register of the input / output control circuit I / O. The user data Dat stored in the shift register is then transferred to the cache memory CM via the bus DB.

[0088] Signals input via the external control terminal / WE (e.g., write enable signal) are used when data is input via the data signal input / output terminals DQ0~DQ7. The data input via the data signal input / output terminals DQ0~DQ7 is fetched into the shift register, instruction register CMR, or address register ADR in the input / output control circuit I / O when the voltage of the external control terminal / WE rises (input signal switching).

[0089] Furthermore, when inputting data, external control terminals / WE can be used, or data strobe signal input / output terminals DQS and / DQS can be used.

[0090] Signals input via external control terminals / RE and RE (e.g., read enable signals and their complementary signals) are used when outputting data via data signal input / output terminals DQ0~DQ7. Data input via data signal input / output terminals DQ0~DQ7 is switched at points where the voltage of external control terminal RE rises and the voltage of external control terminal / RE falls, and where the voltage of external control terminal RE falls and the voltage of external control terminal / RE rises.

[0091] [The structure of the terminating resistor adjustment circuit in the input / output control circuit (I / O)] Figure 10 is a schematic circuit diagram showing the configuration of the terminating resistor adjustment circuit in the input / output control circuit (I / O). Figure 11 is a table used to explain this terminating resistor adjustment circuit.

[0092] The terminating resistor adjustment circuit includes seven terminating resistor adjustment units 210 connected in parallel to the data signal input / output terminals DQ0~DQ7 and the data strobe signal input / output terminals DQS, / DQS, and seven terminating resistor adjustment unit control circuits 220 connected to the seven terminating resistor adjustment units 210.

[0093] Each of the seven terminating resistor adjustment units 210 has an impedance of 240 Ω. Furthermore, each of the seven terminating resistor adjustment units 210 is connected to the signal line TRA_EN<6:0>, and the number of driven terminating resistor adjustment units 210 is controlled accordingly by the signal line TRA_EN<6:0>. For example, when a signal of 0000001 (01 in hexadecimal) is input to the signal line TRA_EN<6:0>, as shown in Figure 11, the impedance ZDRV of the terminating resistor adjustment circuit is set to approximately 240 Ω. Also, for example, when a signal of 0011111 (1F in hexadecimal) is input to the signal line TRA_EN<6:0>, the impedance ZDRV of the terminating resistor adjustment circuit is set to approximately 240 Ω / 5 = 48 Ω. The signal of the signal line TRA_EN<6:0> is controlled by the user, for example.

[0094] For example, as shown in Figure 10, the terminating resistor adjustment unit 210 includes a pull-up circuit 211, which is connected between the voltage supply line of the supplied voltage VDDQ and the data signal input / output terminals DQ0~DQ7 and the data strobe signal input / output terminals DQS, / DQS. Furthermore, the terminating resistor adjustment unit 210 also includes a pull-down circuit 212, which is connected between the data signal input / output terminals DQ0~DQ7 and the data strobe signal input / output terminals DQS, / DQS and the pad electrode P of the supplied ground voltage VSS.

[0095] The pull-up circuit 211 includes a resistor 213 connected to the data signal input / output terminals DQ0~DQ7 or the data strobe signal input / output terminals DQS, / DQS, and n+1 (n is a natural number) transistors 214 connected in parallel between the resistor 213 and the voltage supply line of the supplied voltage VDDQ. The transistors 214 are PMOS transistors. Each of the n+1 transistors 214 has at least one of a different channel width and channel length, and has n+1 different resistance values. The gate electrodes of the n+1 transistors 214 are respectively connected to the signal line Up*. <0> ~Up* <n>(* represents any number from 0 to 6). To the Up signal line* <0> ~Up* <n>The input n+1 bits of data are adjusted so that the impedance of the pull-up circuit 211 is approximately 240 Ω.

[0096] The pull-down circuit 212 includes a resistor 215 connected to the data signal input / output terminals DQ0~DQ7 or the data strobe signal input / output terminals DQS, / DQS, and m+1 (m is a natural number) transistors 216 connected in parallel between the resistor 215 and the pad electrode P supplied with ground voltage VSS. The transistors 216 are NMOS transistors. Each of the m+1 transistors 216 has at least one of a different channel width and channel length, and has m+1 different resistance values. The gate electrodes of the m+1 transistors 216 are respectively connected to the signal line Dn*. <0> ~Dn* <m>(* represents any number from 0 to 6). The following is directed to signal line Dn*. <0> ~Dn* <m>The input m+1 bits of data are adjusted so that the impedance of the pull-down circuit 212 is approximately 240 Ω.

[0097] The terminal resistor adjustment unit control circuit 220, for example, has n+1 OR circuits 221 and m+1 OR circuits 222.

[0098] During data output, a "1" or "0" signal output from data signal input / output terminals DQ0~DQ7, or a clock signal output from data strobe signal input / output terminals DQS / DQS, is input to one of the input terminals of the n+1 OR circuit 221. Additionally, the n+1 bits of data PCODE corresponding to the n+1 PMOS transistors included in the pull-up circuit 211 are input to another input terminal of the n+1 OR circuit 221. <n:0>The corresponding bits in the middle.

[0099] Furthermore, during data output, a "1" or "0" signal output from data signal input / output terminals DQ0~DQ7, or a clock signal output from data strobe signal input / output terminals DQS / DQS, is input to one of the m+1 input terminals of circuit 222. Additionally, the m+1 data NCODE corresponding to the m+1 NMOS transistors included in pull-down circuit 212 is input to another input terminal of circuit 222. <m:0>The corresponding bits in the middle.

[0100] During data input, the signals of one input terminal of the n+1 OR circuits 221 and one input terminal of the m+1 OR circuits 222 are fixed to "1" or "0". Furthermore, n+1 bits of data PCODE are input to the signals of the other input terminal of the n+1 OR circuits 221 and the other input terminal of the m+1 OR circuits 222. <n:0>The corresponding bits and the data NCODE of the m+1 bits. <m:0>The corresponding bits in the middle.

[0101] Furthermore, the PCODE data used during data input <n:0>Compatible with PCODE data used during data output <n:0>Different. Similarly, the data NCODE used during data entry... <m:0>It can be used with the data NCODE used during data output. <m:0>different.

[0102] [Construction of the calibration circuit] Figures 12 and 13 are schematic circuit diagrams showing the configuration of the calibration circuit.

[0103] Figure 9 omits the description, but the peripheral circuit PC includes a calibration circuit. The calibration circuit adjusts the data PCODE so that the impedance of the aforementioned pull-up circuit 211 and pull-down circuit 212 is approximately 240 Ω. <n:0>and data NCODE <m:0>.

[0104] As shown in Figure 12, the calibration circuit includes a first replication unit 310 connected to the calibration electrode ZQ, a first replication unit control circuit 320 connected to the first replication unit 310, a second replication unit 330 connected to the calibration electrode ZQ, a second replication unit control circuit 340 connected to the second replication unit 330, a reference voltage generation circuit 350, a data latch circuit 360, and a calibration control circuit 370.

[0105] The first replication unit 310 includes a pull-up circuit 311 connected between the voltage supply line of the supplied voltage VDDQ and the calibration electrode ZQ.

[0106] As shown in Figure 13, the pull-up circuit 311 includes a resistor 313 connected to the calibration electrode ZQ and n+1 transistors 314 connected in parallel between the resistor 313 and the voltage supply line of the supplied voltage VDDQ. The transistors 314 are PMOS transistors. Each of the n+1 transistors 314 has at least one of a different channel width and channel length, and has n+1 different resistance values. The gate electrodes of the n+1 transistors 314 are respectively connected to n+1 signal lines. Data PCODE is input to these n+1 signal lines. <n:0>enter.

[0107] As shown in Figure 12, the first replication unit control circuit 320 has output data PCODE. <n:0>The counter 321, the comparator 322 that controls the counter 321, and the ESD countermeasure circuit 323 connected to the input terminal of the comparator 322.

[0108] Counter 321 adjusts the PCODE data synchronously with the clock signal. <n:0>For example, when the output signal of comparator 322 is in the "L" state, the n+1 bits of data PCODE are... <n:0>The value represented is decremented by 1. Furthermore, when the output signal of comparator 322 is in the "H" state, counter 321 will decrement the data of bit n+1 by 1. <n:0>The value represented is increased by 1.

[0109] The inverting input terminal of comparator 322 is connected to the reference voltage generation circuit 350 via ESD countermeasure circuit 323. The non-inverting input terminal of comparator 322 is connected to the calibration electrode ZQ via ESD countermeasure circuit 323. Furthermore, comparator 322 is controlled by calibration control circuit 370.

[0110] ESD countermeasure circuit 323 protects comparator 322 from the effects of rapid charging and discharging caused by static electricity, etc.

[0111] The second replication unit 330 includes a pull-up circuit 331 connected between the voltage supply line of the supplied voltage VDDQ and the calibration electrode ZQ. Furthermore, the second replication unit 330 includes a pull-down circuit 332 connected between the calibration electrode ZQ and the electrode supplying the ground voltage VSS.

[0112] As shown in Figure 13, the pull-up circuit 331 includes a resistor 333 connected to the calibration electrode ZQ, and n+1 transistors 334 connected in parallel between the resistor 333 and the voltage supply line of the supplied voltage VDDQ. The transistors 334 are PMOS transistors. Each of the n+1 transistors 334 has at least one of a different channel width and channel length, and has n+1 different resistance values. The gate electrodes of the n+1 transistors 334 are respectively connected to n+1 signal lines. Data PCODE is input to these n+1 signal lines. <n:0>.

[0113] As shown in Figure 13, the pull-down circuit 332 includes a resistor 335 connected to the calibration electrode ZQ, and m+1 transistors 336 connected in parallel between the resistor 335 and the electrode supplying the ground voltage VSS. The transistors 336 are NMOS transistors. Each of the m+1 transistors 336 has at least one of a different channel width and channel length, and has m+1 different resistance values. The gate electrodes of the m+1 transistors 336 are respectively connected to m+1 signal lines. Data NCODE is input to these m+1 signal lines. <m:0>.

[0114] As shown in Figure 12, the second copy unit control circuit 340 has an output data NCODE. <m:0>The counter 341, the comparator 342 that controls the counter 341, and the ESD countermeasure circuit 343 connected to the input terminal of the comparator 342.

[0115] Counter 341 adjusts the data NCODE synchronously with the clock signal. <m:0>For example, when the output signal of comparator 342 is in the "L" state, the m+1 bits of data NCODE are... <m:0>The value represented is incremented by 1. Furthermore, when the output signal of comparator 342 is in the "H" state, counter 341 increments the data NCODE of bit n+1. <m:0>The value it represents is reduced by 1.

[0116] The inverting input terminal of comparator 342 is connected to the reference voltage generation circuit 350 via ESD countermeasure circuit 343. The non-inverting input terminal of comparator 342 is connected to the calibration electrode ZQ via ESD countermeasure circuit 343. Furthermore, comparator 342 is controlled by calibration control circuit 370.

[0117] ESD countermeasure circuit 343 protects comparator 342 from the effects of rapid charging and discharging caused by static electricity or other factors.

[0118] The voltage generation circuit 350, for example, includes a voltage divider circuit. The voltage divider circuit includes two resistive elements connected in series between the voltage supply line of the supplied voltage VDDQ and the electrode of the supplied ground voltage VSS, and an output terminal connected between these two resistive elements. The two resistive elements have the same resistance value, and the voltage at the output terminal is half the voltage of the voltage supply line of the supplied voltage VDDQ.

[0119] The data latch circuit 360 stores the PCODE output from the first copy unit control circuit 320. <n:0>and the NCODE output from the control circuit 340 of the second replication unit. <m:0>And output to the terminal resistor adjustment circuit.

[0120] The calibration control circuit 370 controls the first replication unit control circuit 320 and the second replication unit control circuit 340. For example, it controls the first replication unit control circuit 320 to adjust the PCODE. <n:0>Secondly, the control circuit 340 of the second replication unit is controlled to adjust the NCODE. <m:0>.

[0121] [Operation of the calibration circuit] During the calibration operation of the semiconductor device in this embodiment, the control circuit 320 of the first replication unit is controlled to adjust the data PCODE. <n:0>Here, the calibration electrode ZQ is connected to the voltage supply line of the supplied voltage VDDQ via a pull-up circuit 311, and is connected to the electrode supplying the ground voltage VSS external to the semiconductor device via a series resistor 300 with a resistance of approximately 240 Ω. Furthermore, when the first replication unit control circuit 320 is controlled, the data PCODE is adjusted such that the voltage of the calibration electrode ZQm of the memory die MD0 becomes approximately the reference voltage (1 / 2 VDDQ). <n:0>Therefore, the data is from PCODE. <n:0>The impedance of the pull-up circuit 311 is adjusted to approximately 240 Ω. Subsequently, the data latch circuit 360 stores the PCODE output from the first copy unit control circuit 320. <n:0>.

[0122] Secondly, control the second copy unit control circuit 340 to adjust the data NCODE. <m:0>Here, the calibration electrode ZQ is connected to the voltage supply line of the supplied voltage VDDQ via pull-up circuit 331, and to the electrode supplying the ground voltage VSS via pull-down circuit 332. Furthermore, the impedance of pull-up circuit 331 is adjusted to approximately 240 Ω. Also, when controlling the second replication unit control circuit 340, the data NCODE is adjusted so that the voltage of calibration electrode ZQ becomes approximately the reference voltage (1 / 2 VDDQ). <m:0>Therefore, the data is NCODE. <m:0>The impedance of the pull-down circuit 332 is adjusted to approximately 240 Ω. Subsequently, the data latch circuit 360 stores the NCODE output from the second copy unit control circuit 340. <m:0>.

[0123] [2 types of data PCODE] <n:0>NCODE <m:0>[Acquisition] The calibration circuit may also include two sets of first replication units 310 and first replication unit control circuits 320 to adjust the PCODE data used during data output. <n:0>and the PCODE data used during data entry. <n:0>Both. Similarly, the calibration circuit may also have two sets of second copy units 330 and second copy unit control circuits 340 to adjust the data NCODE used during data output. <m:0>and the NCODE used when inputting data. <m:0>Both.

[0124] For example, the PCODE data used during data input. <n:0>NCODE <m:0>Compatible with PCODE data used during data output <n:0>NCODE <m:0>Similarly, it can also be based on the PCODE data used during data output. <n:0>NCODE <m:0>Figure it out.

[0125] [Time point at which calibration actions can be performed] The impedances of the pull-up circuit 211 and pull-down circuit 212 in the terminating resistor adjustment circuit change accordingly with variations in power supply voltage or temperature. Therefore, the calibration operation is preferably performed appropriately in response to changes in operating conditions.

[0126] Here, the semiconductor device in this embodiment is configured to perform calibration operations in parallel with the core operation. Based on this configuration, a semiconductor device can be provided that operates reliably without consuming time during the calibration operation.

[0127] The timing of the calibration action is explained below. Figures 14 and 15 are timing diagrams used to explain the timing of the calibration action.

[0128] Figure 14 illustrates the instruction sets input to the bare die memory (MD) during read operations. The first instruction set corresponds to a normal read operation. The second instruction set corresponds to a cache read operation. The third instruction set corresponds to a data output operation.

[0129] Normal read operations and cache read operations are performed in roughly the same way. However, when performing a normal read operation, the memory die (MD) is in a busy state until the read operation ends. On the other hand, when performing a cache read operation, the memory die (MD) becomes cache-ready before the read operation ends. The data output operation is the operation of reading user data from the memory cell array (MCA) and outputting it to the cache memory (CM) via the data signal input / output terminals DQ0~DQ7 and then outputting it to the controller die (CD).

[0130] In the example shown, when the first instruction set is input, the memory die MD is in the ready state and the RY / / BY terminal is in the "H" state.

[0131] The first instruction set contains data CR0, CR1, Add, and CR2.

[0132] That is, the controller die CD (Figure 1) inputs data CR0 and CR1 as instruction data Cmd to the memory die MD. Specifically, when the voltages of the data signal input / output terminals DQ0~DQ7 are set to "H" or "L" respectively, and "H" is input to the external control terminal CLE, and "L" is input to the external control terminal ALE, the external control terminal / WE rises from "L" to "H". Data CR0 and CR1 are the instructions input at the start of the read operation.

[0133] Next, the controller die CD inputs the address data Add to the memory die MD. That is, with the voltages of the data signal input / output terminals DQ0~DQ7 set to "H" or "L" respectively, and "L" input to the external control terminal CLE and "H" input to the external control terminal ALE, the external control terminal / WE is raised from "L" to "H". The address data Add is input 5 times.

[0134] Secondly, the controller die CD inputs data CR2 as instruction data Cmd to the memory die MD. Data CR2 indicates that the input of the instruction set related to the normal read operation has ended.

[0135] When the first instruction set is input, the memory die MD becomes busy, and the RY / / BY terminals change from "H" to "L". Simultaneously, access to the memory die MD is disabled. Furthermore, a read operation begins in the memory die MD.

[0136] When the read operation is completed, the memory die MD becomes ready, and the RY / / BY terminals change from the "L" state to the "H" state. This allows access to the memory die MD. In the illustrated example, a second instruction set is input in this state.

[0137] The second instruction set is essentially the same as the first. However, in the second instruction set, input data CR3 replaces data CR2. Data CR3 indicates that the input of the instruction set related to the cache read operation has ended.

[0138] When the second instruction set is input, the memory die MD becomes busy, and the RY / / BY terminals change from "H" to "L". Simultaneously, access to the memory die MD is disabled. Furthermore, a read operation begins in the memory die MD.

[0139] After a fixed period following the input of the second instruction set, the memory die MD becomes cache-ready, and the RY / / BY terminals change from "L" to "H". This allows access to the memory die MD. In the illustrated example, the third instruction set is input in this state.

[0140] The third instruction set includes data CR4, Add, and CR5. Data CR4 is the instruction entered at the beginning of a data output action. CR5 is the instruction indicating that the input of the instruction set related to the data output action has ended.

[0141] When the third instruction set is input, the controller die CD causes the memory die MD to output user data via data signal input / output terminals DQ0~DQ7. That is, the voltages of the data signal input / output terminals DQ0~DQ7 are set to "H" or "L" respectively, corresponding to each bit of the user data, by the terminating resistor adjustment unit 210 as described with reference to FIG10. Furthermore, the data output from the data signal input / output terminals DQ0~DQ7 is switched by switching the signals of the external control terminals / RE, RE. Therefore, the controller die sequentially switches the data output from the external control terminals / RE, RE, and acquires the data output from the data signal input / output terminals DQ0~DQ7.

[0142] Here, the semiconductor device of this embodiment can begin calibration in both a ready state and a cache-ready state. In the example of FIG14, the state before the first instruction set input and the state from the end of the normal readout operation to the second instruction set input correspond to the ready state. Furthermore, the state after the second instruction set input, when the RY / / BY terminal rises, and before the third instruction set input corresponds to the cache-ready state.

[0143] Furthermore, the core operation is not performed in the ready state, but the read operation is performed in the cache ready state illustrated in Figure 14. Therefore, when the calibration operation begins in this cache ready state, the calibration operation and the read operation are performed in parallel.

[0144] Figure 15 illustrates the instruction sets input to the memory die (MD) during write operations. The first instruction set corresponds to cache write operations. The second instruction set corresponds to normal write operations.

[0145] Normal write operations and cache write operations are performed in roughly the same way. However, when performing a normal write operation, the memory die (MD) is in a busy state until the write operation ends. On the other hand, when performing a cache write operation, the memory die (MD) becomes cache-ready before the write operation ends.

[0146] In the example shown, when the first instruction set is input, the memory die MD is in the ready state and the RY / / BY terminal is in the "H" state.

[0147] The first instruction set contains data CW0, CW1, Add, DIN, and CW2.

[0148] That is, the controller die CD (Figure 1) inputs data CW0 and CW1 as instruction data Cmd to the memory die MD. Data CW0 and CW1 are instructions input at the start of the write operation.

[0149] Secondly, the controller die CD inputs the address data Add to the memory die MD.

[0150] Secondly, the controller die CD inputs the data DIN as user data Dat to the memory die MD. That is, while setting the voltage of the data signal input / output terminals DQ0~DQ7 to "H" or "L" corresponding to each bit of the data DIN, and inputting "L" to the external control terminal CLE and "L" to the external control terminal ALE, the input signals of the data strobe signal input / output terminals DQS and / DQS are switched. Furthermore, at this time, the input impedance of the data signal input / output terminals DQ0~DQ7 is adjusted by the terminating resistor adjustment unit 210 as described with reference to FIG10.

[0151] Secondly, the controller die CD inputs data CW2 as instruction data Cmd to the memory die MD. Data CW2 indicates that the input of the instruction set related to the cache write operation has ended.

[0152] When the first instruction set is input, the memory die MD becomes busy, and the RY / / BY terminals change from "H" to "L". Simultaneously, access to the memory die MD is disabled. Furthermore, a write operation begins in the memory die MD.

[0153] After a fixed period following the input of the first instruction set, the memory die MD becomes cache-ready, and the RY / / BY terminals change from "L" to "H". This allows access to the memory die MD. In the illustrated example, the second instruction set is input in this state.

[0154] The second instruction set is essentially the same as the first. However, in the second instruction set, input data CW3 is used instead of data CW2. Data CW3 indicates that the input of the instruction set related to the normal write operation has ended.

[0155] When the second instruction set is input, the memory die MD becomes busy, and the RY / / BY terminals change from "H" to "L". Simultaneously, access to the memory die MD is disabled. Furthermore, the write operation corresponding to the second instruction set begins immediately after the write operation corresponding to the first instruction set is completed.

[0156] Here, in the semiconductor device of this embodiment, the calibration operation can be started in both a ready state and a cache ready state. In the example of FIG15, the state before the first instruction set input corresponds to the ready state. Also, the state before the second instruction set input after the RY / / BY terminal rises after the first instruction set input corresponds to the cache ready state.

[0157] Furthermore, no core actions are performed in the ready state; instead, write actions are performed in the cache-ready state illustrated in Figure 15. Therefore, when the calibration action begins in this cache-ready state, the calibration action and the write action are performed in parallel.

[0158] [Composition of Clock Signal Control Circuit] When performing the calibration action, a clock signal is generated for the calibration action and input to the sequencer SQC (Figure 9).

[0159] Here, when the calibration action begins without the core action being performed, a clock signal is generated at the moment the calibration action begins.

[0160] On the other hand, it is considered that when a calibration action is started while the core action is being performed, the clock signal used in the core action may also be used in the calibration action. However, in this method, depending on the relationship between the time point of starting the calibration action and the phase in the clock signal, the waveform of the clock pulse used for the calibration action may be disordered, leading to abnormalities in the calibration action.

[0161] To prevent this, one approach is to consider setting up a separate clock signal generation circuit for calibration operations. However, this method would increase the overall circuit area of ​​the semiconductor device.

[0162] Therefore, the semiconductor device of this embodiment includes a clock signal control circuit that can stably generate clock pulses for calibration operations even during the execution of core operations. Hereinafter, this clock signal control circuit will be described with reference to the drawings.

[0163] Figure 16 is a schematic circuit diagram showing the configuration of the clock signal control circuit. Figures 17 and 18 are schematic circuit diagrams showing a portion of the clock signal control circuit.

[0164] As shown in Figure 16, the sequencer SQC (Figure 9) inputs signals S101 and S103 to the clock signal control circuit. Signal S101 indicates the execution status of the core action, becoming "H" during core action execution and "L" otherwise. Signal S103 indicates the execution status of the calibration action, becoming "H" during calibration action execution and "L" otherwise.

[0165] The clock signal control circuit includes a clock signal generation circuit 401 that generates a clock signal as signal S105 in response to input signals S101 and S103, and an output circuit 402 (clock signal output circuit) that outputs signal S105 as signal S109 in response to gate signal S108. Furthermore, the clock signal control circuit includes an adjustment circuit 403 and / or circuit 404 for modulating signal S103.

[0166] The clock signal generation circuit 401 outputs signal S105 and signal OSC. When a "H" state signal is input to the clock signal generation circuit 401, the clock signal is output as signal S105 and signal OSC. When a "L" state signal is input to the clock signal generation circuit 401, the "L" state signal is output as signal S105 and signal OSC. Signal OSC can be used as the clock signal for core operations. The frequency of signal OSC can be different from the frequency of signal S105.

[0167] When the gate signal S108 is in the "H" state, circuit 402 outputs signal S105 as signal S109. Similarly, when the gate signal S108 is in the "L" state, circuit 402 outputs the "L" state signal as signal S109. Signal S109 can be used as a clock signal for calibration operations.

[0168] Input signals S103 and OSC to adjustment circuit 403. Adjustment circuit 403 delays signal S103 by a time equivalent to several pulses in the clock signal output from clock signal generation circuit 401, and then outputs it.

[0169] The output signal S103 of the OR circuit 404 is logically summed with the output signal of the adjustment circuit 403. Therefore, the output signal of the OR circuit 404 rises accordingly with the rise of the signal S103, and falls after a time equivalent to the aforementioned number of pulses following the fall of the signal S103.

[0170] Next, the circuit that generates the signal S104 input to the clock signal generation circuit 401 will be described.

[0171] The clock signal control circuit includes OR circuits 411 and 412 disposed in the signal path between signal S101 and signal S104.

[0172] Input signal S101 to OR circuit 411. Also, input signal S101 to OR circuit 411 and output signal S108 to circuit 413. And the logical product of output signal OSC of circuit 413 and the inverted signal of gate signal S108.

[0173] The output signal S104 of OR circuit 412 is input to OR circuit 412, which is the output signal of OR circuit 411. Also, the signal OSC is input to OR circuit 412.

[0174] Furthermore, a fall detection circuit 414, a latch circuit 415, and an AND circuit 416 are provided in the signal path between one of the output terminals of the OR circuit 411 and one of the input terminals of the OR circuit 412. These configurations can temporarily supply a signal in the "L" state to the clock signal generation circuit 401.

[0175] For example, as shown in Figure 17, the descent detection circuit 414 includes a NOT OR circuit 501 and an even number of subordinate NOT circuits 502. The output signal of the OR circuit 411 is input to one input terminal of the NOT OR circuit 501. The inverted signal of the output signal of the OR circuit 411, delayed by the even number of NOT circuits 502, is input to the other input terminal of the NOT OR circuit 501.

[0176] When the output signal of OR circuit 411 is in the "H" state, "H" is input to one input terminal of NOT circuit 501, so NOT circuit 501 outputs "L". During a fixed period after the output signal of OR circuit 411 switches from the "H" state to the "L" state, "L" is input to one input terminal of NOT circuit 501, and "L" is also input to the other input terminal of NOT circuit 501, so NOT circuit 501 outputs "H". After a fixed period has elapsed since the output signal of OR circuit 411 switched to the "L" state, "H" is input to the other input terminal of NOT circuit 501, so NOT circuit 501 outputs "L".

[0177] When the gate signal S108 is in the "L" state, the latch circuit 415 (Figure 16) saves and outputs the output signal of the drop detection circuit 414. When the gate signal S108 is in the "H" state, the latch circuit 415 maintains the saved data and the output signal.

[0178] The latch circuit 415 generally outputs a signal in the "L" state. However, when the gate signal S108 is in the "L" state (for example, when the calibration operation is not being performed) or when the output signal of circuit 411 switches from the "H" state to the "L" state (for example, when the core operation ends), the latch circuit 415 temporarily outputs a signal in the "H" state.

[0179] Furthermore, even when the gate signal S108 is in the "H" state (e.g., during calibration) or the output signal of circuit 411 switches from the "H" state to the "L" state (e.g., after the core operation ends), the output signal of latch circuit 415 remains in the "L" state.

[0180] The inverted signal of signal S102 output from latch circuit 415 is input to one input terminal of circuit 416. The output signal of OR circuit 404 is input to the other input terminal of circuit 416.

[0181] When signal S103 is in the "H" state and for a period of time equivalent to the aforementioned pulses after signal S103 switches to the "L" state, circuit 416 basically outputs a signal in the "H" state. However, during the period when the latch circuit 415 outputs a signal in the "H" state, it also outputs a signal in the "L" state.

[0182] Next, the circuit that generates the gate signal S108 will be explained.

[0183] The clock signal control circuit includes a latch circuit 421, a flip-flop 422 (gate signal output circuit), a switch circuit 423, and a latch circuit 424 disposed in the signal path between signal S103 and gate signal S108.

[0184] A delay circuit 425 is connected to the input terminal of the latch circuit 421. When the output signal of the delay circuit 425 is in the "L" state, the latch circuit 421 stores and outputs signal 103. Furthermore, when the output signal of the delay circuit 425 is in the "H" state, the latch circuit 421 maintains the stored data and the output signal. The delay circuit 425 delays the output signal of the OR circuit 404 and outputs it.

[0185] The output signal of latch circuit 421 becomes "H" state corresponding to the rise of signal S103. Furthermore, after signal S103 falls, after a time equivalent to the aforementioned number of pulses, and then after the delay time of delay circuit 425, it becomes "L" state.

[0186] The output signal of flip-flop 422 is switched to the output signal of latch circuit 421 in response to the rise of signal S105.

[0187] A delay signal supplementary circuit 426 is connected to the switching circuit 423. For example, as shown in FIG18, the delay signal supplementary circuit 426 includes an OR circuit 511 and an even number of subordinately connected NOT circuits 512. The output signal of the OR circuit 411 is input to one input terminal of the OR circuit 511. The output signal of the OR circuit 411, which is delayed by the even number of NOT circuits 502, is input to the other input terminal of the OR circuit 511.

[0188] When the output signal of OR circuit 411 is in the "H" state, "H" is input to one input terminal of OR circuit 511, so OR circuit 511 outputs "H". During a fixed period after the output signal of OR circuit 411 switches from the "H" state to the "L" state, "H" is input to the other input terminal of OR circuit 511, so OR circuit 511 outputs "H". After a fixed period has elapsed since the output signal of OR circuit 411 switched to the "L" state, "L" is input to one input terminal of OR circuit 511 and also to the other input terminal of OR circuit 511, so OR circuit 511 outputs "L".

[0189] When the output signal of the delay signal supplementary circuit 426 is in the "H" state (when the output signal of the OR circuit 411 is in the "H" state, or during a fixed period after the output signal of the OR circuit 411 switches to the "L" state), the switching circuit 423 (Fig. 16) outputs the output signal of the flip-flop 422. Furthermore, when the output signal of the delay signal supplementary circuit 426 is in the "L" state (or after a fixed period has elapsed after the output signal of the circuit 411 switches to the "L" state), the switching circuit 423 outputs the output signal of the latch circuit 421.

[0190] The latch circuit 424 outputs a gate signal S108. When signal 105 is in the "L" state, the latch circuit 424 saves and outputs the signal S107 output from the switch circuit 423. Furthermore, when signal 105 is in the "H" state, the latch circuit 424 maintains the saved data and the output signal.

[0191] [Operation of the clock signal control circuit] Figures 19 to 21 are pattern waveform diagrams used to illustrate the operation of the clock signal control circuit.

[0192] Figure 19 shows the situation when the calibration action begins while the core action is being performed.

[0193] In the illustrated example, since the core operation is being performed, signal S101 is in the "H" state. Therefore, signal S104 is also in the "H" state, and the clock signal is output as signal S105. Furthermore, signal S106 is also in the "H" state, and the switching circuit 423 outputs the output signal of the flip-flop 422 as signal S107.

[0194] In this state, when signal S103 rises from the "L" state to the "H" state at time t101, at time t102 when signal S105 rises, the output signal of flip-flop 422 becomes the "H" state, and correspondingly, signal S107 output from switch circuit 423 also becomes the "H" state. Furthermore, at time t103 when signal S105 falls, gate signal S108 becomes the "H" state. Finally, at subsequent time points, the clock signal used for calibration is output as signal S109.

[0195] Figure 20 shows the situation when the calibration action begins without performing the core action.

[0196] In the illustrated example, since the core action is not performed, signal S101 is in the "L" state. Also, signal S104 is in the "L" state, and no clock signal is output from clock signal generation circuit 401. Furthermore, signal S106 is also in the "L" state, and switching circuit 423 outputs the output signal of latching circuit 421 as signal S107.

[0197] In this state, when signal S103 rises from the "L" state to the "H" state at time t111, gate signal S108 becomes the "H" state. Also, at time t112, signal S104 becomes the "H" state via OR circuit 404, OR circuit 416, and OR circuit 412, and the clock signal is output as signal S105. Furthermore, at subsequent time points, the clock signal used for calibration is output as signal S109.

[0198] Figure 21 shows the situation when the calibration action begins at the point when the core action ends.

[0199] In the illustrated example, at time t121, signal S101 switches to the "L" state, and signal S104 also switches to the "L" state. Furthermore, at this time, the output signal of the drop detection circuit 414 rises, and the gate signal S108 is in the "L" state. Therefore, the signal S102 output from the latch circuit 415 rises to the "H" state. Consequently, the output signal of the latch circuit 416 becomes "L", the "L" state signal is output from the latch circuit 412, and the output of the clock signal from the clock signal generation circuit 401 stops.

[0200] Furthermore, during a fixed period after the output signal of the circuit 411 drops to the "L" state, the signal S106 output from the delay signal supplement circuit 426 remains in the "H" state. Therefore, the signal S107 output from the switching circuit 423 remains at the output signal of the flip-flop 422 ("L" state).

[0201] In this state, at time t121, even if signal S103 rises from the "L" state to the "H" state, signal S102 is still in the "H" state. Therefore, signal S104 is still in the "L" state and will not start outputting clock signals from clock signal generation circuit 401.

[0202] After a fixed period of time t122 ​​has elapsed since signal S101 switched to the "L" state, signal S102 drops to the "L" state and signal S104 rises to the "H" state, and clock signals begin to be output from clock signal generation circuit 401.

[0203] Furthermore, the signal S106 output from the delay signal supplementary circuit 426 drops to the "L" state, and the signal S107 output from the switching circuit 423 becomes the output signal of the latching circuit 421 ("H" state). As a result, the gate signal S108 becomes the "H" state, and the clock signal used for calibration is output as signal S109.

[0204] [Effects of the First Implementation] In this embodiment, the clock signal control circuit includes a flip-flop 422 disposed in the signal path between signal S103 and gate signal S108. The output signal of flip-flop 422 is switched to the output signal of latch circuit 421 in response to the rise of signal S105.

[0205] Based on this configuration, for example, as illustrated with reference to FIG19, the relationship between the phase of the clock signal output as signal S109 and the rising point of the gate signal S108 can be adjusted to stably perform the calibration operation.

[0206] Furthermore, the clock signal control circuit in this embodiment includes a switch circuit 423 connected between the output terminal of the flip-flop 422 and the input terminal of the gate signal S108. Also, when the signal S106 is in the "H" state, the switch circuit 423 outputs the output signal of the flip-flop 422; when the signal S106 is in the "L" state, it outputs the signal S103 input via the latch circuit 421.

[0207] According to this configuration, when signal S106 is in the "H" state, a stable calibration operation as described above can be achieved, and when signal S106 is in the "L" state, for example, as explained with reference to FIG20, a clock signal as signal S109 can be output immediately.

[0208] Furthermore, for example, if the decrease of signal S106 and signal S101 corresponds to the decrease, and signal S103 increases at that point, then at an inappropriate time, the "H" state signal may be output from the switching circuit 423 while the clock signal is being output from the clock signal generation circuit 401, causing the pulse waveform in the clock signal that is signal S109 to be destroyed, resulting in abnormal calibration operation.

[0209] Therefore, in the clock signal control circuit of this embodiment, during a fixed period after the output signal of the OR circuit 411 drops, the switching circuit 423 outputs the output signal of the flip-flop 422.

[0210] Furthermore, the clock signal control circuit in this embodiment includes an OR circuit 412, which has an output terminal connected to the clock signal generation circuit 401. Also, one of the input terminals of the OR circuit 412 is input to the output signal of the OR circuit 411. Also, the other input signal of the OR circuit 412 becomes "H" after a fixed period following the output signal of the OR circuit 404 being in the "H" state and the output signal of the OR circuit 411 switching to the "L" state; otherwise, it becomes "L".

[0211] Based on this configuration, for example, as illustrated with reference to FIG21, the gate signal S108 remains in the "L" state for a fixed period after the signal S101 falls. Furthermore, after a fixed period following the fall of signal S101, a clock signal as signal S109 is output. This allows adjustment of the relationship between the phase of the clock signal output as signal S109 and the rising point of the gate signal S108, thus stably performing the calibration operation. Furthermore, it effectively suppresses the disruption of the pulse waveform initially output from circuit 402.

[0212] [Second Implementation] Next, the semiconductor device of the second embodiment will be described. In the following description, the same symbols are used for the parts that are the same as those in the first embodiment, and the descriptions are omitted.

[0213] The semiconductor device of the second embodiment is basically constructed in the same way as the semiconductor device of the first embodiment. However, the clock signal control circuit of the second embodiment is different from the clock signal control circuit of the first embodiment.

[0214] Figure 22 is a schematic circuit diagram showing the configuration of the clock signal control circuit in the second embodiment. Figure 23 is a schematic circuit diagram showing a portion of the configuration of the clock signal control circuit.

[0215] As shown in Figure 22, the clock signal control circuit of the second embodiment is basically constructed in the same way as the clock signal control circuit of the first embodiment.

[0216] However, when the gate signal S204 is in the "H" state, the circuit 402 of the second embodiment outputs signal S205 as signal S109. Also, when the gate signal S204 is in the "L" state, the circuit 402 outputs the signal in the "L" state as signal S109.

[0217] In the first embodiment, the signal S105 output from the clock signal generation circuit 401 is directly input to the input circuit 402. In the second embodiment, delay circuits 701 and 702 are provided in the signal path between the output signal of the clock signal generation circuit 401 and the input signal of the input circuit 402. Furthermore, the output signal of the clock signal generation circuit 401 is delayed by the delay circuits 701 and 702 to generate signal S205, which is then input to the input circuit 402.

[0218] Furthermore, in the second embodiment, the circuit configuration for generating the signal S104 input to the clock signal generation circuit 401 differs from that in the first embodiment. For example, the clock signal control circuit in the second embodiment does not include the fall detection circuit 414, the latch circuit 415, and the clock signal control circuit 416. Also, one of the input terminals of the clock signal control circuit 412 is input to the output signal of the clock signal control circuit 404, rather than the output signal of the clock signal control circuit 416.

[0219] Furthermore, in the second embodiment, the circuit configuration for generating the gate signal S204 differs from that in the first embodiment. For example, the clock signal control circuit in the second embodiment does not include the switching circuit 423. Instead, the clock signal control circuit in the second embodiment includes a rise delay circuit 703 and a latch circuit 704 disposed in the signal path between the output signal of the latch circuit 421 and the input signal of the flip-flop 422.

[0220] For example, as shown in Figure 23, the rise delay circuit 703 includes an AND circuit 711 and an even number of NOT circuits 712 connected subordinately. The output signal of the latch circuit 421 (Figure 22) is input to one input terminal of the AND circuit 711. The output signal of the latch circuit 421, which is delayed by the even number of NOT circuits 712, is input to the other input terminal of the AND circuit 711.

[0221] When the output signal of latch circuit 421 is in the "L" state, "L" is input to one input terminal of circuit 711, and therefore circuit 711 outputs "L". During a fixed period after the output signal of latch circuit 421 switches from the "L" state to the "H" state, "L" is input to the other input terminal of circuit 711, and therefore circuit 711 outputs "L". After a fixed period has elapsed since the output signal of latch circuit 421 switches to the "H" state, "H" is input to one input terminal of circuit 711, and "H" is also input to the other input terminal of circuit 711, and therefore circuit 711 outputs "H".

[0222] When the signal S201 output from the clock signal generation circuit 401 is in the "H" state, the latch circuit 704 (Fig. 22) saves and outputs the signal S103' output from the rise delay circuit 703. Furthermore, when the signal S201 is in the "L" state, the latch circuit 704 maintains the saved data and the output signal.

[0223] In the second embodiment, the output signal of the flip-flop 422 is switched to the output signal of the latch circuit 704 in response to the rise of the signal output from the delay circuit 701.

[0224] The latch circuit 424 of the second embodiment outputs a gate signal S204. When signal S205 is in the "H" state, the latch circuit 424 saves and outputs the signal S203 output from the flip-flop 422. Furthermore, when signal S205 is in the "L" state, the latch circuit 424 maintains the saved data and the output signal.

[0225] [Operation of the clock signal control circuit] Figures 24 and 25 are pattern waveform diagrams used to illustrate the operation of the clock signal control circuit.

[0226] Figure 24 shows the situation when the calibration action begins while the core action is being performed.

[0227] In the example shown, since the core action is being performed, signal S101 is in the "H" state. Therefore, signal S104 is also in the "H" state, and the clock signal is output as signal S201.

[0228] In this state, when signal S103 rises from the "L" state to the "H" state at time t201, after a predetermined delay time, signal S103' also rises to the "H" state at time t202. Subsequently, at time t203 when signal S201 rises, signal S202 output from latch circuit 704 becomes "H". After another predetermined delay time, at time t204 when the output signal of delay circuit 701 rises, signal S203 output from flip-flop 422 becomes "H". After yet another predetermined delay time, at time t205 when signal S205 output from delay circuit 702 rises, gate signal S204 becomes "H". Finally, at subsequent times, the clock signal used for calibration is output as signal S109.

[0229] Figure 25 shows the situation when the calibration action begins without performing the core action.

[0230] In the example shown, since the core action is not performed, signal S101 is in the "L" state. Also, signal S104 is in the "L" state, and no clock signal is output from the clock signal generation circuit 401.

[0231] In this state, when signal S103 rises from "L" state to "H" state at time t211, signal S104 becomes "H" state via OR circuit 404 and OR circuit 412, and the clock signal is output as signal S201.

[0232] Furthermore, after a predetermined delay time, at time t212, signal S103' also rises to the "H" state. Subsequently, at time t213 when signal S201 rises, signal S202 output from latch circuit 704 becomes "H". Again, after a predetermined delay time, at time t214 when the output signal of delay circuit 701 rises, signal S203 output from flip-flop 422 becomes "H". Again, after another predetermined delay time, at time t215 when signal S205 output from delay circuit 702 rises, gate signal S204 becomes "H". Finally, at this subsequent time point, the clock signal used for calibration is output as signal S109.

[0233] [Effects of the Second Implementation] In this embodiment, the clock signal control circuit also includes a flip-flop 422 disposed in the signal path between signal S103 and gate signal S204. Furthermore, the output signal of flip-flop 422 is switched to the output signal of latch circuit 704 in accordance with the rise of the signal obtained by delaying signal S201.

[0234] Based on this configuration, for example as illustrated with reference to FIG24, the relationship between the phase of the clock signal output as signal S109 and the rising point of the gate signal S204 can be adjusted to stably perform the calibration operation.

[0235] [Third Implementation] Next, the semiconductor device of the third embodiment will be described. In the following description, the same symbols are used for the parts that are the same as in the first embodiment, and the description is omitted.

[0236] The semiconductor device of the third embodiment is basically constructed in the same way as the semiconductor device of the first embodiment. However, the semiconductor device of the third embodiment includes four memory cell arrays MCA0, MCA1, MCA2, and MCA3. These four memory cell arrays MCA can each independently perform core operations.

[0237] Figure 26 is a timing diagram used to explain the timing points at which calibration operations can be performed in the semiconductor device of the third embodiment.

[0238] In the illustrated example, firstly, the instruction set corresponding to the normal read operation of memory cell array MCA0 is input, and memory cell array MCA0 becomes busy. Simultaneously, the terminal RY / / BY switches from the "H" state to the "L" state.

[0239] Then, input the instruction set corresponding to the normal read operation of the memory cell array MCA1, and the memory cell array MCA1 becomes busy.

[0240] Then, the normal readout operation corresponding to memory cell array MCA0 ends, and memory cell array MCA0 becomes ready. However, since the normal readout operation corresponding to memory cell array MCA1 is being performed at this point, the terminal RY / / BY remains in the "L" state.

[0241] Then, input the instruction set for the cache read operation corresponding to memory cell array MCA0, and memory cell array MCA0 becomes busy.

[0242] After a fixed period following the input of the instruction set for the cache read operation corresponding to memory cell array MCA0, memory cell array MCA0 becomes cache ready. Furthermore, when the normal read operation corresponding to memory cell array MCA1 ends, memory cell array MCA1 becomes ready. Simultaneously, the RY / / BY terminal switches from the "L" state to the "H" state.

[0243] Then, the instruction set corresponding to the cache read operation of memory cell array MCA1 is input, and memory cell array MCA1 enters a busy state. Accompanying this, the terminal RY / / BY switches from the "H" state to the "L" state.

[0244] After a fixed period following the input of the instruction set corresponding to the cache read operation of memory cell array MCA1, memory cell array MCA1 becomes cache ready. Simultaneously, the RY / / BY terminal switches from the "L" state to the "H" state.

[0245] In this embodiment of the semiconductor device, calibration can begin as long as any one of the four memory cell arrays (MCAs) is in a ready or cache-ready state. In the example of Figure 26, since memory cell arrays MCA2 and MCA3 are always in a ready state, calibration can begin at any point in time.

[0246] Furthermore, in this embodiment, the controller bare die CD can confirm whether the calibration operation has ended by reading the status. In this case, for example, the status data corresponding to any unused one of the four memory cell arrays MCA can be used as data to indicate the execution status of the calibration operation.

[0247] Furthermore, in this embodiment, the calibration operation can be started only when the terminals RY / / BY are in the "H" state (when the memory die MD is in the ready state or the cache is in the ready state).

[0248] [Other Implementation Methods] The semiconductor devices of the first to third embodiments have been described above. However, these configurations are merely examples, and the specific configurations may be appropriately modified. For example, in the first to third embodiments, the communication between the memory die MD and the controller die CD may be based on an SDR (Single data rate) interface, a switched DDR (Double data rate) interface, or an ONFI (Open NAND flash interface).

[0249] [other] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0250] 10: Memory System 20: Mainframe PC 100: Semiconductor substrate 101: Insulation layer 110: Conductive layer 112: Semiconductor layer 120: Semiconductor column 121: Impurity Region 125: Insulation layer 130: Gate insulating film 210: Terminal resistor adjustment unit 211: Pull-up circuit 212: Pull-down circuit 213: Resistive element 214: Transistor 215: Resistive element 216: Transistor 220: Terminal resistor adjustment unit control circuit 221: or circuit 222: and circuit 300: Series resistor 310: First Replication Unit 311: Pull-up circuit 313: Resistive element 314: Transistor 320: Control circuit for the first replication unit 321: Counter 322: Comparator 323: ESD countermeasure circuit 330: Second Replication Unit 331: Pull-up circuit 332: Pull-down circuit 333: Resistor element 334: Transistor 335: Resistor element 336: Transistor 340: Control circuit for the second replication unit 341: Counter 342: Comparator 343: ESD Countermeasure Circuit 350: Reference voltage generation circuit 360: Data latch circuit 370: Calibration control circuit 401: Clock signal generation circuit 402: and the circuit (clock signal output circuit) 403: Adjustment Circuit 404: or circuit 411: or circuit 412: or circuit 413: and circuit 414: Descent Detection Circuit 415: Latch circuit 416: and circuit 421: Latch circuit 422: Flip-Flipper (Gate Signal Output Circuit) 423: Switching Circuit 424: Latch circuit 425: Delay Circuit 426: Delayed Signal Additional Circuit 501: NOT OR circuit 502: Not a circuit 511: or circuit 512: Non-circuit 701: Delay Circuit 702: Delay Circuit 703: Rise Delay Circuit 704: Latch Circuit 711: and circuit 712: Non-circuit Add: Address information ADR: Address Register ALE: External control terminal B: Joint line BL: Bitline BLP: Bitline BLW: Bitline BLK: Memory Block CA: Row Address Cb: Contact electrode CC: Contact Electrode CD: Controller bare die Ch: Contact electrode CLE: External control terminal CM: Cache Memory Cmd: Command Information CMR: Instruction Register CR0: Data CR1: Data CR2: Data CR3: Data CR4: Data CR5: Data CTR: Logic Circuit CW0: Data CW1: Data CW2: Data CW3: Data DAt: User Profile DB: Data Bus DIN: Data DQ0~DQ7: Data signal input / output terminals DQS: Data strobe signal input / output terminal I / O: Input / output control circuit MC: Memory Cell MCA: Memory Cell Array MCA0: Memory Cell Array MCA1: Memory Cell Array MCA2: Memory Cell Array MCA3: Memory Cell Array MD: Memory Bare Crystal MS: Memory String MSB: Mounting baseboard NCODE <m:0>:material OSC: Signal P: Solder pad electrode PC: Peripheral Circuits PCODE <n:0>:material RA: Column address RD: Column Decoder RE: External control terminal RY / / BY: Terminal S101: Signal S102: Signal S103: Signal S103': Signal S104: Signal S105: Signal S106: Signal S107: Signal S108: Gate signal S109: Signal S201: Signal S202: Signal S203: Signal S204: Gate signal S205: Signal SA: Sensing Amplifier SGD: Drain-side Selective Gate Line SGDT: Drain-side Selective Gate Line SGS: Source-side gate selection SGSB: Source-side gate selection line SL: Source Line SQC: Sequencer ST: Inter-block insulation layer STD: Drain-side selective transistor STDT: Drain-side Selective Transistor STR: State register STS: Source-Side Selective Transistor STSB: Source-side selective transistor Stt: Status Data SU: Serial unit t101: Time point t102: Time point t103: Time point t111: Time point t112: Time point t121: Time point t122: Time point t201: Time point t202: Time point t203: Time point t204: Time point t205: Time point t211: Time point t212: Time point t213: Time point t214: Time point t215: Time point Tr: transistor TRA_EN<6:0>: Signal line Up* <0> ~Up* <n>Signal line Dn* <0> ~Dn* <m>Signal line VCC: Power supply voltage VCGR: Readout Voltage VDD: Operating voltage VDDQ: Voltage VERA: Erasure voltage VPASS: Write Path Voltage VPGM: Programming Voltage VREAD: Read path voltage VSG: Voltage VSG': Voltage VSG: Voltage VSGD: Voltage VSRC: Voltage VSS: Grounding voltage VG: Voltage generation circuit WL: Character Line WLU: Non-selective character line WLS: Select Character Line X: Direction Y: direction Z: Direction ZDRV: Impedance ZQ: Calibration Electrode / CE: External control terminal / DQS: Data strobe signal input / output terminal / WE: External control terminal / RE: External control terminal< / m> < / n> < / m> < / m> < / n> < / n>

Claims

1. A semiconductor device comprising: electrodes; pull-up circuits and pull-down circuits, which control the voltage of the electrodes in accordance with input data; internal circuitry outputting the data to be supplied to the pull-up circuits and pull-down circuits; a sequencer capable of performing an operation of the internal circuitry and a calibration operation of adjusting the output impedance of the pull-up circuits and pull-down circuits; and a clock signal control circuitry supplying a first clock signal to the sequencer when the calibration operation is performed; and the clock signal control circuitry comprising: a clock signal generation circuitry outputting a second clock signal when at least one of the operation of the internal circuitry and the calibration operation is performed; a clock signal output circuitry outputting the second clock signal as the first clock signal in accordance with a gate signal; and a gate signal output circuitry outputting a signal indicating the execution state of the calibration operation as a gate signal in accordance with the switching of the second clock signal.

2. The semiconductor device of claim 1 further includes a latching circuit disposed in the signal path between the output signal of the gate signal output circuit and the input signal of the clock signal output circuit, wherein the latching circuit inputs the input signal to the clock signal output circuit at a time different from the time at which the gate signal output circuit outputs the gate signal.

3. The semiconductor device of claim 2, wherein at one of the rising and falling points of the second clock signal, the gate signal output circuit outputs a signal indicating the execution state of the calibration operation as the gate signal, and at the other of the rising and falling points of the second clock signal, the latch circuit inputs the input signal of the latch circuit to the clock signal output circuit.

4. The semiconductor device of claim 2 further includes a delay circuit disposed in the signal path between the input terminal of the gate signal output circuit into which the second clock signal is input and the input terminal of the latch circuit into which the second clock signal is input.

5. The semiconductor device of claim 1 further includes a switching circuit disposed in the signal path between the output signal of the gate signal output circuit and the input signal of the clock signal output circuit. When the operation of the internal circuit is performed, the switching circuit inputs the output signal of the gate signal output circuit as the gate signal to the clock signal output circuit, and when the operation of the internal circuit is not performed, it inputs a signal indicating the execution state of the calibration operation as the gate signal to the clock signal output circuit.

6. The semiconductor device of claim 5, wherein during a fixed period after the completion of the operation of the internal circuit, the switching circuit inputs the output signal of the gate signal output circuit as the gate signal to the clock signal output circuit.

7. The semiconductor device of claim 6 further includes an OR circuit, which has an output terminal, a first input terminal, and a second input terminal connected to the clock signal generating circuit. A first signal is input to the first input terminal, which becomes a first state when the operation of the internal circuit is performed and a second state when it is not performed. A second signal is input to the second input terminal, which becomes a third state after a fixed period following the switching of the first signal from the first state to the second state and during the calibration operation, and a fourth state in other states. When the first signal is in the first state and when the second signal is in the third state, the OR circuit causes the clock signal generating circuit to output the second clock signal.

8. The semiconductor device of claim 1, wherein the internal circuitry includes a memory cell for storing data, and the operation of the internal circuitry is a read operation, a write operation, or an erase operation of the memory cell.

9. The semiconductor device of claim 1, wherein the internal circuitry further comprises a memory string for storing data, the memory string comprising a plurality of memory cell transistors connected in series.

10. The semiconductor device of claim 1, wherein the above calibration operation can be initiated when the device is in a ready state and a cache ready state.

11. The semiconductor device of claim 1, wherein the internal circuitry comprises a plurality of memory cell arrays, and the calibration operation can be initiated when any of the plurality of memory cell arrays is in a ready state or a cache ready state.

12. The semiconductor device of claim 11, wherein data representing the execution status of the above-mentioned calibration operation can be output as status data instead of information representing the status of the plurality of memory cell arrays that are in a ready state or cache ready state.

13. The semiconductor device of claim 1 communicates with the controller in accordance with ONFI (Open Nand Flash Interface).

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