Memory device, semiconductor device and method of manufacturing semiconductor device

Abstract

A memory device embodiment includes a front-end-of-line (FEOL) portion that includes a word line driver configured to output a word line signal to a first word line and a second word line, and a memory cell portion over the FEOL portion. The memory cell portion includes memory cells accessible as at least two memory cell arrays, including a first memory cell array that includes a first plurality of memory cells electrically coupled to the first word line, and a second memory cell array that includes a second plurality of memory cells electrically coupled to the second word line.

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