Memory system with interleaved row refresh to address row hammer degradation

Abstract

Aspects disclosed include a memory system with interleaved row refresh to address row hammer degradation. The memory system includes a refresh control circuit and a memory block. The memory block includes a first plurality of memory cell rows and a second plurality of memory cell rows, wherein the first plurality of memory cell rows is spatially interleaved with the second plurality of memory cell rows. In response to receiving a first number of commands to open the first plurality of memory cell rows which exceed a first threshold, the refresh control circuit is configured to refresh the second plurality of memory cell rows. The memory system advantageously addresses the known problem of row hammering while not expending energy refreshing the first plurality of memory cell rows, in contrast to conventional approaches which refresh all the rows.