Memory system, memory device and operating method thereof

Abstract

A memory device includes a first memory string and a second memory string. The first memory string is configured to receive a first string select line signal to compare a first stored data bit and a first input bit. The second memory string is configured to receive a second string select line signal to compare the first stored data bit and the first input bit, wherein the first memory string comprises a first transistor, when the first input bit has a first logic value, the first string select line signal has a first voltage level, when the first input bit has a second logic value, the first string select line signal has a second voltage level, and the first voltage level is within a linear region of the first transistor..

Description

Technical Field

[0001] This disclosure relates to a memory technology, and more particularly to a memory system, a memory device, and a method of operating the memory device. Prior Technology

[0002] With the rise of big data and artificial intelligence (AI) hardware accelerators, data comparison and searching have become indispensable functions in these two fields. Existing ternary content-addressable memory (TCAM) can achieve highly parallel search operations. Traditional TCAMs are usually composed of static random access memory (SRAM), resulting in low memory density and high power consumption. To reduce power consumption and increase memory density, a TCAM array design based on non-volatile memory has recently been proposed. Summary of the Invention

[0003] This disclosure includes a memory device. The memory device includes a first memory string and a second memory string. The first memory string is used to receive a first string select line signal to compare a first stored data bit and a first input bit. The second memory string is used to receive a second string select line signal to compare the first stored data bit and the first input bit. The first memory string includes a first transistor. When the first input bit has a first logic value, the first string select line signal has a first voltage level. When the first input bit has a second logic value, the first string select line signal has a second voltage level. The first voltage level is within a linear region of the first transistor.

[0004] In some embodiments, the second memory string includes a second transistor, and a control terminal of the first transistor and a control terminal of the second transistor are respectively used to receive the first string select line signal and the second string select line signal.

[0005] In some embodiments, each of the control terminals of the first transistor and the second transistor is used to receive a preset positive bias voltage to calibrate each of the first transistor and the second transistor.

[0006] In some embodiments, after calibrating each of the first transistor and the second transistor, each of the first transistor and the second transistor has a calibration critical voltage level.

[0007] In some embodiments, when the first input bit has a first logic value, the second string select line signal has a second voltage level, and when the first input bit has a second logic value, the second string select line signal has a first voltage level.

[0008] In some embodiments, the first memory string and the second memory string further include a third transistor and a fourth transistor, respectively. The third transistor and the fourth transistor are used to store the first stored data bits. The third transistor and the fourth transistor are connected in series with the first transistor and the second transistor, respectively. Each of a control terminal of the third transistor and a control terminal of the fourth transistor is used to receive a word line signal.

[0009] In some embodiments, when the first stored data bit has a first logic value, the third transistor and the fourth transistor have a first critical voltage level and a second critical voltage level, respectively; and when the first stored data bit has a second logic value, the third transistor and the fourth transistor have a second critical voltage level and a first critical voltage level, respectively.

[0010] In some embodiments, the first memory string and the second memory string further include a third transistor and a fourth transistor, respectively. The third transistor and the fourth transistor are connected in series with the first transistor and the second transistor, respectively. A control terminal of the third transistor and a control terminal of the fourth transistor are respectively used to receive the first string selection line signal and the second string selection line signal.

[0011] In some embodiments, each of the control terminals of the first transistor, the second transistor, the third transistor, and the fourth transistor is used to receive a preset positive bias voltage to calibrate each of the first transistor, the second transistor, the third transistor, and the fourth transistor.

[0012] This disclosure includes an embodiment of a memory device operation method, comprising: comparing a first stored data bit and a first input bit using a first memory string and a second memory string; generating a first string current signal using the first memory string; generating a second string current signal using the second memory string; comparing the first string current signal and the second string current signal with a preset current level; and recalibrating the memory device when at least one of the current level of the first string current signal and the current level of the second string current signal is greater than the preset current level.

[0013] In some embodiments, the first memory string and the second memory string respectively include a first transistor and a second transistor. A control terminal of the first transistor and a control terminal of the second transistor are respectively used to receive a first string select line signal and a second string select line signal. When the first input bit has a first logic value, the first string select line signal has a first voltage level. When the first input bit has a second logic value, the first string select line signal has a second voltage level. The first voltage level is within a linear region of the first transistor.

[0014] In some embodiments, when the first input bit has a first logic value, the second string select line signal has a second voltage level, and when the first input bit has a second logic value, the second string select line signal has a first voltage level.

[0015] In some embodiments, the first memory string and the second memory string further include a third transistor and a fourth transistor, the third transistor and the fourth transistor being used to store the first stored data bits, the third transistor and the fourth transistor being connected in series with the first transistor and the second transistor respectively, and each of a control terminal of the third transistor and a control terminal of the fourth transistor being used to receive a word line signal.

[0016] In some embodiments, when the first input bit and the first stored data bit have a first logic value and a second logic value respectively, the first string current signal and the second string current signal have a first current level and a second current level respectively.

[0017] In some embodiments, when the first input bit and the first stored data bit have a second logic value and a first logic value respectively, the first string current signal and the second string current signal have a second current level and a first current level respectively.

[0018] In some embodiments, the preset current level is equal to the first current level multiplied by 1.1.

[0019] In some embodiments, recalibrating the memory device includes applying a preset positive bias voltage to each of the first transistor and the second transistor.

[0020] This disclosure includes a memory system comprising a plurality of memory strings, which are used to generate a plurality of bit line signals. Each memory string includes a first memory string and a second memory string, which are respectively used to receive a first string select line signal and a second string select line signal to compare a first stored data bit and a first input bit. The first memory string includes a first transistor. When the first input bit has a first logic value, the first string select line signal has a first voltage level; when the first input bit has a second logic value, the first string select line signal has a second voltage level. The first voltage level is within a linear region of the first transistor.

[0021] In some embodiments, the memory string further includes: a third memory string and a fourth memory string, respectively used to receive a third string select line signal and a fourth string select line signal to compare the second stored data bits and the second input bits, wherein the first memory string, the second memory string, the third memory string and the fourth memory string are respectively used to generate a first string current signal, a second string current signal, a third string current signal and a fourth string current signal, and to add the first string current signal, the second string current signal, the third string current signal and the fourth string current signal together to generate the first bit line signal in the bit line signal.

[0022] In some embodiments, the memory string further includes: a fifth memory string and a sixth memory string, respectively used to receive a first string select line signal and a second string select line signal to compare a third stored data bit and a first input bit, wherein the fifth memory string and the sixth memory string are respectively used to generate a fifth string current signal and a sixth string current signal, and to add the fifth string current signal and the sixth string current signal together to generate a second bit line signal in the bit line signal. Simple Explanation of the Diagram

[0023] Figure 1A is a schematic diagram of a portion of a memory device according to some embodiments of the present disclosure. Figure 1B is a schematic diagram illustrating input bits received by a memory device having different logic values ​​according to some embodiments of the present disclosure. Figure 1C is a schematic diagram illustrating the distribution of critical voltage levels according to some embodiments of the present disclosure. Figure 1D is a schematic diagram illustrating the voltage of the string select line signal and the current through the corresponding transistor according to some embodiments of the present disclosure. Figure 2A is a schematic diagram illustrating the storage data bits stored in a memory device having different logic values ​​according to some embodiments of the present disclosure. Figure 2B is a schematic diagram illustrating the voltage of a character line signal and the current through the corresponding transistor according to some embodiments of this disclosure. Figures 3A and 3B are schematic diagrams illustrating a memory device performing a search operation according to some embodiments of the present disclosure. Figure 4A is a schematic diagram illustrating a memory device receiving input bits of different logic values ​​according to some embodiments of the present disclosure. Figure 4B is a schematic diagram illustrating a memory device performing a search operation according to some embodiments of the present disclosure. Figure 5A is a schematic diagram illustrating the distribution of critical voltage levels of transistors in a string selection layer according to some embodiments of the present disclosure. Figures 5B and 5C are flowcharts illustrating the operation of a memory device according to some embodiments of the present disclosure. Figure 6A is a schematic diagram of a memory system according to some embodiments of the present invention. Figure 6B is a schematic diagram illustrating further details of a memory system according to some embodiments of the present invention. Figures 6C and 6D are schematic diagrams illustrating further details of a memory device according to some embodiments of the present invention. Implementation

[0024] In this document, when an element is referred to as a "connection" or "coupled," it may mean an "electrical connection" or "electrical coupling." "Connection" or "coupled" can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as "first," "second," etc., are used herein to describe different elements, these terms are only used to distinguish elements or operations described using the same technical terminology. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply order or sequence, nor are they intended to limit the content of this disclosure.

[0025] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant technical context and this disclosure, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms, including "at least one." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms "comprising" and / or "including" specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0027] The following drawings disclose several embodiments of this disclosure. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the disclosure. That is, in some embodiments of this disclosure, these practical details are not necessary. In addition, for the sake of simplicity, some conventional structures and components will be shown in the drawings in a simple schematic manner.

[0028] This disclosure provides a "partially active" string select line signal input method to perform reliable in-memory search (IMS) functionality. By using string select line signal clamping technology, the mismatch current exhibits low variability. The string select line signal in the three-dimensional NAND string has a specific calibration critical voltage level distribution for switching the NAND string. The string select line unit with the calibration critical voltage level distribution can provide a clamping current with low variability for input signals in the sub-critical region (i.e., the partially active region).

[0029] The first to the m-th string select line layers (where m is a positive integer) are programmed to the same calibration critical voltage level, which reduces the local electric field between different string select line layers for robust retention. The string select line layers provide better retention compared to other data layers (e.g., the data layer receiving character line signals). To further enhance IMS reliability, a string select line recalibration procedure is performed to achieve high search accuracy after baking. In this approach, stored data with retention loss does not need to be updated. Only the string select lines need to be recalibrated to maintain the same accuracy as before.

[0030] Figure 1A is a schematic diagram of a portion of a memory device 100 according to some embodiments of the present disclosure. In some embodiments, the memory device 100 may include a plurality of memory strings, such as memory strings MS1 and MS1'. In some embodiments, memory strings MS1 and MS1' may be implemented by NAND strings.

[0031] As shown in Figure 1A, the memory string MS1 includes transistors T1~T192 and TS1. The memory string MS1' includes transistors T1'~T192' and TS1'. However, the embodiments disclosed herein are not limited thereto. In various embodiments, the memory string may contain various numbers of transistors. In other words, 192 may be replaced with other positive integers.

[0032] In some embodiments, transistors T1~T192 and TS1 are connected in series and arranged sequentially. Transistors T1'~T192' and TS1' are connected in series and arranged sequentially. Each control terminal of transistors T1 and T1' is used to receive word line signal WL1. Each control terminal of transistors T2 and T2' is used to receive word line signal WL2, and so on. Each control terminal of transistors T192 and T192' is used to receive word line signal WL192. In summary, transistors T1~T192 and T1'~T192' are used to receive word line signals WL1~WL192.

[0033] On the other hand, the control terminal of transistor TS1 is used to receive the string select line signal SSL. The control terminal of transistor TS1' is used to receive the string select line signal SSL'. Each of transistors TS1 and TS1' has a critical voltage level TVT. Details regarding the critical voltage level TVT are further explained in the following embodiment with respect to Figure 1C.

[0034] In some embodiments, string select lines SSL and SSL' are used to carry input bits IDB1. Transistors T192 and T192' are used to store storage data bits SDB1.

[0035] During the search operation on the stored data bit SDB1, the word line signal WL192 has a read voltage level VREAD, and each of the word line signals WL1 to WL191 has a pass voltage level VPASS. Correspondingly, the memory device 100 can compare the input bit IDB1 and the stored data bit SDB1, causing the memory word strings MS1 and MS1' to generate word string current signals IS1 and IS1', respectively. At this time, the current levels of the word string current signals IS1 and IS1' correspond to the comparison result of the input bit IDB1 and the stored data bit SDB1. Correspondingly, transistors TS1, TS1', T192, and T192' can be collectively referred to as in-flash search (IFS) units.

[0036] Figure 1B is a schematic diagram illustrating the input bit IDB1 received by the memory device 100 having different logic values ​​according to some embodiments of the present disclosure. Please refer to Figures 1A and 1B. For simplicity, some reference numerals of the memory device 100 are not shown in Figure 1B.

[0037] In some embodiments, when the word string select line signal has a voltage level VPTO, the corresponding transistor is turned on, allowing the word string current signal passing through the transistor to have a current level ISLP. When the word string select line signal has a voltage level VL, the corresponding transistor is turned off, allowing the word string current signal passing through the transistor to have a current level ISL0.

[0038] In some embodiments, the current level ISL0 is the zero current level. The voltage level VL is the zero voltage level. The current level ISLP is greater than the current level ISL0. The voltage level VPTO is greater than the voltage level VL. Details regarding the voltage level VPTO and partial conduction are further explained in the following embodiments relating to Figure 1D.

[0039] As shown in Figure 1B, when the input bit IDB1 has a logic value of 1, the string selection signals SSL and SSL' have voltage levels VPTO and VL, respectively. Correspondingly, transistor TS1 is partially turned on, and transistor TS1' is turned off.

[0040] When input bit IDB1 has a logic value of 0, the string selection signals SSL and SSL' have voltage levels VL and VPTO, respectively. Correspondingly, transistor TS1' is partially turned on, and transistor TS1 is turned off.

[0041] When input bit IDB1 has a wildcard logic value, each of the string selection signals SSL and SSL' has a voltage level VL. Correspondingly, each of transistors TS1' and TS1 is turned off. In some embodiments, the wildcard logic value refers to any logic value at input. In other words, the wildcard logic value can simultaneously represent the logic values ​​0 and 1 of input bit IDB1.

[0042] Figure 1C is a schematic diagram illustrating the distribution of the critical voltage level TVT DVT1 according to some embodiments of the present disclosure. The horizontal axis of Figure 1C corresponds to the critical voltage level, and the vertical axis of Figure 1C corresponds to the number of transistors.

[0043] Referring to Figures 1A and 1C, the memory device 100 may include multiple transistors, such as transistors TS1 and TS1', for receiving string select line signals. The critical voltage levels of these transistors are located within a critical voltage level TVT distribution DVT1. As shown in Figure 1C, the critical voltage level TVT distribution DVT1 has a width W1.

[0044] In some embodiments, the width W1 is less than 0.6 volts. In some embodiments, the critical voltage level TVT is equal to 1.5 volts. However, the embodiments disclosed herein are not limited thereto.

[0045] In some embodiments, memory device 100 trims transistors such that these transistors have a critical voltage level (TVT) distribution (DVT1). Specifically, during trimming, memory device 100 may apply a preset positive bias voltage to the control terminals of the transistors to inject charge into the charge traps of the transistors, causing the width of the critical voltage level distribution of the transistors to decrease from approximately 1 volt to a width W1. In some embodiments, the critical voltage level (TVT) may be referred to as the trimmed critical voltage level.

[0046] Figure 1D is a schematic diagram illustrating the voltage of the string select line signal and the current through the corresponding transistor according to some embodiments of the present disclosure. The horizontal axis of Figure 1D corresponds to the voltage level of the string select line signal, and the vertical axis of Figure 1D corresponds to the current level of the string current signal through the transistor receiving the string select line signal.

[0047] Please refer to Figures 1A and 1D. The following description uses the string select line signal SSL and the string current signal IS1 through the transistor TS1 as examples. However, the following configuration is also applicable to other string select line signals and string current signals, such as the string select line signal SSL' and the string current signal IS1' through the transistor TS1'.

[0048] As shown in Figure 1D, the voltage level of the string select line signal SSL can be divided into regions RG1 to RG3. The voltage level of region RG1 is lower than the voltage level of region RG2, and the voltage level of region RG2 is lower than the voltage level of region RG3. In some embodiments, region RG1 is referred to as the cutoff region of transistor TS1, region RG2 is referred to as the linear region of transistor TS1, and region RG3 is referred to as the saturation region of transistor TS1.

[0049] In some embodiments, region RG1 is a region with a voltage level less than 1 volt. Region RG2 is a region with a voltage level between 1 volt and 3 volts. Region RG3 is a region with a voltage level less than 3 volts.

[0050] When the voltage level of the string select line signal SSL is within region RG1, the string current signal IS1 has a current level ISL0, and the transistor TS1 is off. When the voltage level of the string select line signal SSL is within region RG2, the current level of the string current signal IS1 increases with the increase of the voltage level of the string select line signal SSL, and the transistor TS1 is considered to be partially turned on.

[0051] Referring to Figures 1B and 1D, the voltage level VL is located within region RG1, and the voltage level VPTO is located within region RG2. In some embodiments, the voltage level VPTO may be equal to 1.5 volts, and the current level ISLP may be within the current range of 1 to 10 nanoamperes. When the voltage level of the string select line signal SSL is within region RG3, transistor TS1 is considered fully turned on, and the current level of the string current signal IS1 is greater than the current level ISLP, for example, 10 to 200 nanoamperes. In some embodiments, the value of voltage level VPTO may be equal to the value of the critical voltage level TVT.

[0052] Figure 2A is a schematic diagram illustrating the storage data bits SDB1 stored in the memory device 100 having different logic values ​​according to some embodiments of the present disclosure. Please refer to Figures 1A and 2A. For the sake of simplicity, some reference numerals of the memory device 100 are not shown in Figure 2A.

[0053] In some embodiments, the memory device 100 stores a storage data bit using two transistors that receive the same word line signal. For example, transistors T192 and T192' are used to store the storage data bit SDB1.

[0054] When the stored data bit SDB1 has a logic value of 1, transistors T192 and T192' have critical voltage levels HVT and LVT, respectively. At this time, in response to the word line signal WL192, there is a read voltage level VREAD, transistor T192 is turned off and transistor T192' is turned on. The read voltage level VREAD is less than the critical voltage level HVT and greater than the critical voltage level LVT.

[0055] When the stored data bit SDB1 has a logic value of 0, transistors T192 and T192' have critical voltage levels LVT and HVT, respectively. At this time, in response to the word line signal WL192 having a read voltage level VREAD, transistor T192' is turned off and transistor T192 is turned on.

[0056] When the stored data bit SDB1 has a negligible logic value X, each of transistors T192 and T192' has a critical voltage level HVT. At this time, in response to the word line signal WL192 having a read voltage level VREAD, each of transistors T192' and T192 is turned off. In some embodiments, the negligible logic value X refers to any logic value at input. In other words, the negligible logic value X can simultaneously represent the logic values ​​0 and 1 of the stored data bit SDB1.

[0057] Figure 2B is a schematic diagram illustrating the voltage of the character line signal and the current through the corresponding transistor according to some embodiments of this disclosure. The horizontal axis in Figure 2B corresponds to the voltage level of the character line signal, and the vertical axis in Figure 2B corresponds to the current level of the character string current signal through the transistor receiving the character line signal.

[0058] As shown in Figure 2B, the transistor with a critical voltage level (LVT) corresponds to curve group CVG1, and the transistor with a critical voltage level (HVT) corresponds to curve group CVG2. When the transistor has a critical voltage level (HVT), the corresponding word line signal has a read voltage level (VREAD), and the word string current signal passing through the transistor has a current level (ISL0). When the transistor has a critical voltage level (LVT), the corresponding word line signal has a read voltage level (VREAD), and the current level distribution of the word string current signal passing through the transistor has a large distribution range. In other words, the transistor's on-current has a large variability.

[0059] For example, referring to Figures 2A and 2B, when both transistors TS1 and TS1' are turned on, when the stored data bit SDB1 has a logic value of 1, the string current signals IS1 and IS1' have current levels ISL0 and IVL2, respectively. When the stored data bit SDB1 has a logic value of 0, the string current signals IS1 and IS1' have current levels IVL1 and ISL0, respectively. When the stored data bit SDB1 has a negligible logic value X, each of the string current signals IS1 and IS1' has a current level ISL0. The current level IVL1 is greater than the current level ISL0 and less than the current level IVL2.

[0060] To reduce the variability of the conduction current, memory device 100 partially turns on each of transistors TS1 and TS1' to clamp the string current signals IS1 and IS1'. In this way, when the transistors are on, the current levels of the string current signals IS1 and IS1' can be unified to a current level ISLP, where the variability of the current level ISLP is low. Details regarding the clamping of the string current signals IS1 and IS1' are further explained in the embodiments shown in Figures 3A and 3B below.

[0061] Figure 3A is a schematic diagram illustrating a search operation of a memory device 100 according to some embodiments of the present disclosure. As shown in Figure 3A, the memory device 100 may also include a sensing amplifier 301. The sensing amplifier 301 is used to receive string current signals generated by the memory string, such as string current signals IS1 and IS1'.

[0062] In the embodiment shown in Figure 3A, the character line signal WL192 has a read voltage level VREAD, and each of the character line signals WL1 to WL191 has a pass voltage level VPASS.

[0063] When input bit IDB1 has a logic value of 1 and stored data bit SDB1 has a logic value of 1, the string select line signal SSL' has a voltage level VL and transistor T192 has a critical voltage level HVT, causing each of transistors TS1' and T192 to be turned off. Correspondingly, each of the string current signals IS1 and IS1' has a current level ISL0.

[0064] When input bit IDB1 has a logic value of 0 and stored data bit SDB1 has a logic value of 1, transistor T192 is turned off at the critical voltage level HVT, causing the word string current signal IS1 to have a current level ISL0. Transistor T192' is turned on at the critical voltage level LVT. The word string select line signal SSL' has a voltage level VPTO, causing transistor TS1' to be partially turned on. At this time, transistor TS1' clamps the word string current signal IS1', causing the word string current signal IS1' to have a current level ISLP.

[0065] Figure 3B is a schematic diagram illustrating a search operation of a memory device 100 according to some embodiments of the present disclosure. In the embodiment shown in Figure 3B, the character line signal WL192 has a read voltage level VREAD, and each of the character line signals WL1 to WL191 has a pass voltage level VPASS.

[0066] When the input bit IDB1 has a logic value of 1 and the stored data bit SDB1 has a logic value of 0, transistor T192' is turned off at the critical voltage level HVT, causing the word string current signal IS1' to have a current level ISL0. Transistor T192 is turned on at the critical voltage level LVT. The word string select line signal SSL has a voltage level VPTO, causing transistor TS1 to partially turn on. At this time, transistor TS1 clamps the word string current signal IS1, causing the word string current signal IS1 to have a current level ISLP.

[0067] When input bit IDB1 has a logic value of 0 and stored data bit SDB1 has a logic value of 0, the string select line signal SSL has a voltage level VL and transistor T192' has a critical voltage level HVT, causing each of transistors TS1 and T192' to be turned off. Correspondingly, each of the string current signals IS1 and IS1' has a current level ISL0.

[0068] In summary, when the logic values ​​of input bit IDB1 and stored data bit SDB1 are the same, input bit IDB1 and stored data bit SDB1 are matched. Correspondingly, the sense amplifier 301 senses the current level ISL0, i.e., the zero current level, from the memory strings MS1 and MS1'.

[0069] Conversely, when the logic values ​​of input bit IDB1 and stored data bit SDB1 are different, input bit IDB1 and stored data bit SDB1 are mismatched. Correspondingly, the sense amplifier 301 senses the current level ISLP, i.e., the low-variability current level, from the memory strings MS1 and MS1'.

[0070] In some embodiments, the memory device 100 may also compare the input bit IDB1 with the stored data bits stored in transistors T1~T191 and T1'~T191'.

[0071] Specifically, when comparing the input bit IDB1 and the stored data bits stored in transistors T191 and T191', word line signal WL191 has a read voltage level VREAD, and each of word line signals WL1~WL190 and WL192 has a pass voltage level VPASS. When comparing the input bit IDB1 and the stored data bits stored in transistors T190 and T190', word line signal WL190 has a read voltage level VREAD, and each of word line signals WL1~WL189 and WL191~WL192 has a pass voltage level VPASS, and so on. When comparing the input bit IDB1 and the stored data bits stored in transistors T1 and T1', word line signal WL1 has a read voltage level VREAD, and each of word line signals WL2~WL192 has a pass voltage level VPASS.

[0072] In some implementations, the string current signal generated by the memory string during a search operation has a large variability, which makes the sensing amplifier's sensing results inaccurate.

[0073] Compared to the above approach, in this embodiment, the memory device 100 adjusts the string select line signals SSL and SSL' to the voltage level VPTO in the linear region, causing transistors TS1 and TS1' to be partially turned on, thereby clamping the string current signals IS1 and IS' to the current level ISLP, which has lower variability. As a result, the sensing result of the sensing amplifier 301 has higher accuracy.

[0074] Figure 4A is a schematic diagram illustrating the memory device 400 receiving input bits of different logic values ​​according to some embodiments of the present disclosure. Referring to Figures 4A and 1A, the memory device 400 is a variation of the memory device 100. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0075] Compared to memory device 100, memory device 400 further includes transistors TS2, TS3, TS2', and TS3'. Transistors TS1 to TS3 are connected in series and arranged sequentially. Transistors TS1' to TS3' are connected in series and arranged sequentially. Transistor TS1 is coupled between transistors TS2 and T192. Transistor TS1' is coupled between transistors TS2' and T192'.

[0076] In some embodiments, each of the control terminals of transistors TS1 to TS3 is used to receive the string select line signal SSL. Each of the control terminals of transistors TS1' to TS3' is used to receive the string select line signal SSL'. In other words, the three string select line layers corresponding to transistors TS1 to TS3 and TS1' to TS3' receive the same string select line signal and operate simultaneously.

[0077] In some embodiments, each of transistors TS1~TS3 and TS1'~TS3' has a critical voltage level TVT. During a search operation, transistors TS1~TS3, TS1'~TS3', T192, and T192' can be considered as an IFS unit.

[0078] When the input bit SDB1 has a logic value of 1, the string select line signals SSL and SSL' have voltage levels VPTO and VL respectively, causing each of the transistors TS1 to TS3 to be partially turned on and each of the transistors TS1' to TS3' to be turned off.

[0079] When the input bit SDB1 has a logic value of 0, the string select line signals SSL and SSL' have voltage levels VL and VPTO respectively, causing each of the transistors TS1' to TS3' to be partially turned on and each of the transistors TS1 to TS3 to be turned off.

[0080] In the embodiment shown in Figure 4A, the memory device 400 includes three string select line layers, namely transistors TS1~TS3 and TS1'~TS3'. However, the embodiments disclosed herein are not limited thereto. In various embodiments, the memory device 400 may include various numbers of string select line layers, such as three to five layers.

[0081] In some embodiments, multiple string select line layers are programmed to the same threshold voltage level (TVT) to reduce the local electric field between different string select line layers, thereby improving the robustness of the memory device 400. The string select line layers provide better robustness compared to data layers (e.g., transistors T1-T192 and T1'-T192'). In some embodiments, the string select line layers are used for query input, and the data layers are used for storing a database. The memory array of the memory device 400 may have one or more data layers.

[0082] In some implementations, when a memory device performs a search operation, the critical voltage level in the data layer affects the local electric field of the string select line layer, thus reducing robustness.

[0083] Compared to the above approach, in the embodiments disclosed herein, the memory device 400 reduces the influence of local electric fields by using multiple string selection line layers, thereby improving robustness.

[0084] Figure 4B is a schematic diagram illustrating a search operation of a memory device 400 according to some embodiments of the present disclosure. In the embodiment shown in Figure 4B, the character line signal WL192 has a read voltage level VREAD, and each of the character line signals WL1 to WL191 has a pass voltage level VPASS.

[0085] When input bit IDB1 has a logic value of 1 and stored data bit SDB1 has a logic value of 1, the string select line signal SSL' has a voltage level VL and transistor T192 has a critical voltage level HVT, causing each of transistors TS1'~TDS3' and T192 to be turned off. Correspondingly, each of the string current signals IS1 and IS1' has a current level ISL0.

[0086] When input bit IDB1 has a logic value of 0 and stored data bit SDB1 has a logic value of 1, transistor T192 is turned off at the critical voltage level HVT, causing the string current signal IS1 to have a current level ISL0. Transistor T192' is turned on at the critical voltage level LVT. The string select line signal SSL' has a voltage level VPTO, causing each of transistors TS1' to TS3' to be partially turned on. At this time, each of transistors TS1' to TS3' clamps the string current signal IS1', causing the string current signal IS1' to have a current level ISLP.

[0087] Figure 5A is a schematic diagram 500A illustrating the distribution of critical voltage levels of transistors in a string selection layer according to some embodiments of this disclosure. The horizontal axis of schematic diagram 500A corresponds to voltage, and the vertical axis of schematic diagram 500A corresponds to the number of transistors.

[0088] As shown in Figure 5A, schematic diagram 500A includes distributed DVT1 and DVT2. The voltage difference between distributed DVT1 and voltage level VPTO is greater than the voltage difference between distributed DVT2 and voltage level VPTO. Distributed DVT1 and DVT2 can correspond to the distribution of the critical voltage levels of the transistors in the string selection layer. Referring to Figures 1A, 4A, and 5A, transistors TS1~TS3 and TS1'~TS3' are embodiments of transistors in the string selection layer.

[0089] In some embodiments, when the transistor calibration in the string selection line layer is completed, the transistors in the string selection line layer are distributed as DVT1. After a period of use and / or use in a high-temperature environment, the transistors in the string selection line layer experience retention loss, resulting in the transistors in the string selection line layer being distributed as DVT2.

[0090] For example, upon completion of calibration, each of transistors TS1~TS3 and TS1'~TS3' has a critical voltage level TVT and a corresponding distribution DVT1. After a period of use and / or use in high-temperature environments, due to retention loss, the critical voltage levels of transistors TS1~TS3 and TS1'~TS3' decrease, resulting in a corresponding distribution DVT2 for transistors TS1~TS3 and TS1'~TS3'.

[0091] When DVT1 is distributed with transistors TS1~TS3 and TS1'~TS3', transistors TS1~TS3 and TS1'~TS3' can clamp the word string current signals IS1 and IS1' to the current level ISLP. When DVT2 is distributed with transistors TS1~TS3 and TS1'~TS3', transistors TS1~TS3 and TS1'~TS3' can clamp the word string current signals IS1 and IS1' to the current level ISLP'. The current level ISLP' is greater than the current level ISLP.

[0092] Correspondingly, the memory device 400 can determine whether to recalibrate transistors TS1~TS3 and TS1'~TS3' based on the word string current signals IS1 and IS1'. During recalibration, the memory device 400 can apply a preset positive bias voltage to the control terminals of transistors TS1~TS3 and TS1'~TS3' to inject charge into the charge traps of transistors TS1~TS3 and TS1'~TS3', causing the distribution of transistors TS1~TS3 and TS1'~TS3' to return from distribution DVT2 to distribution DVT1.

[0093] After recalibration, transistors TS1~TS3 and TS1'~TS3' can clamp the string current signals IS1 and IS1' to the current level ISLP. Details regarding recalibration are further described in the following embodiment relating to Figure 5B.

[0094] Figure 5B is a flowchart illustrating an operation method 500B of a memory device according to some embodiments of the present disclosure. As shown in Figure 5B, the operation method 500B includes operations OP51 to OP54. Referring to Figures 1A to 5B, the operation method 500B can be executed by memory device 100 or memory device 400. The following description uses the execution of operation method 500B by memory device 400 as an example.

[0095] During operation OP51, memory device 400 checks whether the critical voltage level of the word string select line layer meets the recalibration criteria. Specifically, memory device 400 senses the word string current signals IS1 and IS1' using sense amplifier 301 and compares the current levels of word string current signals IS1 and IS1' with the current level ISLP. When the difference between the current levels of word string current signals IS1 and IS1' and the current level ISLP is too large, memory device 400 needs to be recalibrated.

[0096] For example, when at least one of the current levels of the string current signals IS1 and IS1' is greater than a preset current level, the memory device 400 determines that the critical voltage levels of transistors TS1~TS3 and TS1'~TS3' meet the recalibration criteria and executes operation OP52. When each of the current levels of the string current signals IS1 and IS1' is less than a preset current level, the memory device 400 determines that the critical voltage levels of transistors TS1~TS3 and TS1'~TS3' do not meet the recalibration criteria and executes operation OP53.

[0097] In some embodiments, the preset current level is equal to 1.1 times the current level ISLP. However, the embodiments disclosed herein are not limited thereto. In various embodiments, the memory device 400 may have various recalibration standards. In other words, 1.1 times may be replaced with other multipliers.

[0098] During operation OP52, the memory device 400 recalibrates the critical voltage level of the word string selection line layer. Specifically, the memory device 400 applies a preset positive bias voltage to the control terminals of transistors TS1~TS3 and TS1'~TS3' to inject charge into the charge traps of transistors TS1~TS3 and TS1'~TS3', causing the distribution of transistors TS1~TS3 and TS1'~TS3' to return from distribution DVT2 to distribution DVT1.

[0099] During operation OP53, memory device 400 performs a memory search operation, such as the operation shown in Figure 4B. After operation OP53, memory device 400 executes operation OP54.

[0100] During operation OP54, memory device 400 outputs Top-K data. For example, memory device 400 outputs the K data instances with the highest similarity, where K is a positive integer.

[0101] In summary, because the string select line layer can clamp the string current signal, the memory device does not need to reprogram the data layer after retention loss. This saves time and cost associated with reprogramming.

[0102] Figure 5C is a flowchart illustrating an operation method 500C of a memory device according to some embodiments of the present disclosure. As shown in Figure 5C, the operation method 500C can be executed by operating the memory device 100 or the memory device 400 via a controller 501. In some embodiments, the controller 501 may be included in the memory device 100 or the memory device 400. The following description uses the execution of the operation method 500C via the memory device 400 as an example.

[0103] As shown in Figure 5C, operation method 500C includes a programming phase and a query phase. In some embodiments, the query phase is executed after the programming phase. The programming phase includes operations PP51 and PP52. The query phase includes operations OP51~OP54, QP51, and QP52.

[0104] During operation PP51, controller 501 controls memory device 400 to initialize. Specifically, memory device 400 calibrates transistors TS1~TS3 and TS1'~TS3' in the string selection layer and checks the critical voltage level TVT of transistors TS1~TS3 and TS1'~TS3'. In some embodiments, during operation PP51, controller 501 may store the critical voltage level TVT for subsequent comparisons.

[0105] Referring to Figures 5C and 5B, in some embodiments, the voltage level of the preset positive bias applied to transistors TS1~TS3 and TS1'~TS3' in operation PP51 is equal to the voltage level of the preset positive bias applied to transistors TS1~TS3 and TS1'~TS3' in operation OP52. In other words, the waveforms of the preset positive bias in the calibration operation and the recalibration operation are the same.

[0106] During operation PP52, controller 501 controls memory device 400 to program the data layer. Specifically, memory device 400 writes stored data bits to transistors T1~T192 and T1'~T192' of the corresponding word line signals WL1~WL192. After operation PP52, memory device 400 can perform the query phase.

[0107] During the query phase, controller 501 controls memory device 400 to execute operations OP51 to OP54. Please refer to Figures 5C and 5B; the details of operations OP51 to OP54 are explained above in the embodiment shown in Figure 5B. Therefore, for the sake of brevity, the description of operations OP51 to OP54 will not be repeated.

[0108] As shown in Figure 5C, between operations OP53 and OP54, memory device 400 can also perform operations QP51 and QP52.

[0109] When operating QP51, memory device 400 receives query data carried by the string select line signals. Referring to Figures 4B and 5C, the query data may include the input bits IDB1 carried by the string select line signals SSL and SSL'.

[0110] When operating QP52, memory device 400 compares and queries data with the stored data of corresponding character line signals WL1~WL192. Please refer to Figures 4B and 5C. The stored data may include the stored data bit SDB1.

[0111] When operating OP54, memory device 400 outputs the K data instances with the highest similarity (i.e., Top-K data instances).

[0112] Figure 6A is a schematic diagram of a memory system 600 according to some embodiments of the present invention. As shown in Figure 6A, the memory system 600 includes a memory device 610, a sensing device 620, a temporary storage device 630, and an output device 640.

[0113] In some embodiments, memory device 610 is used to generate bit line signals BL1~BL128K, where K equals one thousand. However, this disclosure is not limited thereto. In various embodiments, memory device 610 can generate various numbers of bit line signals. In other words, 128K can be replaced with other positive integers. Sensing device 620 may include a page buffer and a sensing amplifier, and is used to sense the search results corresponding to the bit line signals BL1~BL128K. Temporary storage device 630 may include a cache and a priority encoder. Output device 640 is used to output the pairing results of memory device 610.

[0114] In some embodiments, the processing of bit line signals by the temporary storage device 630 includes AND logic, OR logic, and counting logic processing, and may also include a combination of the above three logics. Referring to Figures 1 to 6A, the temporary storage device 630 can receive sensing results from memory devices 100, 400, and / or 610, and control the sorting (which may be serial or parallel) and combine the sensing results to generate an overall search result as the pairing result output by the output device 640.

[0115] In some embodiments, the temporary storage device 630 is further used to perform priority encoding on the search results corresponding to the bit line signals BL1 to BL128K. For example, the temporary storage device 630 integrates the search results corresponding to the bit line signals BL1 to BL128K and preferentially selects the address of the bit line signal corresponding to the best search result (that is, the value of the query data and the value of the stored data are closest to each other).

[0116] Figure 6B is a schematic diagram illustrating further details of a memory system 600 according to some embodiments of the present invention. In some embodiments, the memory device 610 may be implemented by a three-dimensional (3D) memory architecture. As shown in Figure 6B, the memory device 610 includes memory strings MS1_1~MS1_128K, MS1_1'~MS1_128K', MS2_1~MS2_128K, MS2_1'~MS2_128K', ..., MS256_1~MS256_128K and MS256_1'~MS256_128K'.

[0117] In some embodiments, memory strings MS1_1~MS256_1 and MS1_1'~MS256_1' are used to generate string current signals IS1_1~IS256_1 and IS1_1'~IS256_1', respectively, and are then summed to generate bit line signal BL1. In other words, the current level of bit line signal BL1 is equal to the sum of the current levels of string current signals IS1_1~IS256_1 and IS1_1'~IS256_1'.

[0118] Similarly, the memory strings MS1_128K~MS256_128K and MS1_128K'~MS256_128K' are used to generate string current signals IS1_128K~IS256_128K and IS1_128K'~IS256_128K', respectively, and are then summed to generate the bit line signal BL128K. In other words, the current level of the bit line signal BL128K is equal to the sum of the current levels of the string current signals IS1_128K~IS256_128K and IS1_128K'~IS256_128K'.

[0119] Please refer to Figures 4A, 4B, and 6B. The configuration of memory strings MS1_1~MS1_128K, MS1_1'~MS1_128K', MS2_1~MS2_128K, MS2_1'~MS2_128K', ..., MS256_1~MS256_128K and MS256_1'~MS256_128K' is similar to that of memory strings MS1 and MS1'. The configuration of string current signals IS1_1~IS256_1, IS1_1'~IS256_1', IS1_128K~IS256_128K and IS1_128K'~IS256_128K' is similar to that of string current signals IS1 and IS1'. Therefore, for the sake of brevity, some descriptions will not be repeated.

[0120] For example, memory strings MS1_1 and MS1_1' can be implemented using memory strings MS1 and MS1' respectively. String current signals IS1 and IS1' correspond to string current signals IS1_1 and IS1_1' respectively.

[0121] Figure 6C is a schematic diagram illustrating further details of the memory device 610 according to some embodiments of the present invention. As shown in Figure 6C, the memory string MS1_1 includes transistors T1_1_0 to T1_1_95 and TS1_1_1 to TS1_1_3. The memory string MS1_1' includes transistors T1_1_0' to T1_1_95' and TS1_1_1' to TS1_1_3'. The memory string MS256_1 includes transistors T256_1_0 to T256_1_95 and TS256_1_1 to TS256_1_3. The memory string MS256_1' includes transistors T256_1_0' to T256_1_95' and TS256_1_1' to TS256_1_3'.

[0122] Transistors T1_1_0 to T1_1_95 and TS1_1_1 to TS1_1_3 are connected in series and arranged sequentially. Transistors T1_1_0' to T1_1_95' and TS1_1_1' to TS1_1_3' are connected in series and arranged sequentially. Transistors T256_1_0 to T256_1_95 and TS256_1_1 to TS256_1_3 are connected in series and arranged sequentially. Transistors T256_1_0' to T256_1_95' and TS256_1_1' to TS256_1_3' are connected in series and arranged sequentially.

[0123] In some embodiments, each of the control terminals of transistors TS1_1_1 to TS1_1_3 is used to receive the string select line signal SSL1. Each of the control terminals of transistors TS1_1_1' to TS1_1_3' is used to receive the string select line signal SSL1'. Each of the control terminals of transistors TS2_1_1 to TS2_1_3 is used to receive the string select line signal SSL2. Each of the control terminals of transistors TS2_1_1' to TS2_1_3' is used to receive the string select line signal SSL2', and so on. Each of the control terminals of transistors TS256_1_1 to TS256_1_3 is used to receive the string select line signal SSL256. Each of the control terminals of transistors TS256_1_1' to TS256_1_3' is used to receive the string select line signal SSL256'.

[0124] In some embodiments, prior to performing a search operation, the memory system 600 calibrates each of the transistors TS1_1_1~TS1_1_3, TS1_1_1'~TS1_1_3', TS256_1_1~TS256_1_3, and TS256_1_1'~TS256_1_3' such that each of the transistors TS1_1_1~TS1_1_3, TS1_1_1'~TS1_1_3', TS256_1_1~TS256_1_3, and TS256_1_1'~TS256_1_3' has a critical voltage level TVT.

[0125] On the other hand, each of transistors T1_1_0 to T256_1_0 and T1_1_0' to T256_1_0' is used to receive word line signal WL0. Each of transistors T1_1_1 to T256_1_1 and T1_1_1' to T256_1_1' is used to receive word line signal WL1, and so on. Each of transistors T1_1_95 to T256_1_95 and T1_1_95' to T256_1_95' is used to receive word line signal WL95. In summary, the memory strings MS1_1 to MS256_1 and MS1_1' to MS256_1' are used to receive word line signals WL1 to WL95.

[0126] In some embodiments, string select lines SSL1~SSL256 and SSL1'~SSL256' are used to carry query data QDT. Specifically, the query data QDT includes input bits IDB1~IDB256. String select lines SSL1 and SSL1' are used to carry input bits IDB1. String select lines SSL2 and SSL2' are used to carry input bits IDB2, and so on. String select lines SSL256 and SSL256' are used to carry input bits IDB256.

[0127] On the other hand, transistors T1_1_95 to T256_1_95 and T1_1_95' to T256_1_95' are used to store the stored data SDT1. Specifically, the stored data SDT1 includes stored data bits SDB1_1 to SDB1_256. Transistors T1_1_95 and T1_1_95' are used to store stored data bits SDB1_1. Transistors T2_1_95 and T2_1_95' are used to store stored data bits SDB1_2, and so on. Transistors T256_1_95 and T256_1_95' are used to store stored data bits SDB1_256.

[0128] Please refer to Figures 4B and 6C. The configuration of the transistors and string select line signals shown in Figure 6C is similar to that shown in Figure 4B. Therefore, for the sake of brevity, some descriptions will not be repeated. For example, transistors T1_1_95, T1_1_95', TS1_1_1~TS1_1_3, and TS1_1_1'~TS1_1_3' correspond to transistors T192, T192', TS1~TS3, and TS1'~TS3', respectively. String select line signals SSL1 and SSL1' correspond to string select line signals SSL and SSL', respectively.

[0129] In the embodiment shown in Figure 6C, the character line signal WL95 has a read voltage level VREAD, and each of the character line signals WL0 to WL94 has a pass voltage level VPASS. Correspondingly, the memory device 610 can compare the query data QDT and the stored data SDT1.

[0130] At this time, input bit IDB1 has a logic value of 1, causing the string select line signals SSL1 and SSL1' to have voltage levels VPTO and VL, respectively. Correspondingly, each of transistors TS1_1_1' to TS1_1_3' is turned off, causing the string current signal IS1_1' to have a current level ISL0.

[0131] The data storage bit SDB1_1 has a logic value of 1, which enables transistors T1_1_95 and T1_1_95' to have critical voltage levels HVT and LVT, respectively. Correspondingly, when transistor T1_1_95 is turned off, the word string current signal IS1_1 has a current level ISL0.

[0132] The input bit IDB256 has a logic value of 1, causing the string select line signals SSL256 and SSL256' to have voltage levels VPTO and VL, respectively. Correspondingly, each of transistors TS256_1_1 to TS256_1_3 is partially turned on, and each of transistors TS256_1_1' to TS256_1_3' is turned off, causing the string current signal IS256_1' to have a current level ISL0.

[0133] The data storage bit SDB1_256 has a logic value of 0, causing transistors T256_1_95 and T256_1_95' to have critical voltage levels LVT and HVT, respectively. Correspondingly, transistor T256_1_95 is turned on. At this time, in response, a portion of each of transistors TS256_1_1 to TS256_1_3 is turned on, and the word string current signal IS256_1 has a current level ISLP.

[0134] In the embodiment shown in Figure 6C, input bits IDB2~IDB255 are respectively matched with stored data bits SDB1_2~SDB1_255, such that each of the string current signals IS2_1~IS255_1 and IS2_1'~IS255_1' has a current level ISL0. Correspondingly, the current level of the bit line signal BL1 is equal to the current level ISLP.

[0135] Figure 6D is a schematic diagram illustrating further details of the memory device 610 according to some embodiments of the present invention. As shown in Figure 6D, the memory string MS1_128K includes transistors T1_128K_0 to T1_128K_95 and TS1_128K_1 to TS1_128K_3. The memory string MS1_128K' includes transistors T1_128K_0' to T1_128K_95' and TS1_128K_1' to TS1_128K_3'. The memory string MS256_128K includes transistors T256_128K_0 to T256_128K_95 and TS256_128K_1 to TS256_128K_3. The memory string MS256_128K' contains transistors T256_128K_0'~ T256_128K_95' and TS256_128K_1'~ TS256_128K_3'.

[0136] Transistors T1_128K_0~T1_128K_95 and TS1_128K_1~TS1_128K_3 are connected in series and arranged sequentially. Transistors T1_128K_0'~T1_128K_95' and TS1_128K_1'~TS1_128K_3' are connected in series and arranged sequentially. Transistors T256_128K_0~T256_128K_95 and TS256_128K_1~TS256_128K_3 are connected in series and arranged sequentially. Transistors T256_128K_0'~T256_128K_95' and TS256_128K_1'~TS256_128K_3' are connected in series and arranged sequentially.

[0137] In some embodiments, each of the control terminals of transistors TS1_128K_1 to TS1_128K_3 is used to receive the string select line signal SSL1. Each of the control terminals of transistors TS1_128K_1' to TS1_128K_3' is used to receive the string select line signal SSL1'. Each of the control terminals of transistors TS2_128K_1 to TS2_128K_3 is used to receive the string select line signal SSL2. Each of the control terminals of transistors TS2_128K_1' to TS2_128K_3' is used to receive the string select line signal SSL22'. Each of the control terminals of transistors TS256_128K_1 to TS256_128K_3 is used to receive the string select line signal SSL256. Each of the control terminals of transistors TS256_128K_1' to TS256_128K_3' is used to receive the string select line signal SSL256'.

[0138] In some embodiments, prior to performing a search operation, the memory system 600 calibrates each of the transistors TS1_128K_1~TS1_128K_3, TS1_128K_1'~TS1_128K_3', TS256_128K_1~TS256_128K_3, and TS256_128K_1'~TS256_128K_3' such that each of the memory system 600 calibrates each of the transistors TS1_128K_1~TS1_128K_3, TS1_128K_1'~TS1_128K_3', TS256_128K_1~TS256_128K_3, and TS256_128K_1'~TS256_128K_3' has a critical voltage level TVT.

[0139] On the other hand, each of transistors T1_128K_0 to T256_128K_0 and T1_128K_0' to T256_128K_0' is used to receive the character line signal WL0. Each of transistors T1_128K_1 to T256_128K_1 and T1_128K_1' to T256_128K_1' is used to receive the character line signal WL1, and so on. Each of transistors T1_128K_95 to T256_128K_95 and T1_128K_95' to T256_128K_95' is used to receive the character line signal WL95. In summary, the memory strings MS1_128K~MS256_128K and MS1_128K'~MS256_128K' are used to receive character line signals WL1~WL95.

[0140] In some embodiments, transistors T1_128K_95 to T256_128K_95 and T1_128K_95' to T256_128K_95' are used to store stored data SDT128K. Specifically, the stored data SDT128K includes stored data bits SDB128K_1 to SDB128K_256. Transistors T1_128K_95 and T1_128K_95' are used to store stored data bits SDB128K_1. Transistors T2_1_95 and T2_1_95' are used to store stored data bits SDB128K_2, and so on. Transistors T256_128K_95 and T256_128K_95' are used to store stored data bits SDB128K_256.

[0141] In the embodiment shown in Figure 6D, the character line signal WL95 has a read voltage level VREAD, and each of the character line signals WL0 to WL94 has a pass voltage level VPASS. Correspondingly, the memory device 610 can compare the query data QDT and the stored data SDT128K.

[0142] At this time, input bit IDB1 has a logic value of 1, causing the string select line signals SSL1 and SSL1' to have voltage levels VPTO and VL, respectively. Correspondingly, each of transistors TS1_128K_1' to TS1_128K_3' is turned off, causing the string current signal IS1_128K' to have a current level ISL0.

[0143] The data storage bit SDB128K_1 has a logic value of 1, which enables transistors T1_128K_95 and T1_128K_95' to have critical voltage levels HVT and LVT, respectively. Correspondingly, when transistor T1_128K_95 is turned off, the word string current signal IS1_128K has a current level ISL0.

[0144] The input bit IDB256 has a logic value of 1, causing the string select line signals SSL256 and SSL256' to have voltage levels VPTO and VL, respectively. Correspondingly, each of the transistors TS256_128K_1' to TS256_128K_3' is turned off, causing the string current signal IS256_128K' to have a current level ISL0.

[0145] The data storage bit SDB128K_256 has a logic value of 1, causing transistors T256_128K_95 and T256_128K_95' to have critical voltage levels HVT and LVT, respectively. Correspondingly, when transistor T256_128K_95 is turned off, the word string current signal IS256_128K has a current level ISL0.

[0146] In the embodiment shown in Figure 6D, input bits IDB2~IDB255 are matched with stored data bits SDB128K_2~SDB128K_255, such that each of the string current signals IS2_128K~IS255_128K and IS2_128K'~IS255_128K' has a current level ISL0. Correspondingly, the current level of the bit line signal BL128K is equal to the current level ISL0.

[0147] Please refer to Figures 6D and 6C. Since the current level ISL0 of the bit line signal BL128K is less than the current level ISLP of the bit line signal BL1, the memory system 600 can determine that the similarity between the query data QDT and the stored data SDT128K is greater than the similarity between the query data QDT and the stored data SDT1.

[0148] In some embodiments, the memory cell in this disclosure is referred to as an in-memory searching (IMS) cell. In various embodiments, the IMS cell may be implemented using floating gate memory, split-gate memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, floating dot memory, dynamic random-access memory (DRAM), and / or ferroelectric field-effect transistor (FeFET).

[0149] In various embodiments, the memory device in this disclosure may be implemented by various structures, such as a two-dimensional (2D) cache structure or a three-dimensional (3D) cache structure.

[0150] Although the present disclosure has been presented above with reference to embodiments, it is not intended to limit the scope of the present disclosure. Anyone skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0151] 100, 400: Memory devices MS1, MS1': memory string T1~T192, TS1, T1'~T192', TS1': Transistors WL1~WL192: Character line signals SSL, SSL': String select line signal TVT, HVT, LVT: Critical Voltage Level IS1, IS1': String current signal VREAD: Read voltage level VPASS: Through voltage level VL, VPTO: Voltage Level ISLP, ISL0, IVL1, IVL2: Current Levels DVT1, DVT2: Distribution W1: Width RG1~RG3: Area X: Ignore logical value CVG1, CVG2: Curve Group 301: Sensing Amplifier 500A: Schematic Diagram 500B, 500C: Operating Instructions OP51~OP54, PP51, PP52, QP51, QP52: Operation 501: Controller 600: Memory System 610: Memory device 620: Sensing device 630: Temporary storage device 640: Output device BL1~BL128K: Bit line signals MS1_1~MS256_128K, MS1_1'~MS256_128K': memory string IS1_1~IS256_128K, IS1_1'~IS256_128K': String current signal T1_1_0~T256_128K_95, T1_1_0'~T256_128K_95', TS1_1_1~TS256_128K_3, TS1_1_1'~TS256_128K_3': Transistors SSL1~SSL256, SSL1'~SSL256': String select line signals

Claims

1. A memory device comprising: a first memory string for receiving a first string select line signal to compare a first stored data bit and a first input bit; and a second memory string for receiving a second string select line signal to compare the first stored data bit and the first input bit, wherein the first memory string includes a first transistor, the first string select line signal has a first voltage level when the first input bit has a first logic value, and the first string select line signal has a second voltage level when the first input bit has a second logic value, the first voltage level being within a linear region of the first transistor, control terminals of a plurality of transistors in the first memory string being correspondingly coupled to control terminals of a plurality of transistors in the second memory string, and the second memory string including a second transistor. A control terminal of the first transistor and a control terminal of the second transistor are respectively used to receive the first string select line signal and the second string select line signal, and each of the control terminals of the first transistor and the second transistor is used to receive a preset positive bias voltage to calibrate each of the first transistor and the second transistor.

2. The memory device as claimed in claim 1, wherein after calibrating each of the first transistor and the second transistor, each of the first transistor and the second transistor has a calibration threshold voltage level.

3. The memory device as claimed in claim 1, wherein when the first input bit has the first logic value, the second string select line signal has the second voltage level, and when the first input bit has the second logic value, the second string select line signal has the first voltage level.

4. The memory device as claimed in claim 3, wherein the first memory string and the second memory string further include a third transistor and a fourth transistor, the third transistor and the fourth transistor for storing the first stored data bits, the third transistor and the fourth transistor being connected in series with the first transistor and the second transistor respectively, and each of a control terminal of the third transistor and a control terminal of the fourth transistor being used to receive a word line signal.

5. The memory device as claimed in claim 4, wherein when the first stored data bit has the first logic value, the third transistor and the fourth transistor each have a first threshold voltage level and a second threshold voltage level, respectively, and when the first stored data bit has the second logic value, the third transistor and the fourth transistor each have the second threshold voltage level and the first threshold voltage level, respectively.

6. The memory device as claimed in claim 1, wherein the first memory string and the second memory string further include a third transistor and a fourth transistor, the third transistor and the fourth transistor being connected in series with the first transistor and the second transistor, respectively, and a control terminal of the third transistor and a control terminal of the fourth transistor being used to receive the first string select line signal and the second string select line signal, respectively.

7. The memory device as claimed in claim 6, wherein each of the control terminal of the first transistor, the control terminal of the second transistor, the control terminal of the third transistor, and the control terminal of the fourth transistor is configured to receive the preset positive bias voltage to calibrate each of the first transistor, the second transistor, the third transistor, and the fourth transistor.

8. A method of operating a memory device, comprising: comparing a first stored data bit and a first input bit using a first memory string and a second memory string; generating a first string current signal using the first memory string; generating a second string current signal using the second memory string; comparing the first string current signal and the second string current signal with a preset current level; and recalibrating the memory device when at least one of the current level of the first string current signal and the current level of the second string current signal is greater than the preset current level, wherein the first memory string and the second memory string respectively include a first transistor and a second transistor, a control terminal of the first transistor and a control terminal of the second transistor are respectively used to receive a first string select line signal and a second string select line signal, and each of the control terminals of the first transistor and the second transistor is used to receive a preset positive bias voltage to calibrate each of the first transistor and the second transistor.

9. The method of operation as described in claim 8, wherein when the first input bit has a first logic value, the first string select line signal has a first voltage level, when the first input bit has a second logic value, the first string select line signal has a second voltage level, and the first voltage level is within a linear region of the first transistor.

10. The method of operation as described in claim 9, wherein when the first input bit has the first logic value, the second string select line signal has the second voltage level, and when the first input bit has the second logic value, the second string select line signal has the first voltage level.

11. The method of operation as described in claim 10, wherein the first memory string and the second memory string further include a third transistor and a fourth transistor, the third transistor and the fourth transistor being used to store the first stored data bits, the third transistor and the fourth transistor being connected in series with the first transistor and the second transistor respectively, and each of a control terminal of the third transistor and a control terminal of the fourth transistor being used to receive a word line signal.

12. The method of operation as described in claim 11, wherein when the first input bit and the first stored data bit have the first logic value and the second logic value respectively, the first string current signal and the second string current signal have a first current level and a second current level respectively.

13. The method of operation as described in claim 12, wherein when the first input bit and the first stored data bit have the second logic value and the first logic value, respectively, the first string current signal and the second string current signal have the second current level and the first current level, respectively.

14. The method of operation as described in claim 13, wherein the preset current level is equal to the first current level multiplied by 1.

1.

15. The method of operation as described in claim 9, wherein recalibrating the memory device comprises: applying the preset positive bias voltage to each of the first transistor and the second transistor.

16. A memory system comprising a plurality of memory strings for generating a plurality of bit line signals, the memory strings comprising: a first memory string and a second memory string, respectively configured to receive a first string select line signal and a second string select line signal to compare a first stored data bit and a first input bit, wherein the first memory string includes a first transistor, the first string select line signal having a first voltage level when the first input bit has a first logic value, and the first string select line signal having a second voltage level when the first input bit has a second logic value, the first voltage level being within a linear region of the first transistor, control terminals of the plurality of transistors in the first memory string being correspondingly coupled to control terminals of the plurality of transistors in the second memory string, and the memory strings further comprising: A third memory string and a fourth memory string are respectively used to receive a third string select line signal and a fourth string select line signal to compare a second stored data bit and a second input bit. The first memory string, the second memory string, the third memory string and the fourth memory string are respectively used to generate a first string current signal, a second string current signal, a third string current signal and a fourth string current signal, and are used to add the first string current signal, the second string current signal, the third string current signal and the fourth string current signal to generate a first bit line signal among these bit line signals.

17. The memory system of claim 16, wherein the memory strings further comprise: a fifth memory string and a sixth memory string, respectively configured to receive the first string select line signal and the second string select line signal to compare a third stored data bit and the first input bit, wherein the fifth memory string and the sixth memory string are respectively configured to generate a fifth string current signal and a sixth string current signal to add the fifth string current signal and the sixth string current signal to generate a second bit line signal among the bit line signals.

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