Memory device and erase method thereof

Abstract

A memory device includes a memory array and a memory controller. The memory array includes a plurality of erase units that are formed in a plurality of semiconductor wells corresponding to the plurality of erase units. The memory controller is coupled to the memory array and is configured to perform an erase operation to erase an erase unit corresponding to a semiconductor well of the memory array. The memory controller is configured to bias the semiconductor well with a first well bias voltage and a second well bias voltage during the erase operation, wherein the first well bias voltage is different from the second well bias voltage.

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