Control circuit, semiconductor memory device, and control method of semiconductor memory device
Patent Information
- Application Number
- TW114113293
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-20
- Filing Date
- 2025-04-09
- Publication Date
- 2026-09-01
- Estimated Expiration
- 2045-04-08
AI Technical Summary
Time-to-digital converters (TDCs) are susceptible to variations due to manufacturing processes, temperature, and power supply voltage, leading to unsatisfactory resolution.
A control circuit with a plurality of delay units is used to generate a digital value corresponding to a specific delay amount by controlling the transmission path of a signal through a subset of delay units, allowing precise estimation of the delay between two signals.
The solution effectively estimates the delay between signals and generates an output signal corresponding to that delay, improving the resolution of TDCs.
Smart Images
Figure TWG2TA001074148_001 
Figure TWG2TA001074148_002 
Figure TWG2TA001074148_003
Abstract
Description
[Technical Field]
[0001] This invention relates to a control circuit, a semiconductor memory device, and a control method for the semiconductor memory device. [Previous Technology]
[0002] A Time-to-Digital Converter (TDC) circuit detects the delay (phase difference) between a first signal and a second signal and generates a digital value equivalent to this delay. TDC requires high-precision design of the delay elements. If differences in manufacturing processes, temperature, or power supply voltage cause variations or differences in the delay elements at each stage, the TDC will be affected by the PVT relation, resulting in the inability to achieve the required resolution. Therefore, effectively improving these problems has become a key technology for TDC. [Summary of the Invention]
[0003] This invention provides a control circuit, a semiconductor memory device, and a control method thereof. Utilizing a control circuit having a plurality of delay units, a portion of the delay units can be used to generate a digital value corresponding to a specific delay amount. This effectively estimates the delay amount between a first signal and a second signal and generates an output signal corresponding to that delay amount.
[0004] The present invention provides a control circuit, comprising: a delay unit for receiving a first signal, wherein the delay unit includes a plurality of delay units connected in series, each of the plurality of delay units delaying the input first signal; a detection unit for receiving a second signal, wherein the second signal is a delayed signal of the first signal, wherein when the second signal is input to the delay unit after the first signal is input, the detection unit detects the number of delay units through which the first signal passes in the plurality of delay units when the second signal is input; and a control unit for controlling the transmission path of the first signal in the delay unit, such that when the first signal is output from the delay unit, the number of delay units through which the first signal passes is equal to the number of delay units detected by the detection unit.
[0005] When the second signal is input, the number of delay units through which the first signal passes is detected as the delay amount between the first and second signals. Therefore, the delay amount can be easily detected when both the first and second signals are input. To ensure that the number of delay units through which the first signal passes is equal to the number of delay units detected by the detection unit (i.e., the delay amount between the first and second signals), the transmission path of the first signal is controlled in the delay unit. Therefore, the delay unit can easily generate an output signal that delays the input signal by that amount. The delay amount between the first and second signals is effectively estimated, and an output signal corresponding to that delay amount is generated.
[0006] The present invention further provides a semiconductor memory device including the above-described control circuit.
[0007] The present invention further provides a control method for a semiconductor memory device, which executes a control circuit for the semiconductor memory device. The control method includes: a delay section for inputting a first signal includes a plurality of delay units connected in series, each of the plurality of delay units delaying the input first signal; when the delayed signal of the first signal, i.e., the second signal, is input to the control circuit after the first signal is input to the delay section, the method detects the number of delay units through which the first signal passes when the second signal is input; and controls the transmission path of the first signal in the delay section so that when the first signal is output from the delay section, the number of delay units through which the first signal passes is equal to the number of delay units detected.
[0008] According to the control circuit, semiconductor memory device and control method of the present invention, the delay between the first signal and the second signal can be effectively estimated and an output signal corresponding to the delay can be generated.
Implementation Method
[0009] FIG1 is a schematic diagram of a semiconductor memory device configuration example according to an embodiment of the present invention. As shown in FIG1, the semiconductor memory device includes an input buffer 10, a delay circuit 20, a control circuit 30, a copying unit 40, and an output buffer 50.
[0010] Input buffer 10 buffers the external clock signal input to input buffer 10 and generates a reference clock signal clk_ref. The generated reference clock signal clk_ref is output to delay circuit 20 and control circuit 30.
[0011] The delay circuit 20 is a delay-locked loop (DLL) circuit that generates an output clock signal dll_clk by delaying the input reference clock signal clk_ref. The delay circuit 20 outputs the generated output clock signal dll_clk to the copying unit 40 and the output buffer 50. The delay circuit 20 includes the delay unit 31 and the detection unit 32 included in the control circuit 30.
[0012] The copying unit 40 outputs the output clock signal dll_clk generated by the delay circuit 20 as a feedback signal clk_fb to the control circuit 30.
[0013] The output buffer 50 outputs the output clock signal dll_clk generated by the delay circuit 20 as an internal clock signal to other circuits in the semiconductor memory device (omitted in the figure).
[0014] Referring to FIG2, the control circuit 30 includes a delay unit 31, a detection unit 32 and a control unit 33.
[0015] The delay unit 31 enables the input of the reference clock signal clk_ref or the start signal start_tdc, and includes a plurality of delay units U1 to U8 connected in series (eight in this embodiment). The reference clock signal clk_ref and the start signal start_tdc are each the "first signal" of the present invention.
[0016] A plurality of delay units U1 to U8 constitute an input signal that can be output after a certain delay. In Figure 2, among the plurality of delay units U1 to U8, the upstream delay unit U1 in the delay section 31 receives a signal (reference clock signal clk_ref or start signal start_tdc), and the subsequent delay units U2 to U8 receive the signals output by the previous delay units U1 to U7.
[0017] The plurality of delay units U1 to U8 each include one or more delay elements for delaying the input signal. Each of the plurality of delay units U1 to U8 includes an even number (two in this embodiment) of NAND circuits N1 to N16 as one or more delay elements. The logic level of the signal input to the delay section 31 and the logic level of the signal output from each delay unit U1 to U8 can be consistent. Furthermore, in FIG2, delay unit U1 includes two NAND circuits N1 and N2, delay unit U2 includes two NAND circuits N3 and N4, delay unit U3 includes two NAND circuits N5 and N6, delay unit U4 includes two NAND circuits N7 and N8, delay unit U5 includes two NAND circuits N9 and N10, delay unit U6 includes two NAND circuits N11 and N12, delay unit U7 includes two NAND circuits N13 and N14, and delay unit U8 includes two NAND circuits N15 and N16.
[0018] A plurality of NAND circuits N1 to N16, the input terminal of the upstream NAND circuit N1 of the delay section 31 receives a signal (reference clock signal clk_ref or start signal start_tdc), and the input terminal of the subsequent NAND circuits N2 to N16 receives the signal output by the previous NAND circuits N1 to N15. Among the plurality of NAND circuits N1 to N16, the other input terminal of each NAND circuit N1 to N10, N12, N14, and N16 receives the corresponding activation signal AS[1] to AS
[10] , AS
[12] , AS
[14] , and AS
[16] . When the logic value of the start signal AS[i] (in this embodiment, i is an integer between 1 and 16, excluding 11, 13, and 15) is "1", the NAND circuit Ni is started; when the logic value of the start signal AS[i] is "0", the NAND circuit Ni is not started. In this embodiment, the logic value of the start signal AS[i] is set by the control unit 33.
[0019] The delay section 31 forms a plurality of bypass paths BR1 to BR3, each with a different number of delay units, during the period from when the input signal (reference clock signal clk_ref or start signal start_tdc) is output from the delay section 31. In the example of FIG2, the bypass path BR1 is formed by shorting delay unit U1 and delay unit U8. Therefore, when the signal is output from the delay section 31 through the bypass path BR1, the number of delay units it passes through is 2 (delay units U1 and U8). Furthermore, the bypass path BR2 is formed by shorting delay unit U2 and delay unit U7. Therefore, when the signal is output from the delay section 31 through the bypass path BR2, the number of delay units it passes through is 4 (delay units U1, U2, U7, and U8). Moreover, the bypass path BR3 is formed by shorting delay unit U3 and delay unit U6. Therefore, the number of delay units (delay units U1, U2, U3, U6, U7, U8) that the signal passes through during the period when it is output from the delay unit 31 via the bypass path BR3 is 6.
[0020] Each of the plurality of bypass paths BR1~BR3 is configured to include at least one delay unit. Each of the bypass paths BR1~BR3 can delay the signal.
[0021] In Figure 2, bypass path BR1 includes a NAND circuit BN1 as a delay unit, bypass path BR2 includes a NAND circuit BN2 as a delay unit, and bypass path BR3 includes a NAND circuit BN3 as a delay unit. One input terminal of the NAND circuit BN1 in bypass path BR1 is connected to the output terminal of the NAND circuit N1 in delay unit U1, and the output terminal of NAND circuit BN1 is connected to another input terminal of the NAND circuit N15 in delay unit U8. Furthermore, one input terminal of the NAND circuit BN2 in bypass path BR2 is connected to the output terminal of the NAND circuit N3 in delay unit U2, and the output terminal of NAND circuit BN2 is connected to another input terminal of the NAND circuit N13 in delay unit U7. Moreover, one input terminal of the NAND circuit BN3 in bypass path BR3 is connected to the output terminal of the NAND circuit N5 in delay unit U3, and the output terminal of NAND circuit BN3 is connected to another input terminal of the NAND circuit N11 in delay unit U6. Furthermore, a start signal AS[B1] to AS[B3] is input to another input terminal of each NAND circuit BN1 to BN3 to start the corresponding NAND circuit BN1 to BN3. When the logic value of the start signal AS[Bj] (in this embodiment, j is an integer between 1 and 3) is "1", the NAND circuit BNj starts; when the logic value of the start signal AS[Bj] is "0", the NAND circuit BNj does not start. In this embodiment, the logic values of the start signals AS[B1] to AS[B3] are set by the control unit 33.
[0022] The delay section 31 is configured in a U-shape from a top view (that is, a plurality of delay units U1 to U8 (more specifically, a plurality of NAND circuits N1 to N16) are arranged in a U-shape from a top view). This allows the area formed by the delay section 31 to be compactly integrated. Furthermore, each bypass path BR1 to BR3 can be formed by shorting the delay units arranged opposite each other in the U-shaped path, thereby shortening the length of each bypass path BR1 to BR3.
[0023] The detection unit 32 is configured such that a delayed signal of the start signal start_tdc, i.e., the end signal end_tdc, can be input. The detection unit 32 is configured such that when the start signal start_tdc is input to the delay unit 31, and the end signal end_tdc is input, it can detect the number of delay units passed by the start signal start_tdc among the plurality of delay units U1 to U8 when the end signal end_tdc is input. The end signal end_tdc is an example of the "second signal" of this invention.
[0024] The detection unit 32 includes a latching unit corresponding to each of the plurality of delay units U1 to U8. When the end signal end_tdc is input, the detection unit 32 latches the signal output by the corresponding delay unit U1 to U8 into the latching unit. When the end signal end_tdc is input, the detection unit 32 detects the number of delay units among the plurality of delay units U1 to U8 that have latched the signal with the same value as the start signal start_tdc, which is the number of delay units that the start signal start_tdc has passed through when the end signal end_tdc is input. When the start signal start_tdc and the end signal end_tdc are input respectively, the number of delay units that the start signal start_tdc has passed through when the end signal end_tdc is input can be easily detected (that is, the delay between the start signal start_tdc and the end signal end_tdc).
[0025] The latching section includes a flip-flop circuit, which includes a D-type flip-flop circuit. It latches the signals output from the delay units U1 to U8.
[0026] As shown in FIG. 2, the detection unit 32 includes D-type flip-flop circuits FF1 to FF8 corresponding to a plurality of delay units U1 to U8. The D terminal of D-type flip-flop circuit FF1 is connected to the output terminal of NAND circuit N2 of delay unit U1, and the D terminal of D-type flip-flop circuit FF2 is connected to the output terminal of NAND circuit N4 of delay unit U2. Furthermore, the D terminal of D-type flip-flop circuit FF3 is connected to the output terminal of NAND circuit N6 of delay unit U3, and the D terminal of D-type flip-flop circuit FF4 is connected to the output terminal of NAND circuit N8 of delay unit U4. The D terminal of D-type flip-flop circuit FF5 is connected to the output terminal of NAND circuit N10 of delay unit U5, and the D terminal of D-type flip-flop circuit FF6 is connected to the output terminal of NAND circuit N12 of delay unit U6. Furthermore, the D terminal of the D-type flip-flop circuit FF7 is connected to the output terminal of the NAND circuit N14 of the delay unit U7, and the D terminal of the D-type flip-flop circuit FF8 is connected to the output terminal of the NAND circuit N16 of the delay unit U8. The clock terminals of each of the plurality of D-type flip-flop circuits FF1 to FF8 receive an end signal end_tdc. The outputs of each of the plurality of D-type flip-flop circuits FF1 to FF8 are sent to the control unit 33.
[0027] The control unit 33 controls the transmission path of the reference clock signal clk_ref in the delay unit 31, so that when the reference clock signal clk_ref is output from the delay unit 31, the number of delay units through which the reference clock signal clk_ref passes is equal to the number of delay units detected by the detection unit 32.
[0028] The control unit 33 controls the reference clock signal clk_ref to be transmitted through a bypass path (any one of bypass paths BR1 to BR3) formed by the delay unit 31. When the reference clock signal clk_ref is output from the delay unit 31, the number of delay units for the reference clock signal clk_ref is equal to the number of delay units detected by the detection unit 32. Therefore, since the reference clock signal clk_ref is output from the delay unit 31 through the bypass path, an output signal that delays the number of delay units detected by the detection unit 32 can be easily output from the delay unit 31.
[0029] Among a plurality of bypass paths BR1 to BR3, the control unit 33 selects a bypass path through which the reference clock signal clk_ref passes when it is output from the delay unit 31, wherein the number of delay units is equal to the number of delay units detected by the detection unit 32, and controls the transmission of the reference clock signal clk_ref through this bypass path. The input reference clock signal clk_ref can be delayed by the optimal bypass path selected from the plurality of bypass paths BR1 to BR3.
[0030] The control unit 33 is configured to receive the reference clock signal clk_ref output from the input buffer 10 and the feedback signal clk_fb output from the copying unit 40. Furthermore, at the rising edge of the feedback signal clk_fb, the control unit 33 asserts the start signal start_tdc (i.e., sets the logic value to "1") and outputs it to the delay unit 31. Additionally, at the rising edge of the reference clock signal clk_ref after the rising edge of the feedback signal clk_fb, the control unit 33 asserts the end signal end_tdc (sets the logic value to "1") and outputs it to the detection unit 32.
[0031] The control unit 33 sets the logic values of the start signals AS[1]~AS
[10] , AS
[12] , AS
[14] , AS
[16] and start signals AS[B1]~AS[B3] to "1" or "0" according to the number of delay units detected by the detection unit 32, so as to control the transmission path of the reference clock signal clk_ref in the delay unit 31.
[0032] Referring to Figure 3, the relationship between the signal and the delay amount in the control circuit 30 is explained. When the reference clock signal clk_ref is output from the input buffer 10 and input to the delay circuit 20, the delay circuit 20 delays the input reference clock signal clk_ref, thereby generating the output clock signal dll_clk. Assuming that the control circuit 30 does not perform delay amount detection, the delay circuit 20 generates the output clock signal dll_clk without using the delay unit 31. The copying unit 40 outputs the output clock signal dll_clk generated by the delay circuit 20 as a feedback signal clk_fb to the control circuit 30.
[0033] Here, when the delay of the output clock signal dll_clk is adjusted using the DLL circuit, a sequence of delay (locking) actions of the DLL circuit (e.g., starting the delay lines one by one and synchronizing the reference clock signal clk_ref and the output clock signal dll_clk) will be executed.
[0034] The lock time tDLL caused by the delayed action of the DLL circuit can be expressed by the following formula (1): [Formula (1)] tINT+tDLL=N×tCK (1)
[0035] In addition, the lock time tDLL can be expressed by the following formula (2): [Formula (2)] tDLL=X×CDL+Y×FDL (2) In the above formula (2), CDL represents the delay of a signal in a coarse delay line (CDL) with a relatively large adjustment pitch, and FDL represents the delay of a signal in a fine delay line (FDL) with a relatively small adjustment pitch. In addition, X and Y each represent the number of delay units used for signal delay.
[0036] As shown in Figure 3, the period from the rising edge of the feedback signal clk_fb (and the corresponding start signal start_tdc) at time t1 to the rising edge of the reference clock signal clk_ref (and the corresponding end signal end_tdc) at time t2 is assumed to be almost equal to X×CDL in the above formula (2). In the detection unit 32, the value of X (that is, the number of delay units used for signal delay in CDL (delay unit 31)) is detected.
[0037] Referring to Figures 4 to 6, Figure 4 shows the state of the signals in the control circuit 30 during the delay estimation process, and shows the logic values of the signals in the control circuit 30 at time t1 in Figure 3. At time t1, when the rising edge of the feedback signal clk_fb is input to the control unit 33, the control unit 33 sets the start signal start_tdc to valid (sets the logic value to "1") and outputs it to the delay unit 31. The control unit 33 sets the logic value of each of the start signals AS[1] to AS
[10] , AS
[12] , AS
[14] , and AS
[16] to "1", and sets the logic value of each of the start signals AS[B1] to AS[B3] to "0". Therefore, the start signal start_tdc is transmitted in the delay unit 31 via each delay unit U1 to U8.
[0038] Figure 5 shows the state of the signals in the control circuit 30 during the delay estimation process, and shows the logic value of the signals in the control circuit 30 at time t2 in Figure 3. At time t2, when the rising edge of the reference clock signal clk_ref after the rising edge of the feedback signal clk_fb is input to the control unit 33, the control unit 33 sets the end signal end_tdc to valid (sets the logic value to "1") and outputs it to the detection unit 32. Each of the plurality of D-type flip-flop circuits FF1 to FF8 in the detection unit 32 latches the signal output from the corresponding delay unit U1 to U8 and outputs the latched signal to the control unit 33. As shown in Figure 5, at time t2, the valid start signal start_tdc has been transmitted to the delay unit U6, and the logic value of the signal latched by each D-type flip-flop circuit FF1 to FF6 corresponding to the delay unit U1 to U6 is "1". On the other hand, the logic value of the signal latched by the D-type flip-flop circuits FF7 to FF8 corresponding to each of the delay units U7 to U8 before the start signal start_tdc has been transmitted is "0". Therefore, the detection unit 32 can detect (estimate) the number of D-type flip-flop circuits FF1 to FF8 that latch the signal with a logic value of "1" when the valid end signal end_tdc is input (in the example of FIG5, there are 6), as the number of delay units through which the start signal start_tdc passes when the end signal end_tdc is input.
[0039] Figure 6 shows the state of the signal in the control circuit 30 during output signal generation. The control unit 33 uses a switching circuit (omitted in the figure) or the like to input the reference clock signal clk_ref to the delay unit 31. When the reference clock signal clk_ref is output from the delay unit 31, the control unit 33 controls the transmission path of the reference clock signal clk_ref in the delay unit 31 in such a way that the number of delay units through which the reference clock signal clk_ref passes is equal to the number of delay units detected by the detection unit 32.
[0040] Specifically, the control unit 33 controls the transmission path of the reference clock signal clk_ref in the delay unit 31 by transmitting it through any one of the multiple bypass paths BR1 to BR3. The control unit 33 sets each of the start signal start_tdc and the end signal end_tdc to invalid (sets the logic value to "0"). For example, as shown in FIG5, if the number of delay units detected in the detection unit 32 is 6 (the number of NAND circuits is 12), then the control unit 33 controls the reference clock signal clk_ref to pass through the bypass path BR3 of the multiple bypass paths BR1 to BR3, so that the reference clock signal clk_ref passes through 6 delay units (the number of NAND circuits is 12) when it is output from the delay unit 31. The control unit 33 sets each logic value of the start signals AS[1] to AS[5], AS
[12] , AS
[14] , AS
[16] , and AS[B3] to "1", and sets each logic value of the start signals AS[6] to AS
[10] and AS[B1] to AS[B2] to "0". Therefore, the reference clock signal clk_ref is transmitted in the delay unit 31 via each delay unit U1 to U3, the bypass path BR3, and each delay unit U6 to U8. That is, the reference clock signal clk_ref is transmitted via NAND circuits N1, N2, N3, N4, N5, BN3, N11, N12, N13, N14, N15, and N16.
[0041] In this way, the delay unit 31 can easily generate an output signal from the input signal (reference clock signal clk_ref) that delays the amount of delay detected by the detection unit 32.
[0042] As described above, according to the control circuit 30, semiconductor memory device, and control method of this embodiment, when the end signal end_tdc (second signal) is input, the start signal start_tdc (first signal) is detected by the number of delay units as the delay amount between the start signal start_tdc and the end signal end_tdc. By inputting the start signal start_tdc and the end signal end_tdc respectively, the delay amount can be easily detected. Furthermore, according to the control circuit 30, semiconductor memory device, and control method of this embodiment, the transmission path of the reference clock signal clk_ref in the delay unit 31 is controlled such that the number of delay units through which the reference clock signal clk_ref (first signal) passes is equal to the number of delay units detected by the detection unit 32, so that the delay unit 31 can easily generate an output signal that delays this delay amount from the input signal (reference clock signal clk_ref). Therefore, it is possible to efficiently estimate the delay between the start signal start_tdc and the end signal end_tdc, and generate the corresponding output signal for this delay.
[0043] The delay unit Uk (k is an integer between 1 and 8) includes: a NAND circuit N(2k-1) that delays the start signal start_tdc or the reference clock signal clk_ref (first signal); and a NAND circuit N(2k) connected to the output of the NAND circuit N(2k-1). As shown in FIG7, the delay unit Uk may include the NAND circuit N(2k-1), the NAND circuit N(2k), and the NAND circuit CNk connected between the NAND circuit N(2k-1) and the corresponding D-type flip-flop circuit Ffk (latch section). The NAND circuit N(2k-1) is an example of the "first delay element" of the present invention, the NAND circuit N(2k) is an example of the "second delay element" of the present invention, and the NAND circuit CNk is an example of the "third delay element" of the present invention. Three NAND circuits (delay elements) are used to delay the signal.
[0044] In Figure 7, a NAND circuit CN1 is provided between NAND circuit N1 and the corresponding D-type flip-flop circuit FF1, and a NAND circuit CN2 is provided between NAND circuit N3 and the corresponding D-type flip-flop circuit FF2. Furthermore, a NAND circuit CN3 is provided between NAND circuit N5 and the corresponding D-type flip-flop circuit FF3, and a NAND circuit CN4 is provided between NAND circuit N7 and the corresponding D-type flip-flop circuit FF4. Additionally, a NAND circuit CN5 is provided between NAND circuit N9 and the corresponding D-type flip-flop circuit FF5, and a NAND circuit CN6 is provided between NAND circuit N11 and the corresponding D-type flip-flop circuit FF6. Furthermore, a NAND circuit CN7 is provided between NAND circuit N13 and the corresponding D-type flip-flop circuit FF7, and a NAND circuit CN8 is provided between NAND circuit N15 and the corresponding D-type flip-flop circuit FF8.
[0045] In Figure 7, one input terminal of NAND circuit CN1 is connected to the output terminal of NAND circuit N1, and the output terminal of NAND circuit CN1 is connected to the D terminal of D-type flip-flop circuit FF1. One input terminal of NAND circuit CN2 is connected to the output terminal of NAND circuit N3, and the output terminal of NAND circuit CN2 is connected to the D terminal of D-type flip-flop circuit FF2. One input terminal of NAND circuit CN3 is connected to the output terminal of NAND circuit N5, and the output terminal of NAND circuit CN3 is connected to the D terminal of D-type flip-flop circuit FF3. One input terminal of NAND circuit CN4 is connected to the output terminal of NAND circuit N7, and the output terminal of NAND circuit CN4 is connected to the D terminal of D-type flip-flop circuit FF4. One input terminal of NAND circuit CN5 is connected to the output terminal of NAND circuit N9, and the output terminal of NAND circuit CN5 is connected to the D terminal of D-type flip-flop circuit FF5. One input terminal of NAND circuit CN6 is connected to the output terminal of NAND circuit N11, and the output terminal of NAND circuit CN6 is connected to the D terminal of D-type flip-flop circuit FF6. One input terminal of NAND circuit CN7 is connected to the output terminal of NAND circuit N13, and the output terminal of NAND circuit CN7 is connected to the D terminal of D-type flip-flop circuit FF7. One input terminal of NAND circuit CN8 is connected to the output terminal of NAND circuit N15, and the output terminal of NAND circuit CN8 is connected to the D terminal of D-type flip-flop circuit FF8.
[0046] Each of the NAND circuits CN1 to CN8 has a corresponding start signal AS[C1] to AS[C8] input to its other input terminal. The logic value of each of the start signals AS[C1] to AS[C8] can be set by the control unit 33. The control unit 33 can set the logic value of each of the start signals AS[C1] to AS[C8] to "1" (that is, each NAND circuit CN1 to CN8 can be started) in the delay estimation processing described with reference to Figures 4 and 5. In addition, the control unit 33 can set the logic value of each of the start signals AS[C1] to AS[C8] to "0" (that is, each NAND circuit CN1 to CN8 can be deactivated) in the output signal generation processing described with reference to Figure 6.
[0047] In one embodiment, the delay portion 31 is U-shaped in plan view, but the present invention is not limited thereto. The delay portion 31 may be a straight line as shown in FIG8, or may have a shape different from the U-shaped or straight line shape in plan view.
[0048] Each bypass path BR1 to BR3 has a delay unit, and at least one of the multiple bypass paths BR1 to BR3 may have more than two delay units (delay elements).
[0049] Bypass paths BR1~BR3, the number of bypass paths can be arbitrarily set according to the number of delay units (delay elements) through which the input signal passes.
[0050] The delay element can be a NAND circuit, but the present invention is not limited thereto. For example, other circuits such as inverter circuits or buffer circuits can be used as delay elements.
[0051] The semiconductor memory device can be DRAM, but the present invention is not limited thereto. For example, the semiconductor memory device can be Static Random Access Memory (SRAM) or Pseudo-Static Random Access Memory (pSRAM), flash memory or other semiconductor memory devices. [Simplified Explanation of the Diagram]
[0052] Figure 1 is a schematic diagram of a configuration example of a semiconductor memory device according to an embodiment of the present invention. Figure 2 is a schematic diagram of a control circuit according to an embodiment of the present invention. Figure 3 is a time diagram of signal voltage changes in the control circuit. Figure 4 is a signal state diagram in the control circuit during delay estimation. Figure 5 is a signal state diagram in the control circuit during delay estimation. Figure 6 is a signal state diagram in the control circuit during output signal generation. Figures 7 and 8 are schematic diagrams of configuration examples of a portion of the control circuit in different embodiments.
Claims
1. A control circuit, comprising: A delay unit receives a first signal, comprising a plurality of delay units connected in series, each of which delays the first signal, which may be a start signal or a reference clock signal; a detection unit receives an end signal, wherein when the first signal is a start signal, the end signal is a delayed signal of the start signal; after the start signal is input to the delay unit, when the end signal is input to the detection unit, the detection unit detects the number of delay units through which the start signal has passed in the plurality of delay units up to the time the end signal is input; and a control unit, when the first signal is a reference clock signal, controls the transmission path of the reference clock signal in the delay unit so that when the reference clock signal is output from the delay unit, the number of delay units through which the reference clock signal passes is equal to the number of delay units detected by the detection unit.
2. The control circuit as described in claim 1, wherein, The control unit controls the reference clock signal to form a bypass path through the delay unit for transmission, so that when the reference clock signal is output by the delay unit, the number of delay units through which the first signal passes is equal to the number of delay units detected by the detection unit.
3. The control circuit as claimed in claim 2, wherein in the delay section, the number of delay units through which the reference clock signal is output from the delay section is different from the number of bypass paths; the control section selects, among the plurality of bypass paths, the number of delay units through which the reference clock signal is output from the delay section is equal to the number of bypass paths detected by the detection section that are equal to the number of delay units, and controls the transmission of the reference clock signal through the selected bypass path.
4. The control circuit as described in claim 2, wherein the bypass path includes at least one delay unit.
5. The control circuit as claimed in claim 1, wherein the detection unit includes a latching unit, that is, a latching unit corresponding to each of the plurality of delay units, which latches the signal output by the corresponding delay unit when the end signal is input; when the end signal is input, the detection unit detects the number of delay units among the plurality of delay units for which the corresponding latching unit has latched a signal with the same value as the start signal, as the number of delay units through which the start signal passes when the end signal is input.
6. The control circuit as claimed in claim 5, wherein at least one of the plurality of delay units comprises: A first delay element delays the start signal or the reference clock signal; The second delay element is connected to the output of the first delay element; And a third delay element, which connects the first delay element and the corresponding latching unit.
7. The control circuit as described in claim 5, wherein the latching section includes a flip-flop circuit.
8. The control circuit as described in claim 7, wherein the flip-flop circuit includes a D-type flip-flop circuit.
9. The control circuit as claimed in claim 1, wherein the delay section is formed in a U-shape when viewed from above.
10. The control circuit as claimed in claim 1, wherein each of the plurality of delay units includes a plurality of delay elements that delay the start signal or the reference clock signal.
11. The control circuit as claimed in claim 10, wherein each of the plurality of delay units includes an even number of NAND circuits as the plurality of delay elements.
12. A semiconductor memory device, comprising a control circuit as described in any one of claims 1 to 11.
13. A method for controlling a semiconductor memory device, the method comprising: A first signal is input to a delay unit, which includes a plurality of delay units connected in series. Each of the plurality of delay units delays the input of the first signal. The first signal is either a start signal or a reference clock signal. When the first signal is a start signal, after the start signal is input to the delay unit, when the delayed signal of the start signal, i.e., the end signal, is input to a control circuit, the step of detecting the number of delay units through which the start signal passes when the end signal is input; and when the first signal is the reference clock signal, the step of controlling the transmission path of the reference clock signal in the delay unit so that when the reference clock signal is output from the delay unit, the number of delay units through which the reference clock signal passes is equal to the number of delay units detected.