Method for controlling level shifter as input tolerance input / output level shifter, and associated apparatus

Abstract

A method for controlling a level shifter as an input tolerance input / output (I / O) level shifter and associated apparatus are provided, where the input tolerance I / O level shifter is arranged to couple an I / O pad to a buffering circuit within an input receiver circuit. The method may include performing voltage-detection-based gate bias control on a first N-type transistor within the input tolerance I / O level shifter, including: performing at least one voltage detection operation on a received voltage level on the I / O pad to generate at least one voltage detection result, for generating a self-control signal corresponding to the at least one voltage detection result to perform gate bias control; and according to the at least one voltage detection result, selectively performing a level-down operation to generate a level-down voltage as the self-control signal according to the received voltage level, for controlling a gate bias of the first N-type transistor.

Description

[Technical Field]

[0001] This invention relates to circuit control, and more particularly to a method and related apparatus for controlling a level shifter as an input tolerance input / output (I / O) level shifter. [Previous Technology]

[0002] According to related technologies, the nominal voltage of some I / O devices conforming to newer technologies may be 1.8 volts (V), while the nominal voltage of some I / O devices conforming to older technologies may be 3.3 V. For compatibility with older technologies, it is desirable for circuit designers to operate at voltages higher than the device's nominal voltage for input tolerance cells. For example, when an I / O device has a nominal voltage of 1.8 V, it is desirable for the circuit designer to interface with a 3.3 V voltage. However, regarding device reliability, 1.8 V I / O devices in input tolerance cells may be severely degraded due to excessive voltage differences during transient behavior, potentially shortening their lifespan. In particular, time-dependent oxide breakdown and hot carrier injection may occur. Therefore, a novel approach and related architecture are needed to address these problems with little or no side effects. [Summary of the Invention]

[0003] The purpose of this invention is to provide a method and related apparatus for controlling a level offset device as an input tolerance I / O level offset device, so as to solve the above-mentioned problems.

[0004] At least one embodiment of the present invention provides a device for controlling a level offset as an input-tolerant I / O level offset, wherein the input-tolerant I / O level offset can be used to couple an I / O pad to a buffer circuit within an input receiver circuit to act as a sub-circuit of the input receiver circuit. The device may include a voltage-detection-based gate bias control circuit for voltage-detection-based gate bias control of a first N-type transistor within the input-tolerant I / O level offset, wherein a second N-type transistor system within the input-tolerant I / O level offset is coupled to the first N-type transistor, and a gate of the second N-type transistor is coupled to a power supply voltage. Additionally, the voltage-sensing-based gate bias control circuit may include a voltage sensing and control circuit coupled to one of the I / O pads, and a level-down device coupled to the voltage sensing and control circuit and a gate of the first N-type transistor. For example, the voltage sensing and control circuit may perform at least one voltage sensing operation on a received voltage level on the I / O pad to generate at least one voltage sensing result, which in turn generates a self-control signal corresponding to the at least one voltage sensing result for gate bias control. The at least one voltage sensing result indicates whether the received voltage level corresponds to a logic high state or a logic low state. The level-down device may selectively perform a level-down operation based on the at least one voltage sensing result to generate a level-down voltage as the self-control signal, thereby controlling the gate bias of the first N-type transistor.

[0005] At least one embodiment of the present invention provides a method for controlling a level offset device as an input-tolerance I / O level offset device, wherein the input-tolerance I / O level offset device can be used to couple an I / O pad to a buffer circuit within an input receiver circuit to act as a sub-circuit of the input receiver circuit. The method may include: voltage-sensing gate bias control of a first N-type transistor within the input-tolerance I / O level offset device, wherein a second N-type transistor system within the input-tolerance I / O level offset device is coupled to the first N-type transistor, and a gate of the second N-type transistor is coupled to a power supply voltage. For example, the voltage-sensing-based gate bias control of the first N-type transistor within the input tolerance I / O level offset may further include: performing at least one voltage sensing operation on a received voltage level on the input / output pad to generate at least one voltage sensing result for generating an auto-control signal corresponding to the at least one voltage sensing result to perform gate bias control, wherein the at least one voltage sensing result indicates whether the received voltage level corresponds to a logic high state or a logic low state; and selectively performing a level-down operation based on the at least one voltage sensing result to generate a level-down voltage based on the received voltage level as the auto-control signal for controlling one of the gate biases of the first N-type transistor.

[0006] One of the many advantages of the present invention is that, through appropriate design, the method and related apparatus of the present invention can dynamically manage the input receiver circuit to ensure its proper operation under various conditions. For example, when an I / O device has a nominal voltage of 1.8 V, it can be used to interface with a 1.8 V voltage interface as well as a 3.3 V voltage interface, thereby reducing related costs. In particular, the method and related apparatus of the present invention can maintain the normal operation of the input receiver circuit over time without serious degradation. Furthermore, the method and related apparatus of the present invention can solve the problems of related technologies with little or no side effects.

Implementation Method

[0007] Figure 1 is a schematic diagram of a device 100 according to an embodiment of the present invention for controlling a level offset (e.g., a level offset having at least two transistors) as an input tolerance I / O level offset 20, wherein the device 100 can be operated according to a method for controlling the level offset as an input tolerance I / O level offset. The input tolerance I / O level offset 20 can be used to couple an I / O pad 10 to a buffer circuit 40 (e.g., an I / O buffer circuit) within an input receiver circuit to act as a sub-circuit of the input receiver circuit. According to some embodiments, a plurality of sub-circuits of the input receiver circuit may include an I / O pad 10, an input tolerance I / O level offset 20, a buffer circuit 40, etc., on one of the receiving paths of the input receiver circuit, and the device 100 may include at least a portion of the plurality of sub-circuits (e.g., a portion or all of the sub-circuits). For example, device 100 may include the entire input receiver circuit, or in particular, may represent the input receiver circuit, but the invention is not limited thereto.

[0008] As shown in Figure 1, device 100 may include a voltage-detection-based gate bias control circuit 110 for voltage-detection-based gate bias control of a first N-type transistor 21 within an input tolerance I / O level offset device 20, wherein a second N-type transistor 22 within the input tolerance I / O level offset device 20 is coupled to the first N-type transistor 21, and a gate of the second N-type transistor 22 (not shown in Figure 1) is coupled to a power supply voltage VCC. Additionally, the voltage-detection-based gate bias control circuit 110 may include a voltage detection and control circuit 111 coupled to one of the I / O pads 10, and a level reduction device 112 coupled to the voltage detection and control circuit 111 and a gate of the first N-type transistor 21 (not shown in Figure 1). The voltage detection and control circuit 111 may include a first voltage detection and path control sub-circuit 1111 and a second voltage detection and path control sub-circuit 1112.

[0009] The voltage detection and control circuit 111 can perform at least one voltage detection operation (e.g., one or more voltage detection operations) on a received voltage level IO on the I / O pad 10 to generate at least one voltage detection result (e.g., one or more voltage detection results) for generating an automatic control signal Va corresponding to the at least one voltage detection result to perform gate bias control, wherein the at least one voltage detection result indicates whether the received voltage level IO corresponds to a logic high state or a logic low state. The level reduction device 112 can selectively perform a level reduction operation based on the at least one voltage detection result to generate a level reduction voltage as an automatic control signal Va based on the received voltage level IO for controlling the gate bias of one of the first N-type transistors 21. For better understanding, when the received voltage level IO is in the logic high state, the received voltage level IO can be equal to a predetermined higher voltage IOH. When the received voltage level IO is in this logic low state, the received voltage level IO can be equal to a predetermined lower voltage IOL, where the predetermined lower voltage IOL can be ground voltage. For example, for an application where the predetermined higher voltage IOH is equal to the power supply voltage VCC, IOH = VCC = 1.8 V and IOL = 0 V, and for an application where the predetermined higher voltage IOH is greater than the power supply voltage VCC, IOH = 3.3 V > VCC = 1.8 V and IOL = 0 V, but the invention is not limited thereto. In some examples, the power supply voltage VCC, the predetermined higher voltage IOH, and / or the predetermined lower voltage IOL can be varied.

[0010] The first voltage detection and path control subcircuit 1111 can selectively open a signal path between the I / O pad 10 and the level reduction device 112 based on the at least one voltage detection result, so as to allow the level reduction device 112 to perform the level reduction operation to generate the level reduction voltage as the self-control signal Va. The second voltage detection and path control subcircuit 1112 can selectively close a power path between the power supply voltage VCC and an output terminal of the level reduction device 112 based on the at least one voltage detection result, so as to allow the level reduction device 112 to correctly output the level reduction voltage as the self-control signal Va, without being affected by the power supply voltage VCC. In particular, the at least one voltage detection result may include a first voltage detection result at a first time point and a second voltage detection result at a second time point, wherein the first voltage detection result indicates that the received voltage level IO corresponds to the logic high state, and the second voltage detection result indicates that the received voltage level IO corresponds to the logic low state. For example, the first voltage detection and path control subcircuit 1111 can open the signal path at the first time point based on the first voltage detection result, allowing the level downshifting device 112 to perform the level downshifting operation and generate the level downshifting voltage as the self-control signal Va. The second voltage detection and path control subcircuit 1112 can close the power path at the first time point based on the first voltage detection result, allowing the level downshifting device 112 to correctly output the level downshifting voltage as the self-control signal Va, unaffected by the power supply voltage VCC. Furthermore, the first voltage detection and path control subcircuit 1111 can close the signal path at the second time point based on the second voltage detection result to prevent the level downshifting device 112 from performing the level downshifting operation. The second voltage detection and path control subcircuit 1112 can open the power path at the second time point based on the second voltage detection result to generate the self-control signal Va according to the power supply voltage VCC.

[0011] Based on the architecture shown in Figure 1, the device 100 operating according to this method can dynamically manage the input receiver circuit so that the input receiver circuit operates correctly under various conditions. For better understanding, Figure 2 illustrates a single-transistor level offset control scheme, where the power supply voltage VCC18 can be used as an example of the aforementioned power supply voltage VCC, and VCC18 = 1.8 V. Assuming that the voltage applied across the drain and source of any N-type transistor NM can be called the drain-to-source voltage Vds, for example, corresponding to the drain-to-source voltage Vds(NM) of any N-type transistor NM, when the level offset 19 has only a single transistor, such as the N-type transistor NM0 shown in sub-figure (a), the drain-to-source voltage Vds(NM0) of the N-type transistor NM0 can be written as the drain-to-source voltage Vds0 shown in sub-figure (b). When the received voltage level IO is equal to a predetermined voltage level VIO, such as 3.3 V (e.g., IO = 3.3 V), the drain-to-source voltage Vds0 of the N-type transistor NM0 can be equal to the voltage difference between the received voltage level IO (especially the predetermined voltage level VIO) and the voltage level of the intermediate signal IOA on the input terminal of the pre-drive circuit 30 (or the output terminal of the level offset 19). When IO = 3.3 V, IOA = 1.8 V - Vtn, where “Vtn” can represent the threshold voltage (or turn-on voltage) of the N-type transistor NM. Depending on the process, if Vtn > 0.3 V, then Vds0 may > 1.8 V, which indicates a reliability problem; in particular, as shown in sub-figure (c), Vds0 > 1.8 V indicates excessive oxide stress. In contrast, the method and apparatus 100 of the present invention can dynamically manage the input receiver circuit so that the input receiver circuit operates correctly under various conditions.

[0012] Figure 3 illustrates a multi-transistor level offset control scheme according to an embodiment of the present invention, wherein the power supply voltage VCC18 can be used as an example of the aforementioned power supply voltage VCC, VCC18 = 1.8 V, and the intermediate signal VB can be used as an example of the intermediate signal Vb shown in Figure 1. As shown in sub-figure (a), the plurality of sub-circuits of the input receiver circuit may include I / O pads 10, input tolerance I / O level offset 20, pre-drive circuit 30, buffer circuit 40, etc. on the receiving path, and the gate bias control circuit 110 based on voltage detection can be integrated into the receiving path as one of the plurality of sub-circuits. The first N-type transistor 21 and the second N-type transistor 22 can be implemented as N-type transistors NM2 and NM3, respectively. When the input tolerance I / O level offset 20 has multiple transistors, such as N-type transistors NM2 and NM3, the drain-to-source voltages Vds(NM2) and Vds(NM3) of the N-type transistors NM2 and NM3 can be written as drain-to-source voltages Vds2 and Vds3 as shown in sub-figure (b). The N-type transistors NM2 and NM3 can split excessive voltages into two voltages to withstand them (labeled as "Vds3 + Vds2" in sub-figure (b) for simplicity). When the received voltage level IO is equal to the predetermined voltage level VIO, such as 3.3 V (e.g., IO = 3.3 V), the drain-to-source voltage Vds2 of the N-type transistor NM2 can be equal to the voltage difference between the received voltage level IO (especially the predetermined voltage level VIO) and the voltage level of the intermediate signal VB, while the drain-to-source voltage Vds3 of the N-type transistor NM3 can be equal to the voltage difference between the voltage level of the intermediate signal VB and the voltage level of the intermediate signal IOA on the input terminal of the pre-drive circuit 30 (or the output terminal of the input tolerance I / O level offset 20). As shown in sub-figure (c), Vds2 < 1.8 V and Vds3 < 1.8 V, and there is no problem of excessive oxidation stress.

[0013] For example, when an I / O device has a nominal voltage of 1.8 V, it can be used to interface with a 1.8 V voltage interface as well as a 3.3 V voltage interface to reduce related costs. In particular, over time, the method and apparatus 100 of the present invention can maintain the normal operation of the input receiver circuit without serious degradation.

[0014] Figure 4 illustrates, according to an embodiment of the present invention, the hardware architecture involved in the multi-transistor level offset control scheme shown in Figure 3, wherein the transistors (e.g., N-type transistors and P-type transistors) in the hardware architecture can be metal-oxide-semiconductor field-effect transistors (MOSFETs), such as N-type MOSFETs (or "NMOSFETs") and P-type MOSFETs (or "PMOSFETs"), but the present invention is not limited thereto. The types of these transistors can be varied as long as they do not impede the implementation of the present invention. Additionally, the input receiver circuit can set an input enable signal IE to an input enable / disable state to indicate whether data buffering for the receiving path is enabled. When the input enable signal IE is set to the input enable state, the buffer circuit 40 can perform data buffering for the receiving path to output the received data to a subsequent circuit, such as a data processing circuit, through the data output signal O.

[0015] The partial hardware architecture of the voltage-sensing gate bias control circuit 110 can be described as follows. In the voltage sensing and control circuit 111, the first voltage sensing and path control sub-circuit 1111 may include a first switch coupled to one of the I / O pads 10, such as a P-type transistor PM1, to selectively open the signal path according to the at least one voltage sensing result, so as to allow the level down device 112 to perform the level down operation to generate the level down voltage as the self-control signal Va. The second voltage sensing and path control sub-circuit 1112 may include a second switch coupled to one of the I / O pads 10, such as a P-type transistor PM2, to selectively close the power path according to the at least one voltage sensing result, so as to allow the level down device 112 to correctly output the level down voltage as the self-control signal Va, without being affected by the power supply voltage VCC, such as the power supply voltage VCC18. As shown in Figure 4, one gate of P-type transistor PM1 and one gate of P-type transistor PM2 are coupled to the power supply voltage VCC18 and the I / O pad 10, respectively. One source of P-type transistor PM1 (e.g., the terminal facing the left) and one source of P-type transistor PM2 (e.g., the terminal facing upward) are coupled to the I / O pad 10 and the power supply voltage VCC18, respectively. One drain of P-type transistor PM1 and one drain of P-type transistor PM2 are coupled to one input terminal (e.g., the left terminal) and one output terminal (e.g., the upper terminal) of the level reduction device 112, respectively.

[0016] Additionally, the level reduction device 112 may include a diode-connected transistor, such as an N-type transistor NM1, coupled to the gate of the voltage detection and control circuit 111 and the first N-type transistor 21 (e.g., N-type transistor NM2), for performing the level reduction operation to generate the level reduction voltage as a self-control signal Va. A drain (e.g., the downward-facing terminal) and a gate of the N-type transistor NM1 are electrically connected to each other and coupled to the signal path (between the I / O pad 10 and the level reduction device 112), for example, through the signal path of the source and drain of the P-type transistor PM1, and a source (e.g., the upward-facing terminal) of the N-type transistor NM1 is coupled to the power path (between the power supply voltage VCC18 and the level reduction device 112), for example, through the power path of the source and drain of the P-type transistor PM2.

[0017] For example, when IO = 0 V, the relevant operation may include: (1) the first voltage detection and path control sub-circuit 1111 (or the P-type transistor PM1 within it) may close the signal path at the second time point according to the second voltage detection result to prevent the level reduction device 112 from performing the level reduction operation, and the second voltage detection and path control sub-circuit 1112 (or the P-type transistor PM2 within it) may open the power path at the second time point according to the second voltage detection result to generate a self-control signal Va according to the power supply voltage VCC; (2) the second voltage detection and path control sub-circuit 1112 (or the P-type transistor PM2 within it) may conduct the power supply voltage VCC18 (e.g., VCC18 = 1.8 V) to its lower terminal to generate a self-control signal Va, wherein the self-control signal Va may have a slight voltage drop compared to the power supply voltage VCC18; and (3) Under the control of the gate bias control circuit 110 based on voltage detection, when IO = 0 V, Vds2 = Vds3 = 0 V in the input tolerance I / O level offset 20, so there is no need to worry about reliability.

[0018] For example, when IO = 3.3 V, the relevant operation may include: (1) The first voltage detection and path control sub-circuit 1111 (or the P-type transistor PM1 within it) can open the signal path at the first time point according to the first voltage detection result, so as to allow the level down device 112 to perform the level down operation to generate the level down voltage as the self-control signal Va, and the second voltage detection and path control sub-circuit 1112 (or the P-type transistor PM2 within it) can close the power path at the first time point according to the first voltage detection result, so as to allow the level down device 112 to correctly output the level down voltage as the self-control signal Va, without being affected by the power supply voltage VCC; (2) The first voltage detection and path control sub-circuit 1111 (or the P-type transistor PM1 within it) and the level down device 112 (or the N-type transistor NM1 within it) can receive the voltage level IO (e.g., IO = 3.3 V). (V) The output terminal of the level reduction device 112 is turned on to generate the level reduction voltage as the self-control signal Va, wherein the intermediate signal on the input terminal of the level reduction device 112 can have a very small voltage drop compared to the received voltage level IO, which can be ignored, and the self-control signal Va can have a slight voltage drop compared to this intermediate signal, which is equal to Vtn, so the voltage level of the self-control signal Va can be regarded as equal to (3.3V - Vtn); and (3) Under the control of the gate bias control circuit 110 based on voltage detection, when IO = 3.3 V, in the input tolerance I / O level offset 20, Vds2 < 1.8 V and Vds3 < 1.8 V, there is no need to worry about reliability, wherein the voltage level of the intermediate signal Vb can be equal to (3.3V - (2 * The drain-to-source voltage Vtn can be equal to (2 * Vtn), and the drain-to-source voltage Vds3 (or Vds3) can be equal to (1.5V - Vtn). For example, the threshold voltage Vtn can be equal to 0.5V, but the present invention is not limited thereto. As long as it does not impede the implementation of the present invention, the threshold voltage Vtn can be equal to any value of various types, such as 0.3V, 0.5V, 0.7V, etc.

[0019] Based on the hardware architecture shown in Figure 4, the self-control signal Va is received as the gate bias voltage of the first N-type transistor 21 (e.g., N-type transistor NM2), and the input tolerance I / O level offset 20 is coupled to the voltage-sensing gate bias control circuit 110 to receive the self-control signal Va and operate according to the self-control signal Va, wherein the self-control signal Va is associated with the received voltage level I / O. Since the self-control signal Va is generated by the voltage-sensing gate bias control circuit 110 according to the received voltage level I / O, and not by any other circuit, the voltage-sensing gate bias control circuit 110 can operate automatically and independently. Therefore, the device 100 operated according to this method can operate smoothly without additional control, making the entire hardware architecture very compact and highly efficient.

[0020] According to certain embodiments, the hardware architecture shown in Figure 4 may be varied. For example, the transistor in the diode connection form may be implemented as a P-type transistor, wherein one drain and one gate of the P-type transistor are electrically connected to each other and coupled to the power path, and one source of the P-type transistor is coupled to the signal path.

[0021] The first voltage detection result at the first time point indicates that the received voltage level IO corresponds to the logic high state. The received voltage level IO may be equal to a predetermined voltage level VIO, such as 3.3 V (e.g., IO = 3.3 V). In particular, at the first time point, the power supply voltage VCC, for example, the power supply voltage VCC18, is less than the received voltage level IO. Figure 5 illustrates the normal voltage configuration of the multi-transistor architecture involved in the multi-transistor level offset control scheme shown in Figure 3 according to an embodiment of the present invention in its lower half, while Figure 5 illustrates the normal voltage configuration of the single-transistor architecture involved in the single-transistor level offset control scheme shown in Figure 2 in its upper half for better understanding. For the same conditions, for example, at an operating frequency of 150 MHz, with a process corresponding to PTNT, a normal voltage (NV) and a temperature of 25 degrees Celsius (°C): (1) The single-transistor architecture shown in the upper half of Figure 5 has a reliability problem with the normal voltage configuration, where Vds0 = Vds(MN0) = 2.0V > 1.8V; and (2) The multi-transistor architecture shown in the lower half of Figure 5 does not have a reliability problem with the normal voltage configuration, where Vb = (3.3V - (2 * Vtn)), so Vds2 = Vds(NM2) = (2 * Vtn) < 1.8V and Vds3 = Vds(NM3) = (1.5V - Vtn) < 1.8V.

[0022] To better understand, some implementation details can be further explained as follows. Multiple corner cases regarding process variation may include PTNT, PFNF, PSNS, PFNS, and PSNF (or TT, FF, SS, FS, and SF), any of which can be used to define the operating speed of the PMOSFET and NMOSFET, where "F" represents Fast, "T" represents Typical, and "S" represents Slow. Different combinations are possible in conjunction with voltage variations (e.g., from -10% to +10%) and temperature variations (e.g., from -40°C to 125°C). Common combinations include: (1) Typical Case (TC): TT, VCC, 25°C; (2) Worst Case (WC): SS, VCC with a -10% change, 125°C; and (3) Best Case (BC): FF, VCC with a +10% change, -40°C. For example, with VCC18 = 1.8V, NV is 1.8V. Theoretically, when VCC18 = 1.98V, there could be more serious reliability issues in a single-electrode transistor architecture.

[0023] Figure 6, in its lower half, illustrates the relevant signals of the normal voltage configuration of the multi-transistor architecture shown in the lower half of Figure 5 according to an embodiment of the present invention, while Figure 6, in its upper half, illustrates the relevant signals of the normal voltage configuration of the single-transistor architecture shown in the upper half of Figure 5 for better understanding. The horizontal axis represents time in nanoseconds (ns), and the vertical axis represents voltage in volts (V). As shown in the upper half of Figure 6, Vds0 > 1.8 V, indicating a potential reliability issue. As shown in the lower half of Figure 6, Vds2 < 1.8 V and Vds3 < 1.8 V, indicating no reliability issue.

[0024] Figure 7, in its lower half, illustrates the abnormal voltage configuration of the multi-transistor architecture involved in the multi-transistor level offset control scheme shown in Figure 3 according to an embodiment of the present invention, while Figure 7, in its upper half, illustrates the abnormal voltage configuration of the single-transistor architecture involved in the single-transistor level offset control scheme shown in Figure 2 for better understanding. Under the same conditions, for example, at an operating frequency of 150 MHz, a process corresponding to PTNT, a high voltage (HV) voltage, and a temperature of -40°C: (1) the abnormal voltage configuration of the single-transistor architecture shown in the upper half of Figure 7 has reliability issues, where Vds0 > 1.8 V; and (2) the abnormal voltage configuration of the multi-transistor architecture shown in the lower half of Figure 7 does not have reliability issues, where Vds2 < 1.8 V and Vds3 < 1.8 V.

[0025] Figure 8, in its lower half, illustrates the relevant signals of the abnormal voltage configuration of the multi-transistor architecture shown in the lower half of Figure 7 according to an embodiment of the present invention, while Figure 8, in its upper half, illustrates the relevant signals of the abnormal voltage configuration of the single-transistor architecture shown in the upper half of Figure 7 for better understanding. As shown in the upper half of Figure 8, the intermediate signal IOA can change significantly over time, for example, from the intermediate signal IOA_fresh corresponding to the time of new product manufacturing to the intermediate signal IOA_1.5_yr corresponding to 1.5 years later. This indicates a reliability problem, where the abnormal curve of the intermediate signal IOA_1.5_yr indicates that the N-type transistor NMO deteriorates after 1.5 years. As shown in the lower half of Figure 8, the intermediate signals Vb and IOA do not change significantly over time. For example, the intermediate signals Vb_fresh and IOA_fresh, which correspond to the time when the new product is manufactured, remain unchanged from the intermediate signals Vb_1.5_yr and IOA_1.5_yr, which correspond to the time 1.5 years later. This indicates that there will be no reliability issues.

[0026] Figure 9 illustrates the relevant signals of the abnormal voltage configuration of the multi-electric transistor architecture shown in the lower half of Figure 7 according to another embodiment of the present invention. As shown in Figure 9, the intermediate signals Vb and IOA do not change significantly over time, for example, from the intermediate signals Vb_fresh and IOA_fresh corresponding to the time of new product manufacturing to the intermediate signals Vb_10_yr and IOA_10_yr corresponding to a time 10 years later, respectively, which indicates that there will be no reliability issues.

[0027] Figure 10 illustrates a workflow of the method according to an embodiment of the present invention. The device 100 (or its components) can be operated according to the workflow shown in Figure 10.

[0028] In step S10, the voltage-detection-based gate bias control circuit 110 can perform voltage-detection-based gate bias control on the first N-type transistor 21 in the input tolerance I / O level offset 20. Step S10 may include multiple sub-steps such as steps S11 and S12.

[0029] In step S11, the voltage detection and control circuit 111 can perform a voltage detection operation (e.g., any of the above-mentioned voltage detection operations) on the received voltage level IO on the I / O pad 10 to generate a voltage detection result (e.g., the first voltage detection result or the second voltage detection result) for generating an automatic control signal Va corresponding to the voltage detection result to perform gate bias control, wherein the voltage detection result indicates whether the received voltage level IO corresponds to the logic high state or the logic low state.

[0030] In step S12, the level reduction device 112 may selectively perform a level reduction operation (e.g., the level reduction operation mentioned above) based on the voltage detection result (i.e., the voltage detection result just obtained in step S11) to generate a level reduction voltage (e.g., the level reduction voltage mentioned above) as a self-control signal Va based on the received voltage level IO, so as to control the gate bias voltage of the first N-type transistor 21.

[0031] In step S20, the device 100 can receive the self-control signal Va using the input tolerance I / O level offset 20 to operate according to the self-control signal Va. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0032] For better understanding, the method can be illustrated using the workflow shown in Figure 10, but the invention is not limited thereto. According to certain embodiments, one or more steps may be added, deleted, or modified in the workflow shown in Figure 10.

[0033] The method and apparatus 100 of the present invention can be applied to 28nm / 22nm / 14nm 3.3V bidirectional I / O and input receiver I / O via a 1.8V I / O device, and can be applied to bidirectional I / O and input receiver I / O with signal high voltage tolerance. Furthermore, the method and apparatus 100 of the present invention (especially the voltage-sensing-based gate bias control circuit 110 therein) can be widely used to solve the reliability problem of input receiver level offset, can be self-controlled from I / O pad signals (e.g., the received voltage level IO on I / O pad 10) and used for high-voltage tolerant input receivers, and utilizes the level reduction device 112 to generate a gate bias voltage for the first N-type transistor 21 (e.g., N-type transistor NM2, which can be implemented as an N-type MOSFET), wherein a lower gate bias voltage can better solve the input receiver level offset reliability problem. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention. [Simplified Explanation of the Diagram]

[0034] Figure 1 is a schematic diagram of a device for controlling a level offset as an input-tolerance I / O level offset according to an embodiment of the present invention, wherein the device can be operated according to a method for controlling a level offset as an input-tolerance I / O level offset. Figure 2 illustrates a single-transistor level offset control scheme. Figure 3 illustrates a multi-transistor level offset control scheme according to an embodiment of the present invention. Figure 4 illustrates the hardware architecture involved in the multi-transistor level offset control scheme shown in Figure 3 according to an embodiment of the present invention. Figure 5 shows the normal voltage configuration of the multi-transistor architecture involved in the multi-transistor level offset control scheme shown in Figure 3 according to an embodiment of the present invention in its lower half, and the normal voltage configuration of the single-transistor architecture involved in the single-transistor level offset control scheme shown in Figure 2 in its upper half for better understanding. Figure 6, in its lower half, illustrates the relevant signals of the normal voltage configuration of the multi-transistor architecture shown in the lower half of Figure 5 according to an embodiment of the present invention, while Figure 6, in its upper half, illustrates the relevant signals of the normal voltage configuration of the single-transistor architecture shown in the upper half of Figure 5 for better understanding. Figure 7, in its lower half, illustrates the abnormal voltage configuration of the multi-transistor architecture involved in the multi-transistor level offset control scheme shown in Figure 3 according to an embodiment of the present invention, while Figure 7, in its upper half, illustrates the abnormal voltage configuration of the single-transistor architecture involved in the single-transistor level offset control scheme shown in Figure 2 for better understanding. Figure 8, in its lower half, illustrates the relevant signals of the abnormal voltage configuration of the multi-transistor architecture shown in the lower half of Figure 7 according to an embodiment of the present invention, while Figure 8, in its upper half, illustrates the relevant signals of the abnormal voltage configuration of the single-transistor architecture shown in the upper half of Figure 7 for better understanding. Figure 9 illustrates the relevant signals of the abnormal voltage configuration of the multi-transistor architecture shown in the lower half of Figure 7 according to another embodiment of the present invention. Figure 10 illustrates a workflow of the method according to an embodiment of the present invention.

Claims

1. An apparatus for controlling a level shifter as an input tolerance input / output (I / O) level shifter, the input tolerance input / output level shifter being used to couple an input / output pad to a buffer circuit within an input receiver circuit to act as a sub-circuit of the input receiver circuit, the apparatus comprising: a voltage-detection-based gate bias control circuit for voltage-detection-based gate bias control of a first N-type transistor within the input tolerance input / output level shifter, wherein a second N-type transistor within the input tolerance input / output level shifter is coupled to the first N-type transistor, and a gate of the second N-type transistor is coupled to a power supply voltage, wherein the voltage-detection-based gate bias control circuit comprises: A voltage detection and control circuit, coupled to the input / output pad, is used to perform at least one voltage detection operation on a received voltage level on the input / output pad to generate at least one voltage detection result, which is used to generate a self-control signal corresponding to the at least one voltage detection result for gate bias control, wherein the at least one voltage detection result indicates whether the received voltage level corresponds to a logic high state or a logic low state; and a level-down device, coupled to the voltage detection and control circuit and a gate of the first N-type transistor, is used to selectively perform a level-down operation based on the at least one voltage detection result to generate a level-down voltage as the self-control signal, which is used to control the gate bias of the first N-type transistor.

2. The device as described in claim 1, wherein the voltage detection and control circuit comprises: a first voltage detection and path control sub-circuit coupled to the input / output pad, configured to selectively open a signal path between the input / output pad and the level reduction device based on the at least one voltage detection result, so as to allow the level reduction device to perform the level reduction operation to generate the level reduction voltage as the self-control signal; and a second voltage detection and path control sub-circuit coupled to the input / output pad, configured to selectively close a power path between the power supply voltage and an output terminal of the level reduction device based on the at least one voltage detection result, so as to allow the level reduction device to correctly output the level reduction voltage as the self-control signal without being affected by the power supply voltage.

3. The device as described in claim 2, wherein the at least one voltage detection result includes a first voltage detection result at a first time point, and the first voltage detection result indicates that the received voltage level corresponds to the logic high state, wherein: The first voltage detection and path control sub-circuit is used to open the signal path at the first time point based on the first voltage detection result, so as to allow the level down device to perform the level down operation to generate the level down voltage as the self-control signal; and the second voltage detection and path control sub-circuit is used to close the power path at the first time point based on the first voltage detection result, so as to allow the level down device to correctly output the level down voltage as the self-control signal without being affected by the power supply voltage.

4. The device as described in claim 3, wherein the at least one voltage detection result further includes a second voltage detection result at a second time point, and the second voltage detection result indicates that the received voltage level corresponds to the logic low state, wherein: The first voltage detection and path control sub-circuit is used to shut down the signal path at the second time point based on the second voltage detection result to prevent the level reduction device from performing the level reduction operation; and the second voltage detection and path control sub-circuit is used to turn on the power path at the second time point based on the second voltage detection result to generate the automatic control signal based on the power supply voltage.

5. The device as described in claim 2, wherein: The first voltage detection and path control subcircuit includes: a first switch coupled to the input / output pad, for selectively opening the signal path based on the at least one voltage detection result, so as to allow the level down device to perform the level down operation to generate the level down voltage as the self-control signal; and the second voltage detection and path control subcircuit includes: a second switch coupled to the input / output pad, for selectively closing the power path based on the at least one voltage detection result, so as to allow the level down device to correctly output the level down voltage as the self-control signal, without being affected by the power supply voltage.

6. The device as described in claim 5, wherein the first switch and the second switch are respectively implemented as a first P-type transistor and a second P-type transistor, wherein a gate of the first P-type transistor and a gate of the second P-type transistor are respectively coupled to the power supply voltage and the input / output pad, a source of the first P-type transistor and a source of the second P-type transistor are respectively coupled to the input / output pad and the power supply voltage, and a drain of the first P-type transistor and a drain of the second P-type transistor are respectively coupled to an input terminal and an output terminal of the level reduction device.

7. The device as described in claim 1, wherein the at least one voltage detection result includes a first voltage detection result at a first time point, and the first voltage detection result indicates that the received voltage level corresponds to the logic high state; and at the first time point, the power supply voltage is less than the received voltage level.

8. The device as described in claim 1, wherein the level reduction device comprises: a diode-connected transistor coupled to the voltage detection and control circuit and the gate of the first N-type transistor, for performing the level reduction operation to generate the level reduction voltage as the self-control signal.

9. The device as described in claim 8, wherein: The diode-connected transistor system is implemented as a third N-type transistor, wherein one drain and one gate of the third N-type transistor are electrically connected to each other and coupled to a signal path between the input / output pad and the level reduction device, and one source of the third N-type transistor is coupled to a power path between the power supply voltage and the level reduction device; or the diode-connected transistor system is implemented as a P-type transistor, wherein one drain and one gate of the P-type transistor are electrically connected to each other and coupled to the power path, and one source of the P-type transistor is coupled to the signal path.

10. The device as described in claim 1, wherein the self-control signal is received as the gate bias of the first N-type transistor, and the device further includes: an input tolerance input / output level offset coupled to the voltage-sensing gate bias control circuit for receiving the self-control signal and operating according to the self-control signal.

11. A method for controlling a level shifter as an input tolerance input / output (I / O) level shifter, the level shifter being used to couple an input / output pad to a buffer circuit within an input receiver circuit to act as a sub-circuit of the input receiver circuit, the method comprising: performing voltage-detection-based gate bias control on a first N-type transistor within the level shifter, wherein a second N-type transistor within the level shifter is coupled to the first N-type transistor, and a gate of the second N-type transistor is coupled to a power supply voltage, wherein performing the voltage-detection-based gate bias control on the first N-type transistor within the level shifter further comprises: At least one voltage sensing operation is performed on a received voltage level on the input / output pad to generate at least one voltage sensing result for generating a self-control signal corresponding to the at least one voltage sensing result to perform gate bias control, wherein the at least one voltage sensing result indicates whether the received voltage level corresponds to a logic high state or a logic low state; and based on the at least one voltage sensing result, a level-down operation is selectively performed to generate a level-down voltage based on the received voltage level as the self-control signal for controlling the gate bias of one of the first N-type transistors.

12. The method as described in claim 11, wherein a level-down device is used to perform the level-down operation; and the at least one voltage detection operation is performed on the received voltage level on the input / output pad to generate the at least one voltage detection result for generating the gate bias control corresponding to the at least one voltage detection result, further comprising: selectively opening a signal path between the input / output pad and the level-down device based on the at least one voltage detection result to allow the level-down device to perform the level-down operation to generate the level-down voltage as the control signal; and selectively closing a power path between the power supply voltage and an output terminal of the level-down device based on the at least one voltage detection result to allow the level-down device to correctly output the level-down voltage as the control signal without being affected by the power supply voltage.

13. The method as described in claim 12, wherein the at least one voltage detection result includes a first voltage detection result at a first time point, and the first voltage detection result indicates that the received voltage level corresponds to the logic high state, wherein: Selectively opening the signal path between the input / output pads and the level-down device based on the at least one voltage detection result, to allow the level-down device to perform the level-down operation to generate the level-down voltage as the self-control signal, further includes: opening the signal path at the first time point based on the first voltage detection result, to allow the level-down device to perform the level-down operation to generate the level-down voltage as the self-control signal; and selectively closing the power path between the power supply voltage and the output terminal of the level-down device based on the at least one voltage detection result, to allow the level-down device to correctly output the level-down voltage as the self-control signal without being affected by the power supply voltage, further includes: closing the power path at the first time point based on the first voltage detection result, to allow the level-down device to correctly output the level-down voltage as the self-control signal without being affected by the power supply voltage.

14. The method as described in claim 13, wherein the at least one voltage detection result further includes a second voltage detection result at a second time point, and the second voltage detection result indicates that the received voltage level corresponds to the logic low state, wherein: Selectively opening the signal path between the input / output pads and the level-down device based on the at least one voltage detection result to allow the level-down device to perform the level-down operation and generate the level-down voltage as the self-control signal further includes: closing the signal path at the second time point based on the second voltage detection result to prevent the level-down device from performing the level-down operation; and selectively closing the power path between the power supply voltage and the output terminal of the level-down device based on the at least one voltage detection result to allow the level-down device to correctly output the level-down voltage as the self-control signal without being affected by the power supply voltage further includes: opening the power path at the second time point based on the second voltage detection result to generate the self-control signal based on the power supply voltage.

15. The method as described in claim 12, wherein: Selectively opening the signal path between the input / output pads and the level-down device based on the at least one voltage detection result, to allow the level-down device to perform the level-down operation to generate the level-down voltage as the self-control signal, further includes: using a first switch to selectively open the signal path based on the at least one voltage detection result, to allow the level-down device to perform the level-down operation to generate the level-down voltage as the self-control signal; and selectively closing the power path between the power supply voltage and the output terminal of the level-down device based on the at least one voltage detection result, to allow the level-down device to correctly output the level-down voltage as the self-control signal without being affected by the power supply voltage, further includes: using a second switch to selectively close the power path based on the at least one voltage detection result, to allow the level-down device to correctly output the level-down voltage as the self-control signal without being affected by the power supply voltage.

16. The method as described in claim 15, wherein the first switch and the second switch are respectively implemented as a first P-type transistor and a second P-type transistor, wherein a gate of the first P-type transistor and a gate of the second P-type transistor are respectively coupled to the power supply voltage and the input / output pad, a source of the first P-type transistor and a source of the second P-type transistor are respectively coupled to the input / output pad and the power supply voltage, and a drain of the first P-type transistor and a drain of the second P-type transistor are respectively coupled to an input terminal and an output terminal of the level reduction device.

17. The method as described in claim 11, wherein the at least one voltage detection result includes a first voltage detection result at a first time point, and the first voltage detection result indicates that the received voltage level corresponds to the logic high state; and at the first time point, the power supply voltage is less than the received voltage level.

18. The method as described in claim 11, wherein a level-down device is used to perform the level-down operation; and the level-down device comprises: a diode-connected transistor coupled to the voltage detection and control circuit and a gate of the first N-type transistor, used to perform the level-down operation to generate the level-down voltage as the self-control signal.

19. The method as described in claim 18, wherein: The diode-connected transistor system is implemented as a third N-type transistor, wherein one drain and one gate of the third N-type transistor are electrically connected to each other and coupled to a signal path between the input / output pad and the level reduction device, and one source of the third N-type transistor is coupled to a power path between the power supply voltage and the level reduction device; or the diode-connected transistor system is implemented as a P-type transistor, wherein one drain and one gate of the P-type transistor are electrically connected to each other and coupled to the power path, and one source of the P-type transistor is coupled to the signal path.

20. The method as described in claim 11, wherein the self-control signal is received as the gate bias of the first N-type transistor, and the method further comprises: receiving the self-control signal using the input tolerance input / output level offset to operate according to the self-control signal.

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