Time-interleaved analog-to-digital converter and calibration method therefor
Patent Information
- Application Number
- TW114105814
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-17
- Publication Date
- 2026-09-01
- Estimated Expiration
- 2045-02-16
AI Technical Summary
Time-interleaved analog-to-digital converters (TIADCs) face performance issues due to manufacturing variations leading to inconsistent conversion times among sub-ADCs, necessitating calibration to improve accuracy and reduce power consumption.
A time-interleaved analog-to-digital converter (TIADC) with an ADC group, bit code correction circuit, and sub-ADC correction circuit, where asynchronous sub-ADCs generate completion signals to adjust conversion speeds based on control signals, using low-dropout regulators, comparators, and control circuits to synchronize operations.
Enhances TIADC performance by synchronizing sub-ADC operations, improving accuracy and reducing power consumption through adaptive speed adjustments.
Smart Images
Figure TWG2TA001073671_001 
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Abstract
Description
Technical Field
[0001] This invention relates to analog-to-digital converters (ADCs), and more particularly to time-interleaved analog-to-digital converters (TIADCs) and their calibration methods. Prior Technology
[0002] A TIADC comprises multiple sub-ADCs. Each sub-ADC samples the input signal using a sampling clock with the same frequency but a different phase, and generates its own digital output code as the output of the TIADC in turn. For example, when a TIADC contains four sub-ADCs (e.g., ADC1, ADC2, ADC3, and ADC4), these four sub-ADCs sample the input signal in the following order: ADC1→ADC2→ADC3→ADC4→ADC1→ADC2→…
[0003] Due to variations in manufacturing processes, voltage, and temperature, the time required for these sub-ADCs to complete one analog-to-digital conversion may differ. Therefore, it is necessary to adjust the operating speed of the sub-ADCs (i.e., calibrate the TIADC) to improve its performance (e.g., improve accuracy or reduce power consumption). Summary of the Invention
[0004] In view of the shortcomings of prior art, one object of the present invention is to provide a time-interleaved analog-to-digital converter and its correction method to improve the shortcomings of prior art.
[0005] One embodiment of the present invention provides a time-interleaved analog-to-digital converter (ADC). The time-interleaved ADC is used to convert an input signal to generate a digital output signal, and includes an ADC group, a bit code correction circuit, and a sub-analog-to-digital converter correction circuit. The ADC group includes a first asynchronous sub-analog-to-digital converter and a second asynchronous sub-analog-to-digital converter. The first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter convert the input signal at different times to generate a first digital output code and a second digital output code, respectively. Upon completing one ADC conversion operation, the first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter generate a first conversion completion signal and a second conversion completion signal, respectively. The bit code correction circuit is coupled to the ADC group and is used to correct one of the first digital output code and the second digital output code to obtain the digital output signal. A sub-analog-to-digital converter (ADC) correction circuit is coupled to the ADC group and the digit code correction circuit, and is used to generate a control signal based on the first conversion completion signal and the second conversion completion signal. At least one of the first asynchronous ADC and the second asynchronous ADC changes the speed of an analog-to-digital conversion operation according to the control signal.
[0006] Another embodiment of the present invention provides a calibration method for a time-interleaved analog-to-digital converter (ADC). The time-interleaved ADC includes a first asynchronous sub-analog-to-digital converter (AADC) and a second asynchronous sub-analog-to-digital converter (DAC). The first and second asynchronous sub-analog-to-digital converters convert an input signal at different time points to generate a first digital output code and a second digital output code, respectively. Upon completing an analog-to-digital conversion operation, the first and second asynchronous sub-analog-to-digital converters generate a first conversion completion signal and a second conversion completion signal, respectively. The method includes: generating a control signal based on the first and second conversion completion signals; and changing the speed of an analog-to-digital conversion operation of at least one of the first and second asynchronous sub-analog-to-digital converters based on the control signal.
[0007] The technical means embodied in the embodiments of the present invention can improve at least one of the disadvantages of the prior art, and therefore the present invention can improve the performance of TIADC compared with the prior art.
[0008] The features, implementation, and effects of this invention are described in detail below with reference to the accompanying drawings. Simple Explanation of the Diagram
[0009] Figure 1 is a functional block diagram of one embodiment of the TIADC of the present invention; Figure 2 is a functional block diagram of one embodiment of the sub-ADC of the present invention; Figure 3 is a waveform diagram of one embodiment of the operation timing of the sub-ADC of the present invention; Figure 4 is a functional block diagram of one embodiment of the sub-ADC correction circuit of the present invention; Figure 5 is a functional block diagram of another embodiment of the sub-ADC correction circuit of the present invention; Figure 6 shows an embodiment of the truth table of the present invention; Figure 7 is a flowchart of one embodiment of the TIADC calibration method of the present invention; Figure 8 is a flowchart of one embodiment of step S710 in Figure 7; Figure 9 is a flowchart of another embodiment of step S710 in Figure 7; Figure 10 shows the implementation details of one embodiment of step S720 in Figure 7; and Figure 11 is a detailed implementation of another embodiment of step S720 in Figure 7. Implementation
[0010] The technical terms used in the following description are based on the common terminology of this technical field. If this specification provides explanations or definitions for certain terms, the explanations or definitions in this specification shall prevail.
[0011] This invention discloses a TIADC and its calibration method. Since some components of the TIADC of this invention may be known individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the device invention. Furthermore, part or all of the calibration method of the TIADC of this invention can be in the form of software and / or firmware, and can be executed by the TIADC of this invention or its equivalent device. Without affecting the full disclosure and implementability of the method invention, the following description of the method invention will focus on the steps rather than the hardware.
[0012] Figure 1 is a functional block diagram of one embodiment of the TIADC of the present invention. The TIADC 100 includes an ADC group 110, a sub-ADC correction circuit 120, and a digital code correction circuit 130 coupled together. The sub-ADC correction circuit 120 and the digital code correction circuit 130 operate according to the system clock CK. The TIADC 100 converts the input signal Vin and generates a digital output signal Dout.
[0013] ADC group 110 is an asynchronous ADC, meaning that the time required for each sub-ADC (110_1, 110_2, ..., 110_m) to perform an analog-to-digital conversion operation is not fixed. ADC group 110 contains m sub-ADCs (including sub-ADC 110_1, sub-ADC 110_2, ..., sub-ADC 110_m, where m is an integer greater than or equal to 2). Sub-ADC 110_1 samples the input signal Vin and generates a digital output code D_1 and a conversion completion signal FLG_1. Sub-ADC 110_2 samples the input signal Vin and generates a digital output code D_2 and a conversion completion signal FLG_2. Sub-ADC 110_m samples the input signal Vin and generates a digital output code D_m and a conversion completion signal FLG_m. The conversion completion signal FLG_k indicates that the sub-ADC 110_k has completed a certain analog-to-digital conversion operation (e.g., the least significant bit (LSB) of the digital output code D_k has been generated) (1 ≦k ≦m). More specifically, in some embodiments, when all bits of the digital output code D_k are generated, the sub-ADC 110_k changes the value or level of the conversion completion signal FLG_k (e.g., from a low level to a high level).
[0014] The digital code correction circuit 130 corrects the digital output codes D_1, D_2, ... and D_m in sequence, and outputs the corrected digital output codes as the digital output signal Dout.
[0015] Because ADC group 110 is an asynchronous ADC, although sub-ADC 110_k is given a preset time (e.g., a fixed time) to perform analog-to-digital conversion, if sub-ADC 110_k completes the analog-to-digital conversion operation early, it will have a longer idle time (i.e., not in operation). Conversely, if the preset time is insufficient, sub-ADC 110_k will not be able to complete the analog-to-digital conversion operation within the preset time (i.e., sub-ADC 110_k will not change the value or level of the conversion completion signal FLG_k before the preset time ends).
[0016] Each sub-ADC (110_1, 110_2, ..., 110_m) operates according to its own sub-control signal (sub-control signal EN_1, sub-control signal EN_2, ..., sub-control signal EN_m). These sub-control signals are generated by the sub-ADC correction circuit 120.
[0017] Please refer to Figure 2, which is a functional block diagram of one embodiment of the sub-ADC of the present invention. The sub-ADC 110_k (1≦k≦m) includes a low-dropout regulator (LDO) 210, a conversion circuit 220, and a control circuit 230 that are coupled to each other.
[0018] Low-dropout regulator 210 provides operating voltage VD to conversion circuit 220 and / or control circuit 230. More specifically, the source of the operating voltage for switching capacitor-type digital-to-analog converter 222, comparator 224 and control circuit 230 (hereinafter referred to as the three target circuits) includes, but is not limited to, the following implementations: (1) the operating voltage of one of the three target circuits is operating voltage VD, while the operating voltages of the other two are not operating voltage VD (e.g., other power supply voltages in sub-ADC 110_k, or the system voltage of TIADC 100); (2) the operating voltage of two of the three target circuits is operating voltage VD, while the operating voltage of the other is not operating voltage VD; or (3) the operating voltages of all three target circuits are operating voltage VD.
[0019] Conversion circuit 220, controlled by control signal Ctrl from control circuit 230, converts input signal Vin into intermediate digital code Dx. Control circuit 230 generates control signal Ctrl based on its built-in counter and generates digital output code D_k based on multiple intermediate digital codes Dx. The analog-to-digital conversion operation of sub-ADC 110_k (or conversion circuit 220) can refer to the operation by which sub-ADC 110_k (or conversion circuit 220) determines all bits of the digital output code D_k.
[0020] When the sub-ADC 110_k is an asynchronous SAR ADC, the conversion circuit 220 includes a switched-capacitor DAC 222 and a comparator 224, while the control circuit 230 includes a successive-approximation register and logic circuitry (not shown). The operating voltage VD can be used as the power supply voltage for the comparator 224 or the logic circuitry. Each time a comparison operation is completed, the comparator 224 changes the value or level of the comparison completion signal Rdy (e.g., from low to high). The control circuit 230 generates an asynchronous clock (not shown) required for the sub-ADC 110_k to perform the analog-to-digital conversion operation based on the comparison completion signal Rdy. The control circuit 230 also controls the switching of multiple switches of the switched-capacitor DAC 222 to either turn on or off based on the current intermediate digit code Dx using the control signal Ctrl to generate the next intermediate digit code Dx. When the control circuit 230 has determined all bits of the digital output code D_k, the control circuit 230 issues a conversion completion signal FLG_k. The control circuit 230 can delay the asynchronous clock according to the sub-control signal EN_k. Generating an asynchronous clock based on the comparison completion signal Rdy is well known to those skilled in the art and will not be described further. Note that the asynchronous SAR ADC is for example only; the sub-ADC 110_k can also be other types of ADCs (e.g., a asynchronous pipeline analog-to-digital converter (pipeline ADC, also known as a piperined ADC)).
[0021] Please refer to Figure 3, which is a waveform diagram of one embodiment of the operating timing of the sub-ADCs of the present invention. The system clock CK (with period T) is the operating clock of TIADC 100. In the example of Figure 3, m=4, and the operating waveforms WF_1, WF_2, WF_3, and WF_4 correspond to sub-ADCs 110_1, 110_2, 110_3, and 110_4, respectively. That is, the timing of the sub-ADCs of ADC group 110 (i.e., the order in which analog-to-digital conversion operations are performed) is: sub-ADC 110_1 → sub-ADC 110_2 → sub-ADC 110_3 → sub-ADC 110_4 → sub-ADC 110_1 → ... The operating period of each sub-ADC is 4T.
[0022] Please refer to Figure 4, which is a functional block diagram of one embodiment of the sub-ADC correction circuit 120 of the present invention. The sub-ADC correction circuit 120 includes a logic circuit 410 and a D-type flip-flop 420 coupled to each other. The logic circuit 410 generates an indication signal FLG based at least on the conversion completion signal FLG_a[n] and the conversion completion signal FLG_b[n], wherein the suffix "[n]" represents the nth cycle. For example (see Figure 3), the sub-ADCs 110_1 to 110_4 generate conversion completion signals FLG_1[n] to FLG_4[n] respectively between time points t2 to t6 (the nth cycle), and generate conversion completion signals FLG_1[n+1] to FLG_4[n+1] respectively between time points t6 to t10 (the (n+1)th cycle). The D-type flip-flop 420 temporarily stores the indication signal FLG and outputs the indication signal FLG as a control signal ENX according to the system clock CK.
[0023] Please refer to Figures 1 through 4. In the embodiment shown in Figure 4, the conversion completion signal FLG_a[n] and the conversion completion signal FLG_b[n] can be any two of the conversion completion signals FLG_1 to FLG_m (2 ≦ m), and the sub-control signals EN_1 to EN_m are all equal to the control signal ENX (that is, the sub-ADCs 110_1 to 110_m are all controlled by the same control signal ENX). The following explanation uses m=4 as an example.
[0024] In some embodiments, the sub-ADC correction circuit 120 generates a control signal ENX based on the timing-adjacent sub-ADCs. For example, the conversion completion signal FLG_a[n] and the conversion completion signal FLG_b[n] can be the conversion completion signal FLG_1[n] and the conversion completion signal FLG_2[n], respectively, or the conversion completion signal FLG_4[n] and the conversion completion signal FLG_1[n], respectively.
[0025] In other embodiments, the sub-ADC correction circuit 120 generates a control signal ENX based on the timing-disadvantaged sub-ADCs, meaning that a third analog-to-digital conversion operation exists between the first analog-to-digital conversion operation (corresponding to the conversion completion signal FLG_a[n]) and the second analog-to-digital conversion operation (corresponding to the conversion completion signal FLG_b[n]). For example, the conversion completion signals FLG_a[n] and FLG_b[n] can be conversion completion signals FLG_1[n] and FLG_3[n] respectively (i.e., the third analog-to-digital conversion operation is performed by sub-ADC 110_2), or conversion completion signals FLG_2[n] and FLG_4[n] respectively (i.e., the third analog-to-digital conversion operation is performed by sub-ADC 110_3).
[0026] In other embodiments, the sub-ADC correction circuit 120 generates control signals ENX at different cycles based on different conversion completion signals. For example, conversion completion signals FLG_a[n] and FLG_b[n] are conversion completion signals FLG_1[n] and FLG_2[n], respectively, while conversion completion signals FLG_a[n+1] and FLG_b[n+1] are conversion completion signals FLG_3[n+1] and FLG_4[n+1], respectively.
[0027] In other embodiments, the sub-ADC correction circuit 120 generates a control signal ENX based on the conversion completion signals of all sub-ADCs in the ADC group 110. For example, the logic circuit 410 generates an indication signal FLG based on the conversion completion signals FLG_1, FLG_2, FLG_3, and FLG_4.
[0028] As described above, the control signal ENX can represent the overall operating speed of the ADC group 110, and the sub-ADC correction circuit 120 uses the control signal ENX to adjust all or some of the sub-ADCs. For example, when both the conversion completion signal FLG_a[n] and the conversion completion signal FLG_b[n] indicate that the analog-to-digital conversion operation of the corresponding sub-ADC is relatively slow (fast), the sub-ADC correction circuit 120 outputs a low (high) level control signal ENX to control all or some of the sub-ADCs of the ADC group 110 to accelerate (decelerate) the analog-to-digital conversion operation. When the analog-to-digital conversion operation is too slow, accelerating the analog-to-digital conversion operation can improve the accuracy of the TIADC 100. When the analog-to-digital conversion operation is too fast, decelerating the analog-to-digital conversion operation can reduce the overall power consumption of the TIADC 100. Please refer to Figure 2, this adjustment includes, but is not limited to, the following three embodiments.
[0029] (1) The low-dropout regulator 210 increases (decreases) the operating voltage VD based on the low (high) level sub-control signal EN_k (e.g., by generating multiple candidate voltages through voltage division techniques) to increase (decrease) the operating speed of the conversion circuit 220 and the control circuit 230, thereby increasing (decreasing) the overall operating speed of the sub-ADC 110_k.
[0030] (2) Comparator 224 increases (decreases) its operating current based on the low (high) level sub-control signal EN_k (e.g., by providing multiple current sources with different current values) to increase (decrease) its own operating speed, thereby increasing (decreasing) the overall operating speed of sub-ADC 110_k.
[0031] (3) The control circuit 230 reduces (increases) the delay time of the asynchronous clock according to the low (high) level sub-control signal EN_k (e.g., by providing multiple delay paths with different delay times) to increase (decrease) the overall operating speed of the sub-ADC 110_k. It should be noted that since the ADC group 110 is an asynchronous ADC, the clock period of the asynchronous clock is determined by the delay path in the control circuit 230.
[0032] Please refer to Figure 5, which is a functional block diagram of another embodiment of the sub-ADC correction circuit 120 of the present invention. The sub-ADC correction circuit 120 includes mutually coupled logic circuits 410, D-type flip-flops 420, and m logic circuits 510_1 to 510_m (which generate sub-control signals EN_1 to EN_m respectively). Logic circuit 510_k (1 ≦k ≦m) generates sub-control signal EN_k based on control signal ENX, conversion completion signal FLG_k[n], and conversion completion signal FLG_k[n+1].
[0033] Please refer to Figure 6, which shows an embodiment of the truth table 600 of the present invention, according to which logic circuits 510_1 to 510_m operate. In the example of Figure 6, when at least two of the control signal ENX, the conversion completion signal FLG_k[n], and the conversion completion signal FLG_k[n+1] are low (logic 0) (for example, columns 1, 2, 3, and 5 of the truth table 600 represent relatively slow overall operation speed of ADC group 110 and / or relatively slow operation speed of sub-ADC 110_k in at least one of two consecutive operation cycles), the sub-ADC correction circuit 120 outputs a low-level sub-control signal EN_k to control sub-ADC 110_k to perform analog-to-digital conversion operation at a speed greater than or equal to the current analog-to-digital conversion operation. Columns 4, 6, 7, and 8 of the truth table 600 represent the opposite meaning and will not be described further.
[0034] Compared to the embodiment in Figure 4, in the embodiment in Figure 5, the sub-ADC correction circuit 120 also adjusts the operating speed of the sub-ADC 110_k based on the conversion completion signal FLG_k of the sub-ADC 110_k itself, thereby achieving more precise adjustment.
[0035] In summary, because the sub-ADC correction circuit 120 can obtain indication signals FLG from more than two sub-ADCs in any one operating cycle (as shown in Figure 3, 4T), the sub-ADC correction circuit 120 can accumulate the data required for correction more quickly, so as to converge the correction of TIADC 100 faster and achieve the purpose of improving the performance of TIADC.
[0036] In addition to the aforementioned TIADC 100, this invention also discloses a corresponding TIADC calibration method. This method is performed by a front-end TIADC calibration circuit 120 or its equivalent. Figure 7 is a flowchart of one embodiment of this method, comprising the following steps.
[0037] Step S710: The sub-ADC correction circuit 120 generates a control signal based on the first conversion completion signal of the first sub-ADC and the second conversion completion signal of the second sub-ADC. For example, in the embodiment of FIG4, the sub-ADC correction circuit 120 can generate a control signal ENX based on the conversion completion signals FLG_1 and FLG_2. As another example, in the embodiment of FIG5, the sub-ADC correction circuit 120 can generate a sub-control signal EN_k based on the conversion completion signals FLG_1 and FLG_2.
[0038] Step S720: The sub-ADC correction circuit 120 changes the speed of analog-to-digital conversion operation of at least one of the first sub-ADC (e.g., sub-ADC 110_1) and the second sub-ADC (e.g., sub-ADC 110_2) according to the control signal.
[0039] Please refer to Figure 8, which is a flowchart of one embodiment of step S710 in Figure 7. The embodiment in Figure 8 corresponds to Figure 4 and includes the following steps.
[0040] Step S712: The logic circuit 410 generates an indication signal FLG based on the first conversion completion signal (e.g., conversion completion signal FLG_1) and the second conversion completion signal (e.g., conversion completion signal FLG_2).
[0041] Step S714: The D-type flip-flop 420 generates the control signal ENX according to the instruction signal FLG.
[0042] Please refer to Figure 9, which is a flowchart of another embodiment of step S710 in Figure 7. The embodiment in Figure 9 corresponds to Figure 5. In addition to step S712, the embodiment in Figure 9 also includes the following steps.
[0043] Step S716: The D-type flip-flop 420 temporarily stores the indication signal FLG.
[0044] Step S718: The logic circuit (e.g., logic circuit 510_1) generates the control signal (e.g., sub-control signal EN_1) based on the control signal ENX, the first conversion completion signal (e.g., conversion completion signal FLG_1[n]) and a third conversion completion signal (e.g., conversion completion signal FLG_1[n+1]).
[0045] Please refer to Figure 10, which is an implementation detail of one embodiment of step S720 in Figure 7, including the following steps.
[0046] Step S722: The sub-ADC correction circuit 120 adjusts the operating current of the comparator 224 through the control signal (e.g., control signal ENX or sub-control signal EN_k).
[0047] Please refer to Figure 11, which is an implementation detail of another embodiment of step S720 in Figure 7, including the following steps.
[0048] Step S724: Control circuit 230 delays the asynchronous clock according to the control signal (e.g., control signal ENX or sub-control signal EN_k). For example, the delay time can be changed by selecting different delay paths.
[0049] Since those skilled in the art can understand the implementation details and variations of the method invention through the disclosure of the apparatus invention in this case, to avoid redundancy, repeated descriptions are omitted here without affecting the disclosure requirements and implementability of the method invention. Please note that the shapes, sizes, and proportions of the elements in the aforementioned figures are merely illustrative and are intended for those skilled in the art to understand the invention, and are not intended to limit the invention. Furthermore, in some embodiments, the order of the steps mentioned in the aforementioned flowchart may be adjusted according to actual operation, and they may even be performed simultaneously or partially simultaneously.
[0050] Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the patent application in this specification.
[0051] 100: TIADC (Time Interleaved Analog-to-Digital Converter) 110: ADC Group 110_1, 110_2, 110_k, 110_m: Sub-ADCs (Analog-to-Digital Converters) 120: Sub-ADC correction circuit 130: Digital code correction circuit CK: System clock speed D_1, D_2, D_m, D_k: Digital output codes Dout: Digital output signal EN_1, EN_2, EN_m, EN_k: Sub-control signals FLG_1,FLG_2,FLG_m,FLG_k,FLG_a[n],FLG_b[n],FLG_1[n], FLG_1[n+1],FLG_k[n], FLG_k[n+1],FLG_m[n], FLG_m[n+1]: conversion completion signal Vin: Input signal 210: Low dropout voltage regulator 220: Conversion Circuit 222: Switching Capacitive Digital-to-Analog Converter 224: Comparator 230: Control Circuit Ctrl, ENX: Control signals Dx: Middle Digit Code Rdy: Comparison complete signal VD: Operating voltage T: Period t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15: Time points WF_1, WF_2, WF_3, WF_4: Operation waveforms 410: Logic Circuits 420: Type D flip-flop FLG: Indicator Signal 510_1, 510_k, 510_m: Logic circuits 600: Truth Table S710, S720, S712, S714, S716, S718, S722, S724: Steps
Claims
1. A time-interleaved analog-to-digital converter (ADC) for converting an input signal to generate a digital output signal, comprising: an analog-to-digital converter group including a first asynchronous sub-analog-to-digital converter and a second asynchronous sub-analog-to-digital converter, wherein, The first asynchronous sub-analog-to-digital converter (AADC) and the second asynchronous sub-analog-to-digital converter (DAC) convert the input signal at different times to generate a first digital output code and a second digital output code, respectively. Furthermore, the first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter generate a first conversion completion signal and a second conversion completion signal, respectively, upon completing an analog-to-digital conversion operation. A digit code correction circuit, coupled to the AADC group, is used to correct one of the first digital output code and the second digital output code to obtain the digital output signal. A sub-analog-to-digital converter correction circuit, coupled to the AADC group and the digit code correction circuit, is used to generate a control signal based on the first conversion completion signal and the second conversion completion signal. At least one of the first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter changes the speed of an analog-to-digital conversion operation according to the control signal. The sub-analog-to-digital converter correction circuit includes: a logic circuit for generating an indication signal based on the first conversion completion signal and the second conversion completion signal; and a flip-flop coupled to the logic circuit for generating the control signal based on the indication signal.
2. A time-interleaved analog-to-digital converter (ADC) for converting an input signal to generate a digital output signal, comprising: an analog-to-digital converter group including a first asynchronous sub-analog-to-digital converter and a second asynchronous sub-analog-to-digital converter, wherein, The first asynchronous sub-analog-to-digital converter (AADC) and the second asynchronous sub-analog-to-digital converter (DAC) convert the input signal at different times to generate a first digital output code and a second digital output code, respectively. Furthermore, the first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter generate a first conversion completion signal and a second conversion completion signal, respectively, upon completing an analog-to-digital conversion operation. A digit code correction circuit, coupled to the AADC group, is used to correct one of the first digital output code and the second digital output code to obtain the digital output signal. A sub-analog-to-digital converter correction circuit, coupled to the AADC group and the digit code correction circuit, is used to generate a control signal based on the first conversion completion signal and the second conversion completion signal. At least one of the first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter changes the speed of an analog-to-digital conversion operation according to the control signal. The sub-analog-to-digital converter correction circuit includes: a first logic circuit for generating an indication signal based on the first conversion completion signal and the second conversion completion signal; a flip-flop coupled to the first logic circuit for temporarily storing the indication signal; and a second logic circuit coupled to the flip-flop for generating the control signal based on the control signal, the first conversion completion signal, and a third conversion completion signal; wherein the first conversion completion signal and the third conversion completion signal are generated by the first asynchronous sub-analog-to-digital converter in two consecutive operating cycles.
3. A time-interleaved analog-to-digital converter as described in request item 2, wherein, The first asynchronous sub-analog-to-digital converter includes a comparator, and the sub-analog-to-digital converter correction circuit adjusts an operating current of the comparator through the control signal to change the speed of the analog-to-digital conversion operation of the first asynchronous sub-analog-to-digital converter.
4. A time-interleaved analog-to-digital converter (ADC) for converting an input signal to generate a digital output signal, comprising: an analog-to-digital converter group including a first asynchronous sub-analog-to-digital converter and a second asynchronous sub-analog-to-digital converter, wherein, The first asynchronous sub-analog-to-digital converter (AADC) and the second asynchronous sub-analog-to-digital converter (DAC) convert the input signal at different times to generate a first digital output code and a second digital output code, respectively. Furthermore, the first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter generate a first conversion completion signal and a second conversion completion signal, respectively, upon completing an analog-to-digital conversion operation. A digit code correction circuit, coupled to the AADC group, is used to correct one of the first digital output code and the second digital output code to obtain the digital output signal. A sub-analog-to-digital converter correction circuit, coupled to the AADC group and the digit code correction circuit, is used to generate a control signal based on the first conversion completion signal and the second conversion completion signal. At least one of the first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter changes the speed of an analog-to-digital conversion operation according to the control signal. The first asynchronous sub-analog-to-digital converter includes a comparator and a control circuit. After completing a comparison operation, the comparator generates a comparison completion signal. The control circuit generates an asynchronous clock based on the comparison completion signal. The control circuit delays the asynchronous clock based on the control signal to change the speed of the analog-to-digital conversion operation of the first asynchronous sub-analog-to-digital converter.
5. A time-interleaved analog-to-digital converter as described in request 4, wherein, The group of analog-to-digital converters further includes a third asynchronous sub-analog-to-digital converter and a fourth asynchronous sub-analog-to-digital converter, which operate sequentially.
6. A time-interleaved analog-to-digital converter as described in request item 4, wherein, The first asynchronous sub-analog-to-digital converter performs a first analog-to-digital conversion operation, the second asynchronous sub-analog-to-digital converter performs a second analog-to-digital conversion operation, and a third analog-to-digital conversion operation exists between the first analog-to-digital conversion operation and the second analog-to-digital conversion operation.
7. A time-interleaved analog-to-digital converter (ADC) for converting an input signal to generate a digital output signal, comprising: an analog-to-digital converter group including a first asynchronous sub-analog-to-digital converter and a second asynchronous sub-analog-to-digital converter, wherein, The first asynchronous sub-analog-to-digital converter (AADC) and the second asynchronous sub-analog-to-digital converter (DAC) convert the input signal at different times to generate a first digital output code and a second digital output code, respectively. Furthermore, the first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter generate a first conversion completion signal and a second conversion completion signal, respectively, upon completing an analog-to-digital conversion operation. A digit code correction circuit, coupled to the AADC group, is used to correct one of the first digital output code and the second digital output code to obtain the digital output signal. A sub-analog-to-digital converter correction circuit, coupled to the AADC group and the digit code correction circuit, is used to generate a control signal based on the first conversion completion signal and the second conversion completion signal. At least one of the first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter changes the speed of an analog-to-digital conversion operation according to the control signal. The first asynchronous sub-analog-to-digital converter operates in a continuous first cycle and a second cycle. The group of analog-to-digital converters further includes a third asynchronous sub-analog-to-digital converter and a fourth asynchronous sub-analog-to-digital converter. The third asynchronous sub-analog-to-digital converter and the fourth asynchronous sub-analog-to-digital converter respectively generate a third conversion completion signal and a fourth conversion completion signal. The sub-analog-to-digital converter correction circuit generates the control signal based on the first conversion completion signal and the second conversion completion signal in the first cycle, and generates the control signal based on the third conversion completion signal and the fourth conversion completion signal in the second cycle.
8. A calibration method for a time-interleaved analog-to-digital converter, the time-interleaved analog-to-digital converter comprising a first asynchronous sub-analog-to-digital converter and a second asynchronous sub-analog-to-digital converter, wherein, The first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter convert an input signal at different time points to generate a first digital output code and a second digital output code, respectively. Furthermore, the first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter generate a first conversion completion signal and a second conversion completion signal, respectively, upon completing an analog-to-digital conversion operation. The method includes: generating a control signal based on the first conversion completion signal and the second conversion completion signal; changing the speed of an analog-to-digital conversion operation of at least one of the first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter based on the control signal; generating an indication signal based on the first conversion completion signal and the second conversion completion signal; temporarily storing the indication signal; and generating the control signal based on the control signal, the first conversion completion signal, and a third conversion completion signal. The first conversion completion signal and the third conversion completion signal are generated by the first asynchronous sub-analog-to-digital converter in two consecutive operating cycles.
9. A calibration method for a time-interleaved analog-to-digital converter, the time-interleaved analog-to-digital converter comprising a first asynchronous sub-analog-to-digital converter and a second asynchronous sub-analog-to-digital converter, wherein, The first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter convert an input signal at different time points to generate a first digital output code and a second digital output code, respectively. Furthermore, the first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter generate a first conversion completion signal and a second conversion completion signal, respectively, upon completing an analog-to-digital conversion operation. The method includes: generating a control signal based on the first conversion completion signal and the second conversion completion signal; and changing the speed of an analog-to-digital conversion operation of at least one of the first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter based on the control signal. The first asynchronous sub-analog-to-digital converter includes a comparator and a control circuit. The comparator generates a comparison completion signal after completing a comparison operation, and the control circuit generates an asynchronous clock based on the comparison completion signal. The method further includes: The asynchronous clock is delayed according to the control signal to change the speed of the analog-to-digital conversion operation of the first asynchronous sub-analog-to-digital converter.
10. A calibration method for a time-interleaved analog-to-digital converter, the time-interleaved analog-to-digital converter comprising a first asynchronous sub-analog-to-digital converter and a second asynchronous sub-analog-to-digital converter, wherein, The first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter convert an input signal at different times to generate a first digital output code and a second digital output code, respectively. Furthermore, the first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter generate a first conversion completion signal and a second conversion completion signal, respectively, upon completing an analog-to-digital conversion operation. The method includes: generating a control signal based on the first conversion completion signal and the second conversion completion signal; and changing the speed of an analog-to-digital conversion operation of at least one of the first asynchronous sub-analog-to-digital converter and the second asynchronous sub-analog-to-digital converter based on the control signal. The first asynchronous sub-analog-to-digital converter operates in a continuous first cycle and a second cycle. The time-interleaved analog-to-digital converter further includes a third asynchronous sub-analog-to-digital converter and a fourth asynchronous sub-analog-to-digital converter. The third asynchronous sub-analog-to-digital converter and the fourth asynchronous sub-analog-to-digital converter respectively generate a third conversion completion signal and a fourth conversion completion signal. The correction method generates the control signal based on the first conversion completion signal and the second conversion completion signal in the first cycle, and generates the control signal based on the third conversion completion signal and the fourth conversion completion signal in the second cycle.