Multiplying digital-to-analog converter

Abstract

A multiplying digital-to-analog converter (MDAC) is provided. The MDAC has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, which respectively receive a first signal and a second signal. The main components include four capacitors, an analog-to-digital converter (including a fifth capacitor), a reference voltage generation circuit, an amplifier, and multiple switches. Each capacitor is connected according to nodes. The inverting and non-inverting inputs of the amplifier are respectively connected to the corresponding nodes, and the outputs are connected to the first and second output terminals. In the sampling phase, the first and second capacitors respectively sample the input signals, and one end of the fifth capacitor has a voltage substantially equal to the voltage at the related node. In the amplification phase, the MDAC performs an amplification operation and outputs the corresponding signals.

Description

Technical Field

[0001] This invention relates to a pipeline analog-to-digital converter (ADC), and more particularly to a multiplying digital-to-analog converter (MDAC) of a pipeline analog-to-digital converter. Prior Technology

[0002] Please refer to Figure 1, which is a circuit diagram of a conventional multiplication-to-analog converter (hereinafter referred to as MDAC). MDACs are commonly used in pipelined analog-to-digital converters. The MDAC 100 has input terminals INp, INn, OUTp, and OUTn, and includes a sub-analog-to-digital converter (ADC) 110, a reference voltage generation circuit 120, an operational amplifier 130, switches SWp1, SWp2, SWp3, SWp4, SWp5, SWn1, SWn2, SWn3, SWn4, SWn5, capacitors Cp1, Cp2, Cn1, and Cn2. The MDAC 100 samples and amplifies the input signals Vip and Vin, and then outputs the output signals Vop and Von. The operating principle of the MDAC 100 is well known to those skilled in the art and will not be described further. Vcm is the DC voltage.

[0003] Sub-ADC 110 is designed to generate a digital code Dp (digital code Dn) based on the terminal voltage of capacitor Cp1 (capacitor Cp2), and the reference voltage generation circuit 120 then provides a corresponding reference voltage Vrp (reference voltage Vrn) to capacitor Cp1 (capacitor Cn1) based on the digital code Dp (digital code Dn). In other words, the reference voltage Vrp (reference voltage Vrn) is closely related to the terminal voltage of capacitor Cp1 (capacitor Cn1). However, the first sampling path (between input terminal INp and capacitor Cp1 or between input terminal INn and capacitor Cn1) and the second sampling path (between input terminal INp and sub-ADC 110 or between input terminal INn and sub-ADC 110) have random or systematic mismatches in resistance and capacitance values. This can cause the digital codes Dp and Dn to fail to accurately reflect the terminal voltages of capacitors Cp1 and Cp2, resulting in reduced performance or even errors in the MDAC 100. Summary of the Invention

[0004] In view of the shortcomings of prior art, one object of the present invention is to provide a multiplication digital-to-analog converter to improve upon the shortcomings of prior art.

[0005] One embodiment of the present invention provides a multiplication-to-analog converter. The multiplication-to-analog converter has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal and the second input terminal respectively receive a first input signal and a second input signal. The multiplication-to-analog converter includes: a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, an analog-to-digital converter, a reference voltage generation circuit, an amplifier, and a plurality of switches. The two ends of the first capacitor are respectively a first node and a second node. The two ends of the second capacitor are respectively a third node and a fourth node. The two ends of the third capacitor are respectively the second node and a fifth node. The two ends of the fourth capacitor are respectively the fourth node and a sixth node. The analog-to-digital converter includes a fifth capacitor and is used to generate a digital code. The reference voltage generation circuit is coupled to the analog-to-digital converter and is used to generate a reference voltage based on the digital code. The amplifier has an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal. The inverting input is coupled to the fourth node. The non-inverting input is coupled to the second node. The inverting output is coupled to the first output. The non-inverting output is coupled to the second output. The switches are coupled to the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the analog-to-digital converter, the reference voltage generation circuit, and the amplifier. In a sampling phase, the first capacitor and the second capacitor sample the first input signal and the second input signal, respectively. In an amplification phase, the multiplicative analog-to-digital converter performs an amplification operation to output a first output signal and a second output signal from the first output and the second output, respectively. In the sampling phase, a first voltage at one end of the fifth capacitor is substantially equal to a second voltage at the second node or the fourth node.

[0006] Another embodiment of the present invention provides a multiplication-digital-analog converter. The multiplication-digital-analog converter has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal and the second input terminal respectively receive a first input signal and a second input signal. The multiplication-digital-analog converter includes: a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, an analog-to-digital converter, a reference voltage generation circuit, an amplifier, and a plurality of switches. The two ends of the first capacitor are respectively a first node and a second node. The two ends of the second capacitor are respectively a third node and a fourth node. The two ends of the third capacitor are respectively the second node and a fifth node. The two ends of the fourth capacitor are respectively the fourth node and a sixth node. The analog-to-digital converter includes a fifth capacitor and is used to generate a digital code. The reference voltage generation circuit is coupled to the analog-to-digital converter and is used to generate a reference voltage based on the digital code. The amplifier has an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal. The inverting input is coupled to the fourth node. The non-inverting input is coupled to the second node. The inverting output is coupled to the first output. The non-inverting output is coupled to the second output. The switches are coupled to the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the analog-to-digital converter, the reference voltage generation circuit, and the amplifier. In a sampling phase, the first capacitor and the second capacitor sample the first input signal and the second input signal, respectively. In an amplification phase, the multiplicative analog-to-digital converter performs an amplification operation to output a first output signal and a second output signal from the first output and the second output, respectively. In the sampling phase, the first capacitor or the second capacitor samples the first input signal or the second input signal earlier than the fifth capacitor.

[0007] Another embodiment of the present invention provides a multiplication-to-analog converter. The multiplication-to-analog converter has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal and the second input terminal respectively receive a first input signal and a second input signal. The multiplication-to-analog converter includes: a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, an analog-to-digital converter, a reference voltage generation circuit, an amplifier, a first switch, a second switch, and a third switch. The two ends of the first capacitor are respectively a first node and a second node. The two ends of the second capacitor are respectively a third node and a fourth node. The two ends of the third capacitor are respectively the second node and a fifth node. The two ends of the fourth capacitor are respectively the fourth node and a sixth node. The analog-to-digital converter includes a fifth capacitor and is used to generate a digital code. The reference voltage generation circuit is coupled to the analog-to-digital converter and is used to generate a reference voltage based on the digital code. The amplifier has an inverting input, a non-inverting input, an inverting output, and a non-inverting output. The inverting input is coupled to the fourth node. The non-inverting input is coupled to the second node. The inverting output is coupled to the first output. The non-inverting output is coupled to the second output. A first switch is coupled between the first input and the first capacitor. A second switch is coupled between the second input and the second capacitor. A third switch is coupled between one end of the fifth capacitor and either the first or the third node. In a sampling phase, the first and second capacitors sample the first and second input signals, respectively. In an amplification phase, the multiplicative analog-to-digital converter performs an amplification operation to output a first output signal and a second output signal from the first and second outputs, respectively. The first and second switches change from non-conducting to conducting at the start of the sampling phase, while the third switch changes from non-conducting to conducting after the start of the sampling phase.

[0008] The technical means embodied in the embodiments of the present invention can improve at least one of the disadvantages of the prior art. Therefore, the present invention can improve performance and reduce errors compared to the prior art.

[0009] The features, implementation, and effects of this invention are described in detail below with reference to the accompanying drawings. Simple Explanation of the Diagram

[0010] Figure 1 is a circuit diagram of a conventional MDAC; Figure 2 is a circuit diagram of one embodiment of the MDAC of the present invention; Figure 3 is a circuit diagram of one embodiment of the sub-ADC of the present invention; Figure 4 is a waveform diagram of one embodiment of the multiple clocks of the present invention; Figure 5 is a waveform diagram of another embodiment of the multiple clocks of the present invention; Figure 6 is a waveform diagram of another embodiment of the multiple clocks of the present invention; Figure 7 is a waveform diagram of another embodiment of the multiple clocks of the present invention; Figure 8 is a circuit diagram of one embodiment of the MDAC of the present invention; and Figure 9 is a circuit diagram of one embodiment of the MDAC of the present invention. Implementation

[0011] The technical terms used in the following description are based on the common terminology of this technical field. If this specification provides explanations or definitions for certain terms, the explanations or definitions in this specification shall prevail.

[0012] The disclosure of this invention includes a multiplication-digit analog-to-digital converter. Since some components of the multiplication-digit analog-to-digital converter of this invention may be known individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the device invention.

[0013] In the following description, a high level indicates an active signal, and a low level indicates an inactive signal. Enabling / disabling a signal means raising / lowering the signal's level. However, this is merely an implementation or illustrative example and is not intended to limit the invention. In other words, in different implementations, a high level may represent inactive, and a low level may represent active, while enabling / disabling a signal may represent lowering / highering the signal's level. Level transitions or logical level transitions represent a signal changing from enabled (active) to disabled (inactive), or vice versa.

[0014] Please refer to Figure 2, which is a circuit diagram of one embodiment of the MDAC 200 of the present invention. The MDAC 200 has input terminals INp, INn, OUTp, and OUTn, and includes a sub-ADC 210, a reference voltage generation circuit 120, an amplifier 230 (e.g., an operational amplifier), capacitors Cp1, Cp2, Cn1, and Cn2, switches SWp1~SWp8, and switches SWn1~SWn8. Input terminals INp and INn receive input signals Vip and Vin, respectively. The reference voltage generation circuit 120 in Figure 2 is the same as the reference voltage generation circuit 120 in Figure 1.

[0015] The two ends of capacitor Cp1 are nodes Np1 and Np2, respectively. The two ends of capacitor Cp2 are nodes Np2 and Np3, respectively. The two ends of capacitor Cn1 are nodes Nn1 and Nn2, respectively. The two ends of capacitor Cn2 are nodes Nn2 and Nn3, respectively.

[0016] The non-inverting input terminal of amplifier 230 is coupled or electrically connected to node Np2; the inverting input terminal of amplifier 230 is coupled or electrically connected to node Nn2; the inverting output terminal of amplifier 230 is coupled or electrically connected to output terminal OUTp; the non-inverting output terminal of amplifier 230 is coupled or electrically connected to output terminal OUTn.

[0017] One end of switch SWp1 (SWn1) is coupled to or electrically connected to input terminal INp (INn); the other end of switch SWp1 (SWn1) is coupled to or electrically connected to node Np3 (Nn3).

[0018] One end of switch SWp2 (SWn2) is coupled or electrically connected to the input terminal INp (INn); the other end of switch SWp2 (SWn2) is coupled or electrically connected to node Np1 (Nn1).

[0019] One end of switch SWp3 (SWn3) is coupled or electrically connected to node Np3 (Nn3); the other end of switch SWp3 (SWn3) is coupled or electrically connected to output terminal OUTp (OUTn).

[0020] One end of switch SWp4 (SWn4) is coupled or electrically connected to reference voltage generating circuit 120; the other end of switch SWp4 (SWn4) is coupled or electrically connected to node Np1 (Nn1).

[0021] One end of switch SWp5 (SWn5) receives DC voltage Vcm1; the other end of switch SWp5 (SWn5) is coupled to or electrically connected to node Np2 (Nn2).

[0022] One end of switch SWp6 (SWn6) is coupled or electrically connected to ADC 210; the other end of switch SWp6 (SWn6) is coupled or electrically connected to node Np1 (Nn1).

[0023] One end of switch SWp7 (SWn7) is coupled or electrically connected to node ADC 210; the other end of switch SWp7 (SWn7) is coupled or electrically connected to node Np2 (Nn2).

[0024] One end of switch SWp8 (SWn8) is coupled or electrically connected to ADC 210; the other end of switch SWp8 (SWn8) receives DC voltage Vcm2.

[0025] The DC voltage Vcm1 may or may not be equal to the DC voltage Vcm2. In some embodiments, the input signals Vip and Vin are a differential signal pair, the output signals Vop and Von are a differential signal pair, and the DC voltages Vcm1 and Vcm2 are the common-mode voltages of the input signals Vip and Vin and / or the common-mode voltages of the output signals Vop and Von.

[0026] Please refer to Figure 3, which is a circuit diagram of one embodiment of the sub-ADC 210 of the present invention. The sub-ADC 210 includes capacitor Csp, capacitor Csn, quantizer 212, and quantizer 214. The sub-ADC 210 is used to generate digital codes Dp and Dn. The reference voltage generation circuit 120 can generate a reference voltage Vrp (reference voltage Vrn) based on the digital code Dp (digital code Dn).

[0027] The two ends of capacitor Csp are nodes Np4 and Np5, respectively. The two ends of capacitor Csn are nodes Nn4 and Nn5, respectively.

[0028] One end of switch SWp6 is coupled or electrically connected to node Np4. One end of switch SWp7 is coupled or electrically connected to node Np5. One end of switch SWp8 is coupled or electrically connected to node Np4.

[0029] One end of switch SWn6 is coupled to or electrically connected to node Nn4. One end of switch SWn7 is coupled to or electrically connected to node Nn5. One end of switch SWn8 is coupled to or electrically connected to node Nn4.

[0030] When switch SWp6 (SWn6) is turned on, the voltage at node Np4 (Nn4) is essentially equal to the voltage at node Np1 (Nn1). When switch SWp7 (SWn7) is turned on, the voltage at node Np5 (Nn5) is essentially equal to the voltage at node Np2 (Nn2).

[0031] The input terminals of quantizer 212 and quantizer 214 are nodes Np5 and Nn5, respectively. Node Np4 is not an input terminal of quantizer 212. Node Nn4 is not an input terminal of quantizer 214.

[0032] Please refer to Figure 4, which is a waveform diagram of one embodiment of the multiple clocks of the present invention. The MDAC 200 operates according to clocks CLK1, CLK2, and CLK3 of Figure 4. Between the falling edge of clock CLK1 and the rising edge of clock CLK2 (e.g., between time points t1 and t2, t3 and t4, ...), clock CLK3 is at a first level (e.g., a high level). Clock CLK3 is at a second level (e.g., a low level) at other times.

[0033] When pulse CLK1 is at the first level, the MDAC 200 operates in the sampling phase Φs. During sampling phase Φs, switches SWp1, SWn1, SWp2, SWn2, SWp5, SWn5, SWp6, SWn6, SWp7, and SWn7 are turned on, while other switches are turned off. This causes capacitors Cp1 and Cp2 to sample the input signal Vip, while capacitors Cn1 and Cn2 sample the input signal Vin. When pulse CLK1 is at the second level (i.e., sampling phase Φs ends), switches SWp1, SWn1, SWp2, SWn2, SWp5, SWn5, SWp6, SWn6, SWp7, and SWn7 are turned off.

[0034] When clock CLK2 is at the first level, the MDAC 200 operates in the amplification stage Φh. During amplification stage Φh, switches SWp3, SWn3, SWp4, and SWn4 are turned on, while other switches are turned off, causing the MDAC 200 to amplify and output signals Vop and Von from output terminals OUTp and OUTn, respectively. When clock CLK2 is at the second level (i.e., the amplification stage Φh ends), switches SWp3, SWn3, SWp4, and SWn4 are turned off.

[0035] When clock CLK3 is at the first level, MDAC 200 operates in the latch stage Φt. In the latch stage Φt, switches SWp8 and SWn8 are turned on, while other switches are turned off. This allows quantizer 212 to quantize the voltage across capacitor Csp (which is essentially equal to the voltage across capacitor Cp1) to generate the digital code Dp, and quantizer 214 to quantize the voltage across capacitor Csn (which is essentially equal to the voltage across capacitor Cn1) to generate the digital code Dn. In other words, since the voltage across capacitor Csp (capacitor Csn) is essentially equal to the voltage across capacitor Cp1 (capacitor Cn1), quantizer 212 (quantizer 214) essentially generates the digital code Dp (digital code Dn) based on the terminal voltage of capacitor Cp1 (capacitor Cn1).

[0036] Therefore, since the sub-ADC 210 essentially quantizes the voltage across capacitor Cp1 and the voltage across capacitor Cn1, the digital codes Dp and Dn can correctly reflect the voltages across capacitors Cp1 and Cn1. In other words, the impedance mismatch problem that occurs in the MDAC 100 will not occur in the MDAC 200.

[0037] Since the capacitance of capacitor Csp (capacitor Csn) is less than that of capacitor Cp1 (capacitor Cn1), the above operation will not significantly change the voltage stability behavior of capacitor Cp1 (capacitor Cn1).

[0038] Please refer to Figure 5, which is a waveform diagram of another embodiment of the multiple clocks of the present invention. The rising edge of clock CLK1d lags behind the rising edge of clock CLK1 by a time difference Δt, while the falling edge of clock CLK1d is aligned with the falling edge of clock CLK1. In this embodiment, switches SWp6, SWn6, SWp7, and SWn7 operate according to clock CLK1d. That is, switches SWp6, SWn6, SWp7, and SWn7 only change from non-conducting to conducting after the sampling phase Φs begins, so that capacitors Cp1 and Cn1 sample the input signal Vip or input signal Vin earlier than capacitors Csp and Csn. This operation ensures that capacitors Csp and Csn are connected in parallel with capacitors Cp1 and Cn1 respectively only after the terminal voltages of capacitors Cp1 and Cp2 have stabilized.

[0039] Please refer to Figure 6, which is a waveform diagram of another embodiment of the multiple clocks of the present invention. The rising edge of clock CLK1a is aligned with the rising edge of clock CLK1, but the falling edge of clock CLK1a precedes the falling edge of clock CLK1 by a time difference Δt'. Switches SWp1, SWn1, SWp2, SWn2, SWp6, and SWn6 operate according to clock CLK1, while switches SWp5, SWn5, SWp7, and SWn7 operate according to clock CLK1a. In other words, the time point when switches SWp5, SWn5, SWp7, and SWn7 change from being on to being off is earlier than the time point when switches SWp1, SWn1, SWp2, SWn2, SWp6, and SWn6 change from being on to being off (corresponding to the end of the sampling phase Φs, for example, time point t1 or time point t3). This can improve the stability of the circuit.

[0040] Please refer to Figure 7, which is a waveform diagram of another embodiment of the multiple clocks of the present invention (clock CLK3 is omitted in Figure 7). The falling edge of clock CLK1ad is aligned with the falling edge of clock CLK1a, but the rising edge of clock CLK1ad lags behind the rising edge of clock CLK1a by a time difference Δt''. Switches SWp1, SWn1, SWp2, SWn2, SWp6, and SWn6 operate according to clock CLK1, switches SWp5 and SWn5 operate according to clock CLK1a, and switches SWp7 and SWn7 operate according to clock CLK1ad. In other words, the time point at which switches SWp1, SWn1, SWp2, SWn2, SWp6, SWn6, SWp5, and SWn5 change from non-conducting to conducting is earlier than the time point at which switches SWp7 and SWn7 change from non-conducting to conducting.

[0041] Please refer to Figure 8, which is a circuit diagram of one embodiment of the MDAC 800 of the present invention. The MDAC 800 is similar to the MDAC 200, except that one end of switch SWp7 (SWn7) is not coupled to or electrically connected to node Np2 (Nn2), but instead receives a DC voltage Vcm2. In the embodiment of Figure 8, switches SWp7 and SWp5 are substantially simultaneously on or simultaneously off, while switches SWn7 and SWn5 are substantially simultaneously on or simultaneously off. For example, switches SWp5, SWn5, SWp7, and SWn7 all operate according to clock CLK1 or clock CLK1a.

[0042] Please refer to Figure 9, which is a circuit diagram of one embodiment of the MDAC 900 of the present invention. The MDAC 900 is similar to the MDAC 200, except that one end of switch SWp6 (SWn6) is not coupled to or electrically connected to node Np1 (Nn1), but instead receives the input signal Vip (Vin). In the embodiment of Figure 9, switches SWp6 and SWn6 operate according to clock CLK1 or clock CLK1d.

[0043] In the embodiments of Figures 8 and 9, because the terminal voltages of capacitors Csp and Csn can still adequately reflect at least one terminal voltage of capacitor Cp1 or capacitor Cn1, MDAC 800 and MDAC 900 can still avoid the problems encountered in the prior art.

[0044] Please note that the shapes, sizes, and proportions of the components in the aforementioned illustrations are merely illustrative and intended for those skilled in the art to understand the invention, and are not intended to limit the invention.

[0045] Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the patent application in this specification.

[0046] 100, 200, 800, 900: Multiplication Digit-to-Analog Converter 110, 210: Sub-analog digitizers 120: Reference voltage generation circuit 130: Operational amplifier Cn1, Cn2, Cp1, Cp2, Csn, Csp: Capacitors Dn, Dp: Digital code INn, INp: Input terminals OUTn, OUTp: Output terminals SWn1, SWn2, SWn3, SWn4, SWn5, SWp1, SWp2, SWp3, SWp4, SWp5, SWn6, SWn7, SWn8, SWp6, SWp7, SWp8: Switches Vcm, Vcm1, Vcm2: DC voltage Vin,Vip: Input signal Von, Vop: Output signal Vrn, Vrp: Reference voltages 230: Amplifier Nn1, Nn2, Nn3, Np1, Np2, Np3, Nn4, Nn5, Np4, Np5: Nodes 212, 214: Quantizers CLK1, CLK2, CLK3, CLK1d, CLK1a, CLK1ad: Clock speed t1, t2, t3, t4: Time points Φh: Scale-up stage Φs: Sampling stage Φt: Latching phase t,Δt',Δt'': Time difference

Claims

1. A multiplication-digital-to-analog converter, having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal and the second input terminal respectively receive a first input signal and a second input signal, the multiplication-digital-to-analog converter comprising: a first capacitor, wherein, The first capacitor has a first node and a second node at its two ends; a second capacitor, wherein the two ends of the second capacitor are a third node and a fourth node at its two ends; a third capacitor, wherein the two ends of the third capacitor are the second node and a fifth node at its two ends; a fourth capacitor, wherein the two ends of the fourth capacitor are the fourth node and a sixth node at its two ends; an analog-to-digital converter including a fifth capacitor and used to generate a digit code; and a reference voltage generation circuit coupled to the analog-to-digital converter, used to generate a reference voltage based on the digit code. An amplifier has an inverting input, a non-inverting input, an inverting output, and a non-inverting output, wherein the inverting input is coupled to a fourth node, the non-inverting input is coupled to a second node, the inverting output is coupled to a first output, and the non-inverting output is coupled to a second output; and a plurality of switches are coupled to a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, an analog-to-digital converter, a reference voltage generation circuit, and the amplifier; wherein, in a sampling phase, the first capacitor and the second capacitor sample the first input signal and the second input signal, respectively; in an amplification phase, the multiplicative analog-to-digital converter performs an amplification operation to output a first output signal and a second output signal from the first output and the second output, respectively; and, in the sampling phase, a first voltage at one end of a fifth capacitor is substantially equal to a second voltage at the second node or the fourth node.

2. As in request item 1, a multiplication-to-analog converter, wherein, The switches include: a first switch coupled between the first input terminal and the first capacitor; a second switch coupled between the second input terminal and the second capacitor; and a third switch coupled between the terminal of the fifth capacitor and the second node or the fourth node; wherein the first switch and the second switch change from being on to being off at the end of the sampling phase, and the third switch changes from being on to being off before the end of the sampling phase.

3. As in request item 1, a multiplication-to-analog converter, wherein, During this sampling phase, the first capacitor or the second capacitor samples the first input signal or the second input signal earlier than the fifth capacitor.

4. As in request item 1, a multiplication-to-analog converter, wherein, The switches include: a first switch coupled between the first input terminal and the first capacitor; a second switch coupled between the second input terminal and the second capacitor; and a third switch coupled between the other end of the fifth capacitor and the first node or the third node; wherein the first switch and the second switch change from non-conducting to conducting at the start of the sampling phase, and the third switch changes from non-conducting to conducting after the start of the sampling phase.

5. As in request item 4, a multiplication-to-analog converter, wherein, The analog-to-digital converter further includes: a quantizer, coupled to the fifth capacitor, for generating the digital code; wherein the other end is not an input of the quantizer.

6. The multiplication-to-analog converter of claim 1 further includes: a switch coupled between the other end of the fifth capacitor and a DC voltage; wherein, Between the sampling phase and the amplification phase, the switch is turned on and the analog-to-digital converter generates the digital code.

7. A multiplication-to-analog converter as described in request item 6, wherein, The analog-to-digital converter further includes: a quantizer, coupled to the fifth capacitor, for generating the digital code; wherein the other end is not an input of the quantizer.

8. A multiplication-to-analog converter as described in request item 1, wherein, The analog-to-digital converter further includes: a quantizer coupled to the fifth capacitor for generating the digital code; wherein the terminal is an input terminal of the quantizer.

9. A multiplication-digital-to-analog converter, having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal and the second input terminal respectively receive a first input signal and a second input signal, the multiplication-digital-to-analog converter comprising: a first capacitor, wherein, The first capacitor has a first node and a second node at its two ends; a second capacitor, wherein the two ends of the second capacitor are a third node and a fourth node at its two ends; a third capacitor, wherein the two ends of the third capacitor are the second node and a fifth node at its two ends; a fourth capacitor, wherein the two ends of the fourth capacitor are the fourth node and a sixth node at its two ends; an analog-to-digital converter including a fifth capacitor and used to generate a digit code; and a reference voltage generation circuit coupled to the analog-to-digital converter, used to generate a reference voltage based on the digit code. An amplifier has an inverting input, a non-inverting input, an inverting output, and a non-inverting output, wherein the inverting input is coupled to a fourth node, the non-inverting input is coupled to a second node, the inverting output is coupled to a first output, and the non-inverting output is coupled to a second output; and a plurality of switches are coupled to a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, an analog-to-digital converter, a reference voltage generation circuit, and the amplifier; wherein, in a sampling phase, the first capacitor and the second capacitor sample the first input signal and the second input signal, respectively; in an amplification phase, the multiplicative analog-to-digital converter performs an amplification operation to output a first output signal and a second output signal from the first output and the second output, respectively; and, in the sampling phase, the first capacitor or the second capacitor samples the first input signal or the second input signal earlier than the fifth capacitor.

10. A multiplication-digital-to-analog converter, having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal and the second input terminal respectively receive a first input signal and a second input signal, the multiplication-digital-to-analog converter comprising: a first capacitor, wherein, The first capacitor has a first node and a second node at its two ends; a second capacitor, wherein the two ends of the second capacitor are a third node and a fourth node at its two ends; a third capacitor, wherein the two ends of the third capacitor are the second node and a fifth node at its two ends; a fourth capacitor, wherein the two ends of the fourth capacitor are the fourth node and a sixth node at its two ends; an analog-to-digital converter including a fifth capacitor and used to generate a digit code; a reference voltage generation circuit coupled to the analog-to-digital converter, used to generate a reference voltage based on the digit code; an amplifier having an inverting input, a non-inverting input, an inverting output, and a non-inverting output, wherein the inverting input is coupled to the fourth node, the non-inverting input is coupled to the second node, the inverting output is coupled to the first output, and the non-inverting output is coupled to the second output; a first switch coupled between the first input and the first capacitor; A second switch is coupled between the second input terminal and the second capacitor; and a third switch is coupled between one end of the fifth capacitor and the first node or the third node; wherein, in a sampling phase, the first capacitor and the second capacitor respectively sample the first input signal and the second input signal; and, in an amplification phase, the multiplicative digital-to-analog converter performs an amplification operation to output a first output signal and a second output signal from the first output terminal and the second output terminal respectively; wherein, the first switch and the second switch change from non-conducting to conducting at the beginning of the sampling phase, and the third switch changes from non-conducting to conducting after the beginning of the sampling phase.

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