Ramp generator and image sensing device

Abstract

A ramp generator includes a digital-to-analog converter, a first capacitor, a second capacitor and a noise cancellation circuit. The digital-to-analog converter is configured to generate a ramp-up voltage signal on a first output terminal and a ramp-down voltage signal on a second output terminal. The first capacitor is coupled between the first output terminal and an intermediate node. The second capacitor is coupled between the second output terminal and the intermediate node. The noise cancellation circuit is coupled with the intermediate node. The noise cancellation circuit is configured to provide a compensation feedback according to an intermediate voltage on the intermediate node.

Description

Technical Field

[0001] This disclosure relates to a ramp signal generator and an image sensing device. More specifically, this disclosure relates to a ramp signal generator capable of reducing the inherent noise of an internal digital-to-analog converter. Prior Technology

[0002] A ramp signal generator is a signal generation circuit used to produce an output signal that varies linearly over time, commonly used in analog-to-digital converters (ADCs). In CMOS image sensors (CIS), it is necessary to convert the analog signals generated by pixels into digital signals, and the ramp signal generator is a crucial component in this conversion process. CMOS image sensors typically employ a single-slope ADC (SS-ADC) architecture due to its simplicity, low power consumption, and high linearity. In this architecture, the ramp signal generator provides a reference voltage, and the output signal of each pixel is compared to this reference voltage to determine the digital output value of each pixel. Summary of the Invention

[0003] This disclosure document discloses a ramp signal generator comprising a digital-to-analog converter, a first capacitor, a second capacitor, and a noise cancellation circuit. The digital-to-analog converter has a first output and a second output. The digital-to-analog converter generates a ramp-up voltage signal at the first output and a ramp-down voltage signal at the second output. The first capacitor is coupled between the first output and an intermediate node. The second capacitor is coupled between the second output and the intermediate node. The noise cancellation circuit is coupled to the intermediate node. The noise cancellation circuit provides compensation feedback based on the intermediate voltage at the intermediate node.

[0004] Another embodiment of this disclosure discloses an image sensing device. The image sensing device includes a ramp signal generator and an image readout circuit. The ramp signal generator generates a ramp output signal. The ramp signal generator includes a digital-to-analog converter, a first capacitor, a second capacitor, and a noise cancellation circuit. The digital-to-analog converter has a first output terminal and a second output terminal. The digital-to-analog converter generates a ramp-up voltage signal at the first output terminal and a ramp-down voltage signal at the second output terminal. The first capacitor is coupled between the first output terminal and an intermediate node. The second capacitor is coupled between the second output terminal and the intermediate node. The noise cancellation circuit is coupled to the intermediate node. The noise cancellation circuit provides compensation feedback based on the intermediate voltage at the intermediate node. The image readout circuit is coupled to the ramp signal generator and a photodetector pixel. The image readout circuit samples the pixel sensing voltage from the photodetector pixel with reference to the ramp output signal from the ramp signal generator to generate a digital output signal. Simple Explanation of the Diagram

[0005] To make the above and other objects, features and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described below: Figure 1 is a schematic diagram of a ramp signal generator according to some embodiments of this disclosure. Figure 2 is a schematic diagram of an image sensing device according to some embodiments of this disclosure. Figure 3 is a schematic diagram of the internal structure of a ramp signal generator according to some embodiments of this disclosure. Figure 4 illustrates the signal waveforms of the ramp-up voltage signal, ramp-down voltage signal, intermediate voltage, and control signal in some embodiments. Figure 5 is a schematic diagram of the internal structure of a ramp signal generator according to some embodiments of this disclosure. Figure 6 is a schematic diagram of a ramp signal generator according to some embodiments of this disclosure. Figure 7 is a schematic diagram of a ramp signal generator according to some embodiments of this disclosure. Implementation

[0006] The following disclosure provides numerous different embodiments or examples for implementing the various features of this disclosure. Where appropriate, the same reference numerals are used between figures and in corresponding text descriptions to represent the same or similar elements.

[0007] Please refer to Figure 1, which illustrates a schematic diagram of a ramp signal generator 100 according to some embodiments of the present disclosure. As shown in Figure 1, the ramp signal generator 100 includes a digital-to-analog converter (DAC) 120, a first capacitor C1, a second capacitor C2, and a noise cancellation circuit 140.

[0008] In some embodiments, the ramp signal generator 100 is a ramp signal generator based on a digital-to-analog converter 120. As shown in Figure 1, the digital-to-analog converter 120 generates a ramp-up voltage signal VRMP+ at a first output terminal of the digital-to-analog converter 120 according to a first digit code D[N:0] (containing bit codes D0~DN). The ramp-up voltage signal VRMP+ is a voltage signal that increases linearly with time. For example, as the first digit code D[N:0] decreases sequentially with time (e.g., counting down from 255 to 0), the ramp-up voltage signal VRMP+ generated by the digital-to-analog converter 120 can gradually increase from a low voltage level to a high voltage level.

[0009] Simultaneously, the digital-to-analog converter 120 generates a sloping voltage signal VRMP- at its second output terminal based on the second digit code DB[N:0] (containing bit codes DB0~DBN). The second digit code DB[N:0] can be the complement of the first digit code D[N:0]. The sloping voltage signal VRMP- is a voltage signal that decreases linearly with time. For example, as the second digit code DB[N:0] increases with time (e.g., counting from 0 to 255), the sloping voltage signal VRMP- generated by the digital-to-analog converter 120 can gradually decrease from a high voltage level to a low voltage level.

[0010] In some embodiments, the ramp signal generator 100 is used to generate a ramp output signal VRMP_OUT based on either a ramp-up voltage signal VRMP+ or a ramp-down voltage signal VRMP-, according to actual needs (e.g., ramp signal needs of subsequent circuitry connected to the ramp signal generator 100).

[0011] If the ramp output signal VRMP_OUT needs to increase linearly with time, the ramp signal generator 100 can output a ramp-up voltage signal VRMP+ as the ramp output signal VRMP_OUT. On the other hand, if the ramp output signal VRMP_OUT needs to decrease linearly with time, the ramp signal generator 100 can output a ramp-down voltage signal VRMP- as the ramp output signal VRMP_OUT.

[0012] In some embodiments, the ramp output signal VRMP_OUT and the ramp signal generator 100 can be applied to an image sensing device. Please also refer to Figure 2, which is a schematic diagram of an image sensing device 200 according to some embodiments of this disclosure.

[0013] As shown in Figure 2, the image sensing device 200 includes a ramp signal generator 100, a photosensitive pixel 210, and an image readout circuit 220. In some embodiments, the photosensitive pixel 210 includes an image sensor (e.g., a CMOS image sensor, a CCD image sensor, or a photodiode sensor) capable of sensing an optical input signal and generating a pixel sensing voltage VPIX accordingly. The image readout circuit 220 is coupled to the photosensitive pixel 210 and the ramp signal generator 100. The image readout circuit 220 samples the pixel sensing voltage VPIX with reference to the ramp output signal VRMP_OUT from the ramp signal generator 100, thereby generating a digital output signal DOUT. The digital output signal DOUT represents the grayscale or luminance level of the pixel sensing voltage VPIX.

[0014] In the embodiment shown in Figure 2, the image readout circuit 220 includes a readout comparator 222, a buffer stage 224, and a counter 226.

[0015] Buffer stage 224 is coupled to ramp signal generator 100. Buffer stage 224 is used to generate a ramp buffer signal VRMP_BUF based on the ramp output signal VRMP_OUT. In some embodiments, buffer stage 224 can be implemented by a source follower. The input signal to buffer stage 224 (i.e., the ramp output signal VRMP_OUT) and the ramp buffer signal VRMP_BUF generated by buffer stage 224 are both analog voltage signals with similar amplitude and waveform, but the ramp buffer signal VRMP_BUF differs from the ramp output signal VRMP_OUT in their impedance characteristics. The input signal (i.e., the ramp output signal VRMP_OUT) is fed into a high-impedance terminal, while the ramp buffer signal VRMP_BUF is output with low impedance, enabling it to drive subsequent circuitry more stably.

[0016] A readout comparator 222 is coupled to a buffer stage 224 and a photodetector pixel 210. The readout comparator 222 compares the pixel sensing voltage VPIX from the photodetector pixel 210 with a ramp buffer signal VRMP_BUF to generate a comparison result VCMP. A counter 226 is coupled to the readout comparator 222 and generates a digital output signal DOUT based on a time count corresponding to the point in time when the comparison result VCMP changes. Because the ramp buffer signal VRMP_BUF changes linearly with time, the time count corresponding to the change in the comparison result VCMP reflects the luminance level or grayscale corresponding to the pixel sensing voltage VPIX. Therefore, the digital output signal DOUT can be used to represent the grayscale or luminance level of the pixel sensing voltage VPIX.

[0017] In some embodiments, the ramp signal generator 100 shown in Figure 1 is not limited to use in the image sensing device 200 shown in Figure 2. The ramp output signal VRMP_OUT generated by the ramp signal generator 100 can be utilized by various circuits in different applications (e.g., analog-to-digital converters, phase-locked loops, voltage-controlled oscillators, proximity sensors, capacitive sensors, chirp signal generators).

[0018] In some embodiments, the ramp signal generator 100 may suffer from noise issues, particularly the inherent noise caused by the digital-to-analog converter 120. This noise can negatively impact the signal quality of the ramp output signal VRMP_OUT and may further reduce the accuracy of the digital output signal DOUT in image sensing, especially in low-light conditions.

[0019] In some embodiments, the ramp signal generator 100 includes a noise cancellation structure (including a first capacitor C1, a second capacitor C2, and a noise cancellation circuit 140 shown in Figure 1) to suppress common-mode and differential-mode noise.

[0020] As shown in Figure 1, the first capacitor C1 and the second capacitor C2 are connected in series between the first output terminal (the output terminal that forms the ramp-up voltage signal VRMP+) and the second output terminal (the output terminal that forms the ramp-down voltage signal VRMP-) of the digital-to-analog converter 120. An intermediate voltage VN is formed at the midpoint between the first capacitor C1 and the second capacitor C2.

[0021] In other words, the first capacitor C1 is coupled between the first output terminal of the digital-to-analog converter 120 and the intermediate node, and the second capacitor C2 is coupled between the second output terminal of the digital-to-analog converter 120 and the intermediate node.

[0022] In some embodiments, the AC component (e.g., AC noise) of the rising slope voltage signal VRMP+ is coupled to the intermediate voltage VN via a first capacitor C1, and another AC component (e.g., AC noise) of the falling slope voltage signal VRMP- is also coupled to the intermediate voltage VN via a second capacitor C2. In other words, the AC component of the intermediate voltage VN may carry noise information from both the rising slope voltage signal VRMP+ and the falling slope voltage signal VRMP-.

[0023] As shown in Figure 1, the noise cancellation circuit 140 is coupled to the intermediate node. The noise cancellation circuit 140 provides compensation feedback based on the intermediate voltage VN at the intermediate node. The compensation feedback is correlated with the AC component of the intermediate voltage VN. The compensation feedback generated by the noise cancellation circuit 140 is used to compensate for the inherent noise of the digital-to-analog converter 120.

[0024] Please also refer to Figure 3, which is a schematic diagram of the internal structure of a ramp signal generator 100 according to some embodiments of this disclosure. As shown in Figure 3, the digital-to-analog converter 120 includes a plurality of digital-to-analog conversion units 122. Each of the plurality of digital-to-analog conversion units 122 includes a first current source CS1, a first transistor M1, and a second transistor M2.

[0025] Each of the multiple digital-to-analog converter units 122 has a first transistor M1 controlled by a single bit code D0~DN in the first digital code D[N:0] to generate a ramp-up voltage signal VRMP+. In the embodiment shown in Figure 3, the first transistor M1 is implemented by a P-type metal-oxide-semiconductor field-effect transistor (PMOS). As the first digital code D[N:0] decreases over time, more of the first transistors M1 in the multiple digital-to-analog converter units 122 tend to turn on, causing the voltage level of the ramp-up voltage signal VRMP+ to increase over time.

[0026] On the other hand, the second transistors M2 of each of the multiple digital-to-analog conversion units 122 are controlled by individual bits DB0~DBN in the second bit code DB[N:0] to generate a ramp-down voltage signal VRMP-. As the second bit code D[N:0] increases over time, more of the second transistors M2 in the multiple digital-to-analog conversion units 122 tend to turn off, causing the voltage level of the ramp-down voltage signal VRMP- to decrease over time. In this embodiment shown in Figure 3, the ramp-down voltage signal VRMP- is output as a ramp output signal VRMP_OUT.

[0027] The noise cancellation circuit 140A shown in Figure 3 is an embodiment of the noise cancellation circuit 140 in Figure 1. As shown in Figure 3, the noise cancellation circuit 140A includes a third transistor M3, a switch SW, and multiple fourth transistors M4. The drain and gate terminals of the third transistor M3 are connected to a second current source CS2 to form a bias voltage VBIAS. The switch SW is coupled between the third transistor M3 and the intermediate node. The switch SW is controlled by a control signal SH. The multiple gate terminals of the multiple fourth transistors M4 are commonly connected to the intermediate node and controlled by an intermediate voltage VN. The drain terminals of each of the multiple fourth transistors M4 are connected to the feedback node NFB and the first current source CS1 of each of the multiple digital-to-analog conversion units 122.

[0028] In the embodiment shown in Figure 3, the third transistor M3 and the plurality of fourth transistors M4 are N-type metal-oxide-semiconductor field-effect transistors (NMOS). The noise cancellation circuit 140A is formed in the form of an NMOS current mirror.

[0029] Please also refer to Figure 4, which shows the signal waveforms of the ramp-up voltage signal VRMP+, the ramp-down voltage signal VRMP- (i.e., the ramp-out signal VRMP_OUT), the intermediate voltage VN, and the control signal SH in some embodiments.

[0030] As shown in Figures 3 and 4, from time point T1 to T2, the control signal SH is set to a high level, switching the switch SW to conduct, in order to reset the DC level of the intermediate voltage VN according to the bias voltage VBIAS. After time point T2, the DC level of the intermediate voltage VN becomes VBIAS + ∆Vinj, where ∆Vinj is the charge injection voltage generated when the switch SW is turned off.

[0031] As shown in Figures 3 and 4, at time point T3, the AC component NRMP+ (i.e., AC noise) of the rising voltage signal VRMP+ is coupled to the intermediate voltage VN through the first capacitor C1, and the AC component NRMP- (i.e., AC noise) of the falling voltage signal VRMP- is also coupled to the intermediate voltage VN through the second capacitor C2. In other words, the AC component NAC of the intermediate voltage VN can carry AC noise from both the rising voltage signal VRMP+ and the falling voltage signal VRMP-.

[0032] In some embodiments, the AC components NRMP+ and NRMP- (i.e., AC noise) are positively correlated with the operating current IDAC of the digital-to-analog converter 120. The operating current IDAC is generated by a first current source CS1 and flows through a first transistor M1 and a second transistor M2. As the operating current IDAC increases, the AC noise (i.e., NRMP+ and NRMP-) increases accordingly.

[0033] When the AC noise levels on the ramp-up voltage signal VRMP+ and the ramp-down voltage signal VRMP- are high, the level of the AC component NAC of the intermediate voltage VN will increase accordingly. In this case, multiple fourth transistors M4 tend to conduct, and the shunt current IFB1 flowing through the multiple fourth transistors M4 is high. As shown in Figure 3, the feedback node NFB is located between the first current source CS1 of each of the multiple digital-to-analog converter units 122 and the transistors (i.e., the first transistor M1 and the second transistor M2). As shown in Figure 3, the shunt current IFB1 shunt from the feedback node NFB competes with the operating current IDAC of the digital-to-analog converter 120. Therefore, each of the multiple fourth transistors M4 is used to form the shunt current IFB1 to suppress the operating current IDAC of the digital-to-analog converter 120.

[0034] On the other hand, when the AC noise levels on the ramp-up voltage signal VRMP+ and the ramp-down voltage signal VRMP- are low, the level of the AC component NAC of the intermediate voltage VN will also decrease. In this case, multiple fourth transistors M4 tend to turn off, and the shunt current IFB1 flowing through the multiple fourth transistors M4 is low, which will reduce the suppression effect on the operating current IDAC.

[0035] In this case, the shunt current IFB1 can serve as compensation feedback to suppress the inherent noise of the digital-to-analog converter 120.

[0036] Please also refer to Figure 5, which is a schematic diagram of the internal structure of a ramp signal generator 100 according to some embodiments of the present disclosure. As shown in Figure 5, the ramp signal generator 100 includes a digital-to-analog converter 120, a first capacitor C1, a second capacitor C2, and a noise cancellation circuit 140B.

[0037] The digital-to-analog converter 120, the first capacitor C1, and the second capacitor C2 in the embodiment shown in Figure 5 are similar to those in Figure 3, and will not be described again here.

[0038] The noise cancellation circuit 140B shown in Figure 5 is another embodiment of the noise cancellation circuit 140 in Figure 1. As shown in Figure 5, the noise cancellation circuit 140B includes a low-dropout (LDO) regulator 141, a fifth transistor M5, a switch SW, and a plurality of sixth transistors M6.

[0039] Low-dropout regulator 141 is used to maintain a stable output voltage generated from the system power supply voltage AVDD. Low-dropout regulator 141 can also be used to filter voltage noise on the system power supply voltage AVDD. The drain and gate terminals of the fifth transistor M5 are connected to the third current source CS3 to form a bias voltage VBIAS. The source terminal of the fifth transistor M5 is connected to the low-dropout regulator 141. Switch SW is coupled between the fifth transistor M5 and the intermediate node. Switch SW is controlled by the control signal SH. Multiple gate terminals of multiple sixth transistors M6 are connected to the intermediate node and controlled by the intermediate voltage VN. The drain terminals of each of the multiple sixth transistors M6 are respectively connected to the feedback node NFB and the first current source CS1 of each of the multiple digital-to-analog converters 122.

[0040] In the embodiment shown in Figure 5, the fifth transistor M5 and the plurality of sixth transistors M6 are P-type metal-oxide-semiconductor field-effect transistors (PMOS). The noise cancellation circuit 140B is formed in the form of a PMOS current mirror.

[0041] The waveform shown in Figure 4 also applies to the ramp signal generator 100 and noise cancellation circuit 140B shown in Figure 5.

[0042] As shown in Figures 4 and 5, from time point T1 to T2, the control signal SH is set to a high level, causing the switch SW to switch to conduction to reset the DC level of the intermediate voltage VN according to the bias voltage VBIAS. After time point T2, the DC level of the intermediate voltage VN will become VBIAS + ∆Vinj.

[0043] As shown in Figures 4 and 5, at time point T3, the AC component NRMP+ (i.e., AC noise) of the rising voltage signal VRMP+ is coupled to the intermediate voltage VN through the first capacitor C1, and the AC component NRMP- (i.e., AC noise) of the falling voltage signal VRMP- is also coupled to the intermediate voltage VN through the second capacitor C2. In other words, the AC component NAC of the intermediate voltage VN can carry AC noise from both the rising voltage signal VRMP+ and the falling voltage signal VRMP-.

[0044] As shown in Figure 5, multiple sixth transistors M6 are each used to form a supplementary current IFB2 to the feedback node NFB in the digital-to-analog converter 120. The supplementary current IFB2 will be added to the operating current IDAC of the digital-to-analog converter 120. The supplementary current IFB2 and the operating current IDAC will flow through the first transistor M1 and the second transistor M2 to form a ramp-up voltage signal VRMP+ and a ramp-down voltage signal VRMP-.

[0045] In some embodiments, the AC components NRMP+ and NRMP- (i.e., AC noise) are positively correlated with the operating current IDAC of the digital-to-analog converter 120. The value of the supplementary current IFB2 is negatively correlated with the AC component NAC of the intermediate voltage VN (because the plurality of sixth transistors M6 are PMOS).

[0046] When the AC noise levels on the ramp-up voltage signal VRMP+ and the ramp-down voltage signal VRMP- are high, the level of the AC component NAC of the intermediate voltage VN will increase accordingly. In this case, multiple sixth transistors M6 tend to turn off, and the current value of the supplementary current IFB2 flowing through the multiple sixth transistors M6 is low. In other words, when the AC noise level is high, the current value of the supplementary current IFB2 is low.

[0047] On the other hand, when the AC noise levels on the ramp-up voltage signal VRMP+ and the ramp-down voltage signal VRMP- are low, the level of the AC component NAC of the intermediate voltage VN will also decrease. In this case, multiple sixth transistors M6 tend to conduct, and the current value of the supplementary current IFB2 flowing through the multiple sixth transistors M6 is high. In other words, when the AC noise level is low, the current value of the supplementary current IFB2 is high.

[0048] In this case, the supplementary current IFB2 is used as compensation feedback to suppress the inherent noise of the digital-to-analog converter 120.

[0049] The noise cancellation circuits 140A and 140B shown in Figure 3 and Figure 5, respectively, are used to generate compensation feedback (i.e., shunt current IFB1 and supplementary current IFB2) to the digital-to-analog converter 120 inside the ramp signal generator 100. However, this disclosure is not limited thereto. In some other embodiments, the compensation feedback generated by the noise cancellation circuit 140 in Figure 1 may also be sent to other circuit components (e.g., the readout comparator 222 or the buffer stage 224 shown in Figure 2).

[0050] Please also refer to Figure 6, which is a schematic diagram of a ramp signal generator 100 according to some embodiments of the present disclosure. As shown in Figure 6, the ramp signal generator 100 includes a digital-to-analog converter 120, a first capacitor C1, a second capacitor C2, and a noise cancellation circuit 140C. The digital-to-analog converter 120, the first capacitor C1, and the second capacitor C2 shown in Figure 6 are similar to those shown in Figure 3, and will not be described again here.

[0051] The noise cancellation circuit 140C shown in Figure 6 is used to generate a compensation feedback (i.e., supplementary voltage VFB1) to the buffer stage 224.

[0052] As shown in Figures 2 and 6, buffer stage 224 can be implemented by a source follower, which includes a ninth transistor M9. The gate of the ninth transistor M9 is used to receive the ramp output signal VRMP_OUT (i.e., the ramp-down voltage signal VRMP-). The drain of the ninth transistor M9 is used to generate the ramp buffer signal VRMP_BUF. As shown in Figure 2, the ramp buffer signal VRMP_BUF is transmitted to the readout comparator 222 as a reference voltage for signal comparison.

[0053] As shown in Figure 6, the noise cancellation circuit 140C includes a low-dropout (LDO) regulator 141, a seventh transistor M7, a switch SW, and an eighth transistor M8. The LDO regulator 141 maintains a stable output voltage generated from the system power supply voltage AVDD. The LDO regulator 141 also filters voltage noise on the system power supply voltage AVDD. The drain and gate terminals of the seventh transistor M7 are connected to a fourth current source CS4 to form a bias voltage VBIAS. The source terminal of the seventh transistor M7 is connected to the LDO regulator 141. The switch SW is coupled between the seventh transistor M7 and the intermediate node. The switch SW is controlled by the control signal SH. The gate terminal of the eighth transistor M8 is connected to the intermediate node. The drain terminal of the eighth transistor M8 is connected to the buffer stage 224.

[0054] The waveform shown in Figure 4 also applies to the ramp signal generator 100 and noise cancellation circuit 140C shown in Figure 6.

[0055] As shown in Figures 4 and 6, from time point T1 to T2, the control signal SH is set to a high level, causing the switch SW to switch to conduction to reset the DC level of the intermediate voltage VN according to the bias voltage VBIAS. After time point T2, the DC level of the intermediate voltage VN will become VBIAS + ∆Vinj.

[0056] As shown in Figures 4 and 6, at time point T3, the AC component NRMP+ (i.e., AC noise) of the ramp-up voltage signal VRMP+ will be coupled to the intermediate voltage VN through the first capacitor C1, and the AC component NRMP- (i.e., AC noise) of the ramp-down voltage signal VRMP- will also be coupled to the intermediate voltage VN through the second capacitor C2.

[0057] As shown in Figure 6, the eighth transistor M8 is used to form a supplementary voltage VFB1 to the drain terminal of the ninth transistor M9 in buffer stage 224. The supplementary voltage VFB1 is used to boost the ramp buffer signal VRMP_BUF.

[0058] In some embodiments, the AC components NRMP+ and NRMP- (i.e., AC noise) are positively correlated with the operating current IDAC of the digital-to-analog converter 120. The voltage level of the supplementary voltage VFB1 is negatively correlated with the AC component NAC of the intermediate voltage VN (because the eighth transistor M8 is a PMOS).

[0059] When the AC noise levels on the ramp-up voltage signal VRMP+ and the ramp-down voltage signal VRMP- are high, the level of the AC component NAC of the intermediate voltage VN will increase accordingly. In this case, the eighth transistor M8 tends to turn off, and the level of the supplementary voltage VFB1 is low. In other words, when the AC noise level is high, the level of the supplementary voltage VFB1 will decrease accordingly.

[0060] On the other hand, when the AC noise levels on the ramp-up voltage signal VRMP+ and the ramp-down voltage signal VRMP- are low, the level of the AC component NAC of the intermediate voltage VN will also decrease. In this case, the eighth transistor M8 tends to turn on, and the level of the supplementary voltage VFB1 will be higher. In other words, when the AC noise level is low, the level of the supplementary voltage VFB1 will increase accordingly.

[0061] In this case, the supplemental voltage VFB1 is used as compensation feedback to suppress the inherent noise of the digital-to-analog converter 120.

[0062] Please also refer to Figure 7, which is a schematic diagram of a ramp signal generator 100 according to some embodiments of the present disclosure. As shown in Figure 7, the ramp signal generator 100 includes a digital-to-analog converter 120, a first capacitor C1, a second capacitor C2, and a noise cancellation circuit 140D. The digital-to-analog converter 120, the first capacitor C1, and the second capacitor C2 shown in Figure 7 are similar to those shown in Figure 3, and will not be described again here.

[0063] The noise cancellation circuit 140D shown in Figure 7 is used to generate compensation feedback (i.e., supplementary voltage VFB2) to the readout comparator 222.

[0064] As shown in Figures 2 and 7, buffer stage 224 generates a ramp buffer signal VRMP_BUF based on the ramp output signal VRMP_OUT. The readout comparator 222 includes a first comparator 222a, a second comparator 222b, and an inverter 222c. The ramp buffer signal VRMP_BUF generated by buffer stage 224 is transmitted to the positive input of the first comparator 222a via a sixth capacitor C6. The pixel sensing voltage VPIX from the photoelectric sensing pixel 210 is transmitted to the negative input of the first comparator 222a via a fifth capacitor C5. The first comparator 222a generates an internal comparison result VCMPi by comparing the signals at the positive and negative inputs.

[0065] As shown in Figure 7, the noise cancellation circuit 140D includes a third capacitor C3, a fourth capacitor C4, and a switch SW. The third capacitor C3 is coupled between the negative input terminal of the first comparator 222a and the intermediate node. The fourth capacitor C4 is coupled between the positive input terminal of the first comparator 222a and the signal source of the bias voltage VBIAS.

[0066] Switch SW is coupled between the bias voltage VBIAS signal source and the intermediate node. Switch SW is used to reset the DC level of the intermediate voltage VN on the intermediate node according to the bias voltage VBIAS.

[0067] As shown in Figure 7, the AC component of the intermediate voltage VN (refer to the AC component NAC in Figure 4) can be coupled to the negative input terminal of the first comparator 222a through the third capacitor C3. The third capacitor C3 is used to form a supplementary voltage VFB2 based on the AC component of the intermediate voltage VN, which is then applied to the negative input terminal of the first comparator 222a. The voltage level of the supplementary voltage VFB2 is positively correlated with the AC component of the intermediate voltage VN.

[0068] The ramp buffer signal VRMP_BUF is positively correlated with the ramp output signal VRMP_OUT, and also positively correlated with the AC component NRMP- (i.e., AC noise caused by the digital-to-analog converter 120) on the ramp drop voltage signal VRMP-. Since the supplementary voltage VFB2 is supplied to the negative input of the first comparator 222a, the supplementary voltage VFB2 can be used to suppress the ramp buffer signal VRMP_BUF.

[0069] In this case, the supplemental voltage VFB2 is used as compensation feedback to suppress the inherent noise of the digital-to-analog converter 120.

[0070] The noise cancellation circuit 140C shown in Figure 6 and the noise cancellation circuit 140D shown in Figure 7 are used to generate compensation feedback (i.e., supplementary voltages VFB1 and VFB2) to the readout comparator 222 or buffer stage 224 in the image readout circuit 220 shown in Figure 2. In other words, the compensation feedback generated by the noise cancellation circuit 140 in Figure 1 can be fed to other circuit components other than the ramp signal generator 100 to indirectly compensate for the inherent noise of the digital-to-analog converter 120.

[0071] This disclosure provides a ramp signal generator with noise cancellation circuitry to reduce AC noise or inherent noise caused by the digital-to-analog converter 120. When an image sensing device includes the aforementioned ramp signal generator with noise cancellation circuitry, the performance or accuracy of image sensing can be enhanced, especially under low-light (or dark pixel content) conditions.

[0072] While specific embodiments of the present disclosure have been disclosed in relation to the above embodiments, these embodiments are not intended to limit the present disclosure. Various alternatives and modifications can be made by those skilled in the art in accordance with the present disclosure without departing from the principles and spirit of the present disclosure. Therefore, the scope of protection of the present disclosure is determined by the appended claims.

[0073] 100: Ramp Signal Generator 120: Digital-to-Analog Converter 122: Digital-to-Analog Conversion Unit 140, 140A, 140B, 140C, 140D: Noise cancellation circuits 141: Low dropout voltage regulator 200: Image sensing device 210: Photoelectric sensing pixel 220: Image readout circuit 222: Readout comparator 222a: First comparator 222b: Second comparator 222c: Inverter 224: Buffer Level 226: Counter C1: First capacitor C2: Second capacitor C3: Third capacitor C4: Fourth capacitor C5: Fifth capacitor C6: Sixth capacitor CS1: First current source CS2: Second current source CS3: Third Current Source CS4: Fourth Current Source D[N:0]: First digit code DB[N:0]: Second digit code D0, DN: Bit code DB0, DBN: Bit code DOUT: Digital Output Signal IDAC: Operating Current IFB1: Shunt current IFB2: Supplemental Current M1: First transistor M2: Second transistor M3: Third transistor M4: Fourth Transistor M5: Fifth Transistor M6: Sixth Transistor M7: Seventh Transistor M8: Eighth transistor M9: Ninth Transistor NAC, NRMP+, NRMP-: AC components NFB: Feedback Node SH: Control Signal SW: Switch T1, T2, T3: Time points VBIAS: Bias Voltage VCMP: Comparison Results VCMPi: Internal comparison result VFB1, VFB2: Supplemental voltage VN: Intermediate voltage VPIX: Pixel Sensing Voltage VRMP+: Ramp-up Voltage Signal VRMP - Ramp Down Voltage Signal VRMP_BUF: Ramp Buffer Signal VRMP_OUT: Ramp output signal AVDD: System power supply voltage

[0074] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A ramp signal generator, comprising: a digital-to-analog converter having a first output terminal and a second output terminal, and for generating a ramp-up voltage signal at the first output terminal and a ramp-down voltage signal at the second output terminal; a first capacitor coupled between the first output terminal and an intermediate node; a second capacitor coupled between the second output terminal and the intermediate node; and a noise cancellation circuit coupled to the intermediate node and for providing a compensation feedback based on an intermediate voltage at the intermediate node.

2. The ramp signal generator as claimed in claim 1, wherein the compensation feedback is correlated with an AC component of the intermediate voltage, the compensation feedback being used to compensate for an inherent noise of the digital-to-analog converter.

3. The ramp signal generator as claimed in claim 1, wherein the digital-to-analog converter includes a plurality of digital-to-analog conversion units, each of the plurality of digital-to-analog conversion units including a first current source, a first transistor, and a second transistor, wherein the first transistor of each of the plurality of digital-to-analog conversion units is controlled by a single bit code in a first digital code to generate the ramp-up voltage signal, and the second transistor of each of the plurality of digital-to-analog conversion units is controlled by a single bit code in a second digital code to generate the ramp-down voltage signal.

4. The ramp signal generator as claimed in claim 3, wherein the noise cancellation circuit comprises: a third transistor, wherein a drain terminal and a gate terminal of the third transistor are connected to a second current source to form a bias voltage; a switch coupled between the third transistor and the intermediate node; and a plurality of fourth transistors, wherein a plurality of gate terminals of the plurality of fourth transistors are commonly connected to the intermediate node, and a drain terminal of each of the plurality of fourth transistors is connected to the first current source of each of the plurality of digital-to-analog converters.

5. The ramp signal generator as claimed in claim 4, wherein the switch is configured to reset the DC level of the intermediate voltage at the intermediate node according to the bias voltage, and each of the plurality of fourth transistors is configured to form a shunt current to suppress an operating current of the digital-to-analog converter.

6. The ramp signal generator as claimed in claim 3, wherein the noise cancellation circuit comprises: a low-dropout regulator; a fifth transistor, wherein a drain terminal and a gate terminal of the fifth transistor are connected to a third current source to form a bias voltage, and a source terminal of the fifth transistor is connected to the low-dropout regulator; a switch coupled between the fifth transistor and the intermediate node; and a plurality of sixth transistors, wherein a plurality of gate terminals of the plurality of sixth transistors are commonly connected to the intermediate node, and a drain terminal of each of the plurality of sixth transistors is respectively connected to the first current source of each of the plurality of digital-to-analog converters.

7. The ramp signal generator as claimed in claim 6, wherein the switch is configured to reset the DC level of the intermediate voltage at the intermediate node according to the bias voltage, and the plurality of sixth transistors are each configured to form a supplementary current to the digital-to-analog converter, wherein a current value of the supplementary current is negatively correlated with an AC component of the intermediate voltage.

8. The ramp signal generator of claim 1, wherein the ramp signal generator is configured to generate a ramp output signal to an image readout circuit, the image readout circuit comprising: a buffer stage coupled to the ramp signal generator and configured to generate a ramp buffer signal based on the ramp output signal; a readout comparator coupled to the buffer stage and a photodetector pixel and configured to compare a pixel sensing voltage from the photodetector pixel with the ramp buffer signal to generate a comparison result; and a counter coupled to the readout comparator and configured to generate a digital output signal based on the comparison result, the digital output signal representing a grayscale or a luminance level of the pixel sensing voltage.

9. The ramp signal generator as claimed in claim 8, wherein the noise cancellation circuit comprises: a low-dropout regulator; a seventh transistor, wherein a drain terminal and a gate terminal of the seventh transistor are connected to a fourth current source to form a bias voltage, and a source terminal of the seventh transistor is connected to the low-dropout regulator; a switch coupled between the seventh transistor and the intermediate node; and an eighth transistor, wherein a gate terminal of the eighth transistor is connected to the intermediate node, and a drain terminal of the eighth transistor is connected to the buffer stage.

10. The ramp signal generator of claim 9, wherein the buffer stage includes a ninth transistor, wherein a gate terminal of the ninth transistor is configured to receive the ramp output signal, a drain terminal of the ninth transistor is configured to generate the ramp buffer signal, wherein the switch is configured to reset the DC level of the intermediate voltage at the intermediate node according to the bias voltage, and the eighth transistor is configured to form a supplementary voltage to the drain terminal of the ninth transistor, wherein a voltage level of the supplementary voltage is negatively correlated with an AC component of the intermediate voltage.

11. The ramp signal generator as claimed in claim 8, wherein the readout comparator includes a first comparator, a second comparator, and an inverter, wherein the noise cancellation circuit includes: a third capacitor coupled between a negative input of the first comparator and the intermediate node; a fourth capacitor coupled between a positive input of the first comparator and a biased signal source; and a switch coupled between the biased signal source and the intermediate node.

12. The ramp signal generator as claimed in claim 11, wherein the switch is configured to reset the DC level of the intermediate voltage at the intermediate node according to the bias voltage, and the third capacitor is configured to form a supplementary voltage to the negative input of the first comparator, wherein a voltage level of the supplementary voltage is positively correlated with an AC component of the intermediate voltage.

13. An image sensing device, comprising: a ramp signal generator for generating a ramp output signal, wherein the ramp signal generator includes: a digital-to-analog converter having a first output terminal and a second output terminal, and for generating a ramp-up voltage signal at the first output terminal and a ramp-down voltage signal at the second output terminal, wherein the ramp output signal is generated based on the ramp-up voltage signal or the ramp-down voltage signal; and a first capacitor coupled between the first output terminal and an intermediate node; A second capacitor is coupled between the second output terminal and the intermediate node; a noise cancellation circuit is coupled to the intermediate node and is used to provide a compensation feedback based on an intermediate voltage on the intermediate node; and an image readout circuit is coupled to the ramp signal generator and a photodetector pixel, the image readout circuit being used to sample a pixel sensing voltage from the photodetector pixel with reference to the ramp output signal from the ramp signal generator to generate a digital output signal.

14. The image sensing apparatus of claim 13, wherein the image readout circuitry comprises: a buffer stage coupled to the ramp signal generator and configured to generate a ramp buffer signal based on the ramp output signal; a readout comparator coupled to the buffer stage and the photosensitive pixel and configured to compare the pixel sensing voltage from the photosensitive pixel with the ramp buffer signal to generate a comparison result; and a counter coupled to the readout comparator and configured to generate the digital output signal based on the comparison result, the digital output signal representing a grayscale or a luminance level of the pixel sensing voltage.

15. The image sensing apparatus of claim 14, wherein the digital-to-analog converter includes a plurality of digital-to-analog conversion units, each of the plurality of digital-to-analog conversion units including a first current source, a first transistor, and a second transistor, wherein the first transistor of each of the plurality of digital-to-analog conversion units is controlled by a single bit code in a first digital code to generate the ramp-up voltage signal, and the second transistor of each of the plurality of digital-to-analog conversion units is controlled by a single bit code in a second digital code to generate the ramp-down voltage signal.

16. The image sensing apparatus of claim 15, wherein the noise cancellation circuit comprises: a third transistor, wherein a drain terminal and a gate terminal of the third transistor are connected to a second current source to form a bias voltage; a switch coupled between the third transistor and the intermediate node; and a plurality of fourth transistors, wherein a plurality of gate terminals of the plurality of fourth transistors are commonly connected to the intermediate node, and a drain terminal of each of the plurality of fourth transistors is connected to the first current source of each of the plurality of digital-to-analog conversion units.

17. The image sensing apparatus of claim 15, wherein the noise cancellation circuit comprises: a low-dropout regulator; a fifth transistor, wherein a drain terminal and a gate terminal of the fifth transistor are connected to a third current source to form a bias voltage, and a source terminal of the fifth transistor is connected to the low-dropout regulator; a switch coupled between the fifth transistor and the intermediate node; and a plurality of sixth transistors, wherein a plurality of gate terminals of the plurality of sixth transistors are commonly connected to the intermediate node, and a drain terminal of each of the plurality of sixth transistors is respectively connected to the first current source of each of the plurality of digital-to-analog conversion units.

18. The image sensing apparatus of claim 15, wherein the noise cancellation circuit comprises: a low-dropout regulator; a fifth transistor, wherein a drain terminal and a gate terminal of the fifth transistor are connected to a third current source to form a bias voltage, and a source terminal of the fifth transistor is connected to the low-dropout regulator; a switch coupled between the fifth transistor and the intermediate node; and a plurality of sixth transistors, wherein a plurality of gate terminals of the plurality of sixth transistors are commonly connected to the intermediate node, and a drain terminal of each of the plurality of sixth transistors is respectively connected to the first current source of each of the plurality of digital-to-analog conversion units.

19. The image sensing apparatus of claim 14, wherein the readout comparator includes a first comparator, a second comparator, and an inverter, wherein the noise cancellation circuit includes: a third capacitor coupled between a negative input terminal of the first comparator and the intermediate node; a fourth capacitor coupled between a positive input terminal of the first comparator and a biased signal source; and a switch coupled between the biased signal source and the intermediate node.

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