Dram with improved bit line contact and method of manufacturing the same

Abstract

The present invention discloses a DRAM with an improved bit line contact, including a contact hole formed on an active area, a bit line contact positioned in the contact hole and directly contacting the active region, wherein an isolation oxide layer is provided on parts of the sidewall of the bit line contact, and an air gap is formed between the isolation oxide layer and the STI at two sides of the contact hole, a bit line positioned on the bit line contact, and a storage node contact positioned on the adjacent active region, wherein the storage node contact is separated from the bit line contact by the STI, the air gap and the isolation oxide layer.

Description

[Technical Field]

[0001] This invention is generally related to a dynamic random access memory (DRAM), and more particularly, to a dynamic random access memory having improved bit line contacts and a method of manufacturing the same. [Previous Technology]

[0002] Dynamic random access memory (DRAM) devices have many memory cells, each capable of storing one bit of information. Each cell typically consists of a storage capacitor and a transistor. One end of the transistor's source or drain is connected to the storage capacitor, and the other end is connected to a bit line. Electrical connections between these components are necessary for the device to function. These connections are typically achieved by forming contacts in an insulating layer, such as bit line contacts and storage node contacts.

[0003] However, as electronic products become increasingly miniaturized, DRAM memory cell designs are also evolving towards higher integration and density, leading to ever-increasing market demand. To achieve higher integration, the pattern linewidth of related semiconductor components must be reduced, resulting in a higher risk of short circuits between components. Particularly in DRAM structures employing self-aligned contact technology, process variations and low tolerances can easily cause short circuits between closely spaced bit line contacts and memory node contacts, potentially leading to component failure. For example, this can occur when bit line contacts are exposed due to over-etching of the isolation layer, or when bit line contacts are not accurately patterned. Therefore, those skilled in the art need to improve existing DRAM contacts to avoid the aforementioned short circuit problems. [Summary of the Invention]

[0004] In view of the problems encountered by the aforementioned prior art, the present invention proposes a novel dynamic random access memory, characterized in that a void and an isolation oxide layer are formed between the bit line contact and the storage node contact, which solves the problem of short-circuit bridging between the two contacts in the prior art, and at the same time reduces the parasitic capacitance of the component.

[0005] One aspect of the present invention is to provide a dynamic random access memory with improved bit line contacts, comprising: a substrate having a plurality of active regions defined by shallow trench isolation structures; a contact hole formed on each of the active regions, the contact hole being recessed into the active region and having the shallow trench isolation structures on both sides; a bit line contact located in the contact hole and in direct contact with the active regions, wherein a partial sidewall of the bit line contact has an isolation oxide layer, a gap exists between the isolation oxide layer and the shallow trench isolation structures on both sides of the contact hole, and the isolation oxide layer is exposed through the gap; a bit line located on and connected to the bit line contacts; a storage node contact located on and in direct contact with another active region adjacent to the bit line contact, wherein the storage node contact and the bit line contact are separated by the shallow trench isolation structures, the gap, and the isolation oxide layer; and a storage node located on and connected to each of the storage node contacts.

[0006] Another aspect of the present invention is to provide a method for manufacturing dynamic random access memory with improved bit line contacts, comprising: providing a substrate having a plurality of active regions defined by shallow trench isolation structures; forming a contact hole in each active region, the contact hole being recessed into the active region and having the shallow trench isolation structures on both sides; forming a sacrificial layer on the sidewall of the contact hole; filling the contact hole with a polysilicon layer, the bottom surface and side surface of the polysilicon layer being in direct contact with the active region and the sacrificial layer, respectively; and performing a photolithography process to pattern the polysilicon layer into a bit line contact. And a bit line, each bit line contact being located in a contact hole and in direct contact with the active region; removing the sacrificial layer to form a gap between the bit line contact and the surrounding shallow trench isolation structure, with a portion of the bit line contact exposed from the gap; performing an oxygen annealing process to oxidize the portion of the bit line contact exposed from the gap into an isolation oxide layer; and forming a storage node contact on another active region adjacent to the bit line contact, wherein the storage node contact and the bit line contact are separated by the shallow trench isolation structure, the gap, and the isolation oxide layer.

[0007] Such and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments described below with various illustrations and drawings.

Implementation Method

[0008] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the described features to enable the reader to understand and achieve the technical effects. The reader will understand that the descriptions herein are by way of illustration only and are not intended to limit the scope of the invention. Various embodiments of the invention and various non-conflicting features thereof can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.

[0009] It should be readily understood by the reader that the meanings of "on," "above," and "above" in this case should be interpreted broadly, such that "on" not only means "directly on" something but also includes the meaning of being "on" something with an intervening feature or layer, and that "above" or "above" not only means "above" or "above" something but can also include the meaning of being "above" or "above" something without an intervening feature or layer (i.e., directly on something). Furthermore, spatially related terms such as "below," "under," "lower part," "above," and "upper part" may be used herein for descriptive convenience to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0010] Readers can generally understand terms at least partially from their usage in context. For example, depending at least partially on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partially on the context, terms such as "a," "an," "the," or "the" can also be understood to convey either a singular or a plural usage. In addition, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least partially on the context.

[0011] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they expressly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.

[0012] As used herein, the term "substrate" refers to the material on which subsequent material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0013] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a range smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any horizontal faces at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0014] First, please refer to Figure 1, which is a top view schematic diagram of a dynamic random access memory (DRAM) with improved bit line contacts according to Embodiment 1 of the present invention. The DRAM of the present invention is fabricated on a semiconductor substrate, such as a silicon substrate, a silicon-coated insulator (SOI) substrate, or a silicon-germanium substrate. A storage cell region and a peripheral region located around the storage cell region are defined on the semiconductor substrate. The storage cell region is used to set up the storage cells of the memory, or storage nodes. Multiple storage nodes can be arranged in an array in the storage cell region, storing charge to generate distinct storage states. The peripheral region is used to set up peripheral circuits of the memory, such as row decoders, column decoders, sense amplifiers, or I / O control modules and other functional circuits. Since the inventive features of this case are not related to the peripheral region, in order to avoid obscuring the focus of the present invention, only the components and features in the storage cell region will be shown in this figure. The memory cell region of the semiconductor substrate defines multiple active areas (AA), each AA being separated and defined by a shallow trench isolation structure (STI, not shown) formed on the substrate. In an embodiment, the active areas AA are short strips in plan view, with their long axis extending in a third direction D3, and the multiple active areas AA can be uniformly arranged in a staggered manner in a first direction D1. Dopants can be incorporated into the active areas AA to form various doped regions as well regions, endpoints, or channels of memory elements.

[0015] Referring again to Figure 1. In addition to the active region AA mentioned above, multiple word lines WL and bit lines BL are also disposed on the semiconductor substrate. The long axis of the word lines WL extends in the first direction D1 and is evenly spaced in the second direction D2. The long axis of the bit lines BL extends in the second direction D2 and is evenly spaced in the first direction D1. The first direction D1 and the second direction D2 are preferably orthogonal, and the angle between the third direction D3 and the second direction D2 is preferably between 0 degrees and 45 degrees. The word lines WL are usually embedded in the semiconductor substrate and serve as memory access transistors to control the switching of the gate and the storage and release of charge. The bit lines BL are usually disposed on the semiconductor substrate and span multiple word lines WL. They are connected to the active region AA through bit line contacts BLC to perform data writing and reading operations. Specifically, in this embodiment, bit lines BL extend in the second direction D2, crossing multiple active regions AA, and are connected to the middle portion of these active regions AA via corresponding bit line contacts BLC. Word lines WL extend in the first direction D1, crossing multiple active regions AA. Each active region AA is crossed by two word lines WL, with their overlapping portions located on either side of the bit line contacts BLC. Furthermore, the two ends of each active region AA are memory storage nodes, which, in the plan view, are located in the space between the intersecting word lines WL and bit lines BL. These two ends are connected to the corresponding storage structure, such as capacitors (not shown), via their respective storage node contacts SNC. With this configuration, each active region AA has two storage nodes, each storage node is controlled by a word line WL for access, and data is written and read via a bit line.

[0016] After explaining the planar layout of the DRAM of the present invention, please now refer to Figure 2, which is a cross-sectional schematic diagram of a DRAM with improved bit line contacts according to Embodiment 1 of the present invention. The cross-sectional view is drawn with the line S-S' in Figure 1, and the important technical features of the DRAM structure of the present invention are illustrated by taking the range of one bit line contact BLC, two storage node contacts SNC, and two bit lines BL on the first direction D1 as an example.

[0017] As shown in Figure 2, the DRAM of the present invention is fabricated on a semiconductor substrate 100, such as a silicon substrate, a silicon-coated insulator (SOI) substrate, or a silicon-germanium substrate. Multiple active regions AA are defined in the storage cell region of the semiconductor substrate 100, separated and defined by shallow trench isolation structures (STIs) formed on the semiconductor substrate 100. The active regions AA are the portions of the semiconductor substrate 100 exposed from the shallow trench isolation structures (STIs). Their material can be single-crystal silicon, and various doped regions can be formed by incorporating dopants through ion bonding or diffusion processes, serving as well regions, endpoints, or channels of memory elements. For the sake of simplicity, the doped regions will not be shown in subsequent figures. The shallow trench isolation structures (STIs) can be made of silicon oxide (SiO2), which electrically isolates each active region AA. In an embodiment, a contact hole 102 is formed on each active region AA, in which a bit line contact (BLC) component of the DRAM is disposed. The contact hole 102 is recessed into the corresponding active region AA, reducing the height of the top surface of the active region AA, and the two sides are shallow trench isolation structures (STI). The bit line contact BLC is located in the contact hole 102 and makes direct electrical contact with the corresponding active region AA. Its material can be polycrystalline silicon. In the embodiment, the contact hole 102 is not completely filled by the bit line contact BLC. A gap-filling insulating layer 116 is formed on the sidewall of the bit line contact BLC, which fills most of the remaining space of the contact hole 102. The gap-filling insulating layer 116 can be made of silicon nitride (Si3N4), which can serve as a spacer for the bit line contact BLC to electrically isolate it from surrounding components.

[0018] Referring again to Figure 2. In an embodiment, a lateral protrusion 106c may be formed near the bottom of the bit line contact (BLC). The protrusion 106c may be formed due to an imperfect photolithography process. If it protrudes from the interstitial insulating layer 116, it may cause a short circuit between the bit line contact (BLC) and the subsequently formed storage node contact (SNC). To address this, in an embodiment, an isolation oxide layer 122 is formed on a portion of the sidewall of the bit line contact (BLC), particularly on the sidewall of the protrusion 106c. The isolation oxide layer 122 may be made of silicon oxide and can serve as an electrical isolation layer between the bit line contact (BLC) and surrounding components. As can be seen from the figure, the isolation oxide layer 122 and the aforementioned interstitial insulating layer 116 can together serve as a spacer wall for the bit line contact (BLC). Furthermore, a void 120a is formed between the gap-filling insulating layer 116 and / or the insulating oxide layer 122 and the adjacent shallow trench isolation structure STI. This void 120a may be annularly surrounding the corresponding bit line contact BLC (as shown in Figure 1). In the embodiment, the aforementioned void 120a and the insulating oxide layer 122 can further enhance the electrical isolation between the bit line contact BLC and the storage node contact SNC, especially when the formed bit line contact BLC has a protrusion 106c defect. In addition, the void 120a can also reduce the parasitic capacitance between the bit line contact BLC and the storage node contact SNC, improving the overall electrical properties of the memory element.

[0019] Referring again to Figure 2. In addition to the bit line contacts BLC described above, bit lines BL are formed on the semiconductor substrate 100. In this embodiment of the invention, some bit lines BL are located on and electrically connected to the bit line contacts BLC, and some bit lines BL are located on the shallow trench isolation structure STI, with a first interlayer insulating layer 112 and a second interlayer insulating layer 114 therebetween to electrically isolate the bit lines BL from the adjacent non-corresponding active regions AA. The materials of the first interlayer insulating layer 112 and the second interlayer insulating layer 114 can be silicon oxide and silicon nitride, respectively, wherein the sidewall of the second interlayer insulating layer 114 can be flush with the sidewall of the bit line BL. More specifically, in this embodiment, the bit line BL comprises a polysilicon layer 106b and a metal layer 108, and the polysilicon layer 106b may be integrally formed with the polysilicon bit line contact BLC in the contact hole 102. The metal layer 108 may be made of titanium (Ti), titanium nitride (TiN), tungsten (W), or a multilayer structure composed of materials thereon. In other embodiments, the polysilicon layer 106b and the bit line contact BLC may also be integrally formed, electrically connected through other layer structures. In addition, a thick hard mask layer 110 may be provided above the bit line BL, which may be made of silicon nitride, for the hard mask pattern used in the photolithography process of forming the bit line BL. One end of the bit line BL can be electrically connected to the active region AA through its polysilicon layer 106b and bit line contact BLC, while the other end can be connected to an external circuit through its metal layer 108 to provide a stable ohmic contact.

[0020] Referring again to Figure 2. In this embodiment, a first spacer 118 and a second spacer 124 are sequentially formed on the sidewalls of the bit line BL (including the hard masking layer 110 thereon). The first spacer 118 is located on the sidewalls of the bit line BL and the hard masking layer 110, as well as on the interstitial insulating layer 116, and its material may be silicon oxide. The sidewalls of the first spacer 118 may be flush with the sidewalls of the underlying first interlayer insulating layer 112. The second spacer 124 is located on the sidewalls of the first spacer 118 and on the shallow trench isolation structures STI on both sides, and the second spacer 124 can seal the void 120a and connect to the underlying interstitial insulating layer 116. The material of the second spacer 124 may have etch selectivity relative to the material of the first spacer 118, such as silicon nitride. In the embodiment, the first spacer 118 and the second spacer 124 serve as electrical isolation layers between the bit line BL and the adjacent storage node contact SNC, and can achieve the self-alignment effect of the storage node contact SNC during the manufacturing process.

[0021] Referring again to Figure 2. In this embodiment, a storage node contact SNC is formed on the semiconductor substrate 100 on both sides of the bit line contact BLC in the first direction D1. The storage node contact SNC extends downward into the active region AA and the shallow trench isolation structure STI, and its bottom surface is preferably higher than the bottom surface of the contact hole 102. The storage node contact SNC can be formed using a self-aligned contact technique, and its bottom surface will contact the adjacent active region AA to achieve electrical connection. Its sidewalls are electrically isolated from the adjacent bit line BL by a first spacer 118 and a second spacer 124. The lower half of the storage node contact SNC may partially overlap with the bit line contact BLC in the first direction D1. In this embodiment, the storage node contact SNC and the bit line contact BLC are separated by the shallow trench isolation structure STI, the gap-filling insulating layer 116, the void 120a, and the isolation oxide layer 122. Especially when a protrusion 106c is formed on the bit line contact BLC, the presence of the void 120a and the insulating oxide layer 122 can significantly improve the electrical isolation effect between the storage node contact SNC and the bit line contact BLC, and prevent bridging and short circuits between the formed storage node contact SNC and the bit line contact BLC in related processes. This will be explained in more detail in subsequent manufacturing method embodiments. The material of the storage node contact SNC can be the same as that of the bit line contact BLC, both being polycrystalline silicon. Furthermore, other components of the storage node, such as corresponding metal contact plugs and capacitors, can be electrically connected above the storage node contact SNC. Since these components are not the focus of this invention, they will not be shown in the figures to avoid obscuring important features of the invention and for the sake of simplicity.

[0022] Please now refer to Figures 3 through 10 in sequence, which show cross-sectional schematic diagrams of the manufacturing process of the DRAM with improved bit line contacts according to the embodiments of the present invention. These cross-sectional diagrams are also made with the cross-section S-S' in Figure 1, which allows the reader to understand the evolution and formation of the components and features of the DRAM in the manufacturing process.

[0023] First, please refer to Figure 3. At the beginning of the process, a semiconductor substrate 100 is provided as the basis for setting the DRAM of the present invention. The semiconductor substrate 100 may be a silicon substrate, a silicon-coated insulator (SOI) substrate, or a silicon-germanium substrate, etc. The semiconductor substrate 100 has a plurality of active regions AA, which are separated and defined by shallow trench isolation structures (STI) formed on the semiconductor substrate 100. The shallow trench isolation structure (STI) can be formed by photolithography on the semiconductor substrate 100 to form shallow trenches, and then by deposition to fill the shallow trenches with dielectric material (such as silicon oxide). The part of the semiconductor substrate 100 exposed from the shallow trench isolation structure (STI) is the active region AA, in which dopants can be doped through processes such as ion bonding or diffusion to form various doped regions (not shown) as well regions, endpoints, or channels of memory elements.

[0024] Please refer to Figure 4. Next, a first interlayer insulating layer 112 and a second interlayer insulating layer 114 are sequentially formed on the surface of the semiconductor substrate 100. The materials of the first interlayer insulating layer 112 and the second interlayer insulating layer 114 can be silicon oxide and silicon nitride, respectively, and they can be formed by a CVD process. Afterward, a contact hole 102 is formed on each active region AA. The contact hole 102 can be formed by a photolithography process. It passes through the first interlayer insulating layer 112 and the second interlayer insulating layer 114 and is recessed into the corresponding active region AA (as shown in the middle part of the active region AA in Figure 1), so that the top surface height of the active region AA is reduced, and its two sides are shallow trench isolation structures (STI).

[0025] Please refer to Figure 5. After the contact hole 102 is formed, a sacrificial layer 104 is then formed on the sidewall of the contact hole 102. In this embodiment, the sacrificial layer 104 can be formed by first forming a conformal material layer on the substrate surface through a CVD process, and then performing an etching process to remove the portion of it located outside the sidewall of the contact hole 102. In this way, the surface of the semiconductor substrate 100 and the bottom surface of the contact hole 102 will not be covered by the sacrificial layer 104, and the sacrificial layer 104 will only be formed on the sidewall of the contact hole 102. Subsequently, a polysilicon layer 106, a metal layer 108, and a hard mask layer 110 are sequentially formed on the semiconductor substrate 100. These layer structures can be formed through a suitable CVD process. The formed polysilicon layer 106 will partially fill the contact hole 102 and directly contact the underlying active region AA and the surrounding sacrificial layer 104, while the other part is located on the second interlayer insulating layer 114. The metal layer 108 can be made of titanium (Ti), titanium nitride (TiN), tungsten (W), or a multilayer structure composed of materials thereon, and the hard mask layer 110 can be made of silicon nitride. It should be noted that in this embodiment of the invention, the material of the sacrificial layer 104 has etch selectivity relative to the materials of adjacent components such as the polycrystalline silicon layer 106, the shallow trench isolation structure STI, the first interlayer insulating layer 112, and the second interlayer insulating layer 114. For example, it can be organic amorphous carbon, metal (such as tungsten W), or metal compound (such as titanium nitride TiN), which can meet the process requirements for selective removal in subsequent processes.

[0026] Please refer to Figure 6. After the above layer structure is formed, a photolithography process is then performed to pattern these layer structures, thereby forming bit lines BL and bit line contacts BLC. This photolithography process can oxidize the first interlayer insulating layer 112 of silicon material as a stop layer, so that the first interlayer insulating layer 112 on the surface of the semiconductor substrate 100 will not be removed in the photolithography process, and the second interlayer insulating layer 114 on the first interlayer insulating layer 112 is patterned into the pattern of bit lines BL. Furthermore, the patterned polysilicon layer 106 has a lower half 106a located in the contact hole 102 and an upper half 106b located above the surface height of the semiconductor substrate 100. The lower half 106a is the bit line contact BLC of the present invention, which is electrically contacted with the corresponding active region AA below. The upper half 106b, together with the upper metal layer 108, constitutes the bit line BL, part of which is located on the second interlayer insulating layer 114, and part of which is directly connected to the bit line contact BLC. The hard mask layer 110 can not only serve as a hard mask in this photolithography process, but also increase the height of the bit line portion, providing space for the subsequent storage node-related portions. It should be noted that the portion of the bit line contact BLC near the bottom may have a lateral protrusion 106c due to imperfect photolithography process, which may cause the bit line contact BLC to bridge and short-circuit with the subsequently formed storage node contact SNC. In this embodiment, due to the presence of the sacrificial layer 104, the protrusion 106c of the bit line contact BLC does not directly contact the shallow trench isolation structures STI on both sides.

[0027] Please refer to Figure 7. After the bit line BL and the bit line contact BLC are formed, a gap-filling insulating layer 116 is then formed in the remaining space of the contact hole 102, and a first spacer 118 is formed on the sidewall of the bit line BL (including the hard mask layer 110 thereon). In the embodiment, the gap-filling insulating layer 116 and the first spacer 118 can be made of silicon nitride and silicon oxide, respectively, and can be formed by a CVD process and an etch-back process. It should be noted that in the embodiment, the formed gap-filling insulating layer 116 and the first spacer 118 will not cover the sacrificial layer 104 in the contact hole 102, and the first interlayer insulating layer 112 exposed on the surface of the semiconductor substrate 100 will also be removed in the etch-back process, thus exposing the active region AA, and the sidewall of the formed first spacer 118 will be flush with the sidewall of the first interlayer insulating layer 112.

[0028] Please refer to Figure 8. After the gap-filling insulating layer 116 and the first spacer 118 are formed, the sacrificial layer 104 is then removed, thus forming a gap 120 between the bit line contact BLC, the gap-filling insulating layer 116, and the surrounding shallow trench isolation structure STI, and a portion of the bit line contact BLC (i.e., the protrusion 106c) will be exposed from the gap 120. More specifically, when the material of the sacrificial layer 104 is organic amorphous carbon, the sacrificial layer 104 can be selectively removed by an oxygen ashing process. When the material of the sacrificial layer 104 is metal, the sacrificial layer 104 can be selectively removed by using a sulfuric acid / hydrogen peroxide mixture (SPM) or an ammonium hydroxide / hydrogen peroxide mixture (APM) without damaging surrounding components.

[0029] Please refer to Figure 9. After the sacrificial layer 104 is removed, an oxygen annealing process is then performed to oxidize the portion of the bit line contact (BLC) exposed in the gap 120 into an isolation oxide layer 122. Since only the polycrystalline silicon protrusion 106c is exposed in the structure and will react with oxygen, the isolation oxide layer 122 is only formed on the exposed surface of the protrusion 106c. In this way, it can serve as a spacer for the bit line contact (BLC) together with the gap-filling insulating layer 116, and is separated from the surrounding shallow trench isolation structure (STI) by the gap 120.

[0030] Please refer to Figure 10. After the isolation oxide layer 122 is formed, a second spacer 124 is then formed on the sidewall of the bit line BL (including the hard mask layer 110 thereon). The second spacer 124 seals the gap 120 below, forming a sealed cavity 120a. The second spacer 124 can be connected to the lower gap-filling insulating layer 116 and the shallow trench isolation structure STI. Its material can be silicon nitride, and it can be formed through CVD and etch-back processes. After the second spacer 124 is formed, the storage node contact SNC is then formed on the active region AA next to the bit line contact BLC. Due to the presence of the first spacer 118 and the second spacer 124, the storage node contact (SNC) can be formed in a self-aligned manner. For example, the space defined by the first spacer 118, the second spacer 124, and other spacer structures (not shown) is filled with polysilicon material, and then an etching process is performed to lower the polysilicon material to a predetermined height (e.g., below the top surface of the second spacer 124). This completes the fabrication of the DRAM with improved bit line contacts according to the present invention.

[0031] As can be seen from the above embodiments, the present invention solves the problem of short-circuit bridging caused by process defects or excessive distance between the two contacts in the prior art by forming a sacrificial layer, voids, and an isolation oxide layer in the space between the bit line contact and the storage node contact. Simultaneously, it can reduce the parasitic capacitance of the device, making it a novel and progressive invention. The above description is only a preferred embodiment of the present invention. All equivalent variations and modifications made within the scope of the claims of this invention should be considered within the scope of this invention. [Simplified Explanation of the Diagram]

[0032] This specification includes accompanying drawings, which form part of this specification, to provide the reader with a further understanding of the embodiments of the present invention. These drawings depict some embodiments of the present invention and, together with the description herein, illustrate its principles. In these drawings: Figure 1 is a top view of a dynamic random access memory (DRAM) with improved bit-line contacts according to an embodiment of the present invention; Figure 2 is a cross-sectional view of a DRAM with improved bit-line contacts according to an embodiment of the present invention; and Figures 3 through 10 are cross-sectional views illustrating the manufacturing process of a DRAM with improved bit-line contacts according to an embodiment of the present invention. It should be noted that all illustrations in this specification are illustrative in nature. For clarity and convenience of illustration, the dimensions and proportions of the components in the illustrations may be exaggerated or reduced. Generally, the same reference numerals in the drawings are used to indicate corresponding or similar element features in modified or different embodiments.

Claims

1. A dynamic random access memory (DRAM) with improved bitline contacts, comprising: a substrate having a plurality of active regions defined by shallow trench isolation structures; a contact hole formed in each of the active regions, the contact hole being recessed into the active region and flanked by the shallow trench isolation structures; a bitline contact located in the contact hole and in direct contact with the active regions, wherein a insulating oxide layer is provided on a portion of the sidewall of the bitline contact, a gap exists between the insulating oxide layer and the shallow trench isolation structures on both sides of the contact hole, and the insulating oxide layer is exposed through the gap; a bitline located on and connected to the bitline contacts; a storage node contact located on and in direct contact with another active region adjacent to the bitline contact, wherein the storage node contact and the bitline contact are separated by the shallow trench isolation structures, the gap, and the insulating oxide layer; and a gap-filling insulating layer located between the bitline contact and the gap. A first spacer wall is located on the sidewall of the bit line and above the gap-filling insulation layer; and a storage node is located on and connected to each storage node contact.

2. A dynamic random access memory with an improved bit line contact as described in claim 1, wherein the bit line comprises a polysilicon layer, a metal layer and a hard mask layer, the portion of the polysilicon layer located in the contact hole is the bit line contact, and the portion of the polysilicon layer located outside the contact hole is the bit line.

3. The dynamic random access memory with improved bit line contacts as described in claim 2, wherein the material of the metal layer is titanium (Ti), titanium nitride (TiN), tungsten (W), or a multilayer structure composed of materials thereon.

4. A dynamic random access memory with improved bit line contacts as described in claim 2, wherein the material of the hard mask layer is silicon nitride (Si3N4).

5. A dynamic random access memory with improved bit line contacts as described in claim 2, wherein the bit line contacts and the bit lines are integrally formed from the polycrystalline silicon layer.

6. A dynamic random access memory with improved bit line contacts as described in claim 1, wherein the material of the isolation oxide layer is silicon oxide (SiO2).

7. A dynamic random access memory with improved bit line contacts as described in claim 1, wherein the material of the interstitial insulating layer is silicon nitride (Si3N4) and the material of the first spacer is silicon oxide (SiO2).

8. The dynamic random access memory with improved bit line contacts as described in claim 1, further comprising a second spacer wall located on the first spacer wall, the second spacer wall sealing the top opening of the gap.

9. A dynamic random access memory with improved bit line contacts as described in claim 8, wherein the material of the second spacer is silicon nitride (Si3N4).

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