Vertical channel transistor structure and method of manufacturing the same

Abstract

A vertical channel transistor structure includes oxide semiconductor pillars, a first electrode, a second electrode, word lines and a gate oxide layer. Each of the oxide semiconductor pillars has a top end and a bottom end. The first electrode is disposed under and connected to the top end of each of the oxide semiconductor pillars, and the second electrode is disposed on and connected to the bottom end of each of the oxide semiconductor pillars. The word lines are disposed at different heights of the oxide semiconductor pillars. The gate oxide layer is dispose between each of the oxide semiconductor pillars and each of the word lines.

Description

[Technical Field]

[0001] This invention relates to a semiconductor device, and more particularly to a vertical channel transistor structure and a method for manufacturing the same. [Previous Technology]

[0002] In order to continue the development path of DRAM below 10nm, it is proposed to replace the 6F2 unit cell structure with a 4F2 unit cell structure of vertical channel / pillar transistor (VCT / VPT) to meet the requirements of high density and low cost.

[0003] However, interference from adjacent word lines (WL) is a weakness of the VCT / VPT transistors in 4F2DRAM, and can cause RETH problems after frequent operation of adjacent WL. Therefore, due to the small WL-WL spacing (poor coupling effect), it is difficult to reduce the size of the next-generation 4F2DRAM cell. [Summary of the Invention]

[0004] The present invention provides a vertical channel transistor structure and its fabrication method to reduce the WL-WL coupling effect and increase the feasibility of reducing the unit cell size in 4F2DRAM.

[0005] A vertical channel transistor structure according to one embodiment of the present invention includes a plurality of oxide semiconductor pillars, a first electrode, a second electrode, a plurality of word lines, and a gate oxide layer. Each of the plurality of oxide semiconductor pillars has a top end and a bottom end. The first electrode is disposed below and connected to the bottom end of the plurality of oxide semiconductor pillars. The second electrode is disposed above and connected to the top end of the plurality of oxide semiconductor pillars. The plurality of word lines are disposed at different heights of the plurality of oxide semiconductor pillars. The gate oxide layer is disposed between each of the plurality of oxide semiconductor pillars and each of the plurality of word lines.

[0006] In one embodiment of the present invention, one character line and another adjacent character line are disposed at different heights of the oxide semiconductor pillar.

[0007] In one embodiment of the present invention, the minimum distance between one of the character lines and the other character line adjacent to it is greater than the horizontal distance between one of the character lines and the other character line adjacent to it.

[0008] In one embodiment of the present invention, in the cross-sectional view, the shape of each character line is trapezoidal.

[0009] In one embodiment of the present invention, in a cross-sectional view, each oxide semiconductor pillar is inverted trapezoidal in shape.

[0010] In one embodiment of the present invention, one of the plurality of character lines surrounds a set of oxide semiconductor pillars along a direction parallel to the plane, and the oxide semiconductor pillars are arranged perpendicular to the plane.

[0011] A method for manufacturing a vertical channel transistor structure according to another embodiment of the present invention includes the following steps: A plurality of first electrodes are formed on a substrate. A first word line is formed at a first height above the first electrodes. A second word line is formed at a second height above the first electrodes, wherein the first height and the second height are different. A plurality of channel holes are formed, respectively penetrating the first word line and the second word line. A gate oxide layer is formed on the sidewall of each channel hole. A plurality of oxide semiconductor pillars are formed in the plurality of channel holes. A plurality of second electrodes are formed on the plurality of oxide semiconductor pillars.

[0012] In another embodiment of the present invention, the first height is higher than the second height, or the first height is lower than the second height.

[0013] In another embodiment of this disclosure, the method of forming a first character line includes forming a first insulating layer on a plurality of first electrodes, depositing a conductive material layer on the first insulating layer, forming a first patterned mask on the conductive material layer, and using the first patterned mask as an etch mask to etch back the conductive material layer.

[0014] In another embodiment of this disclosure, the method of forming the second character line includes forming a second insulating layer above the first character line, depositing a conductive material layer on the second insulating layer, forming a second patterned mask on the conductive material layer, and using the second patterned mask as an etching mask to etch back the conductive material layer.

[0015] In another embodiment of the present invention, the method of forming a plurality of channel holes includes forming a third insulating layer on the second character line, forming a third patterned mask on the third insulating layer, using the third patterned mask as an etching mask, etching the third insulating layer, the second character line and the first character line until the plurality of first electrodes are exposed.

[0016] In another embodiment of the invention, the third patterned mask has a first opening aligned with the first character line.

[0017] In another embodiment of the invention, the third patterned mask has a second opening aligned with the second character line.

[0018] Based on the above, the vertical channel transistor structure according to the present invention reduces the WL-WL coupling effect by setting multiple word lines at different heights. At the same time, the present invention also increases the feasibility of reducing the unit cell size in 4F2DRAM.

[0019] In order to make the above features of the present invention more obvious and understandable, specific embodiments are given below, and detailed descriptions are provided in conjunction with the accompanying drawings.

Implementation Method

[0020] The present invention can be understood by referring to the following detailed description in conjunction with the accompanying drawings. However, the present invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, for clarity and explicitness, the dimensions of each layer and region and their relative dimensions may not be shown to exact scale.

[0021] FIG1 is a top view of a plurality of vertical channel transistor structures according to some embodiments of the present invention, and FIG2 is a cross-sectional view taken along XX of FIG1. ​​For clarity, some components in FIG1, such as the second electrode 102 and the upper part of the insulating layer 108 in FIG2, are not shown.

[0022] Referring now to Figures 1 and 2, each vertical channel transistor structure 100 includes a plurality of oxide semiconductor pillars OS, a first electrode 104, a second electrode 102, a plurality of word lines WL1-WL2, and a gate oxide layer 106. Each oxide semiconductor pillar OS has a top OSt and a bottom OSb. The first electrode 104 is disposed below and connected to the bottom OSb of each oxide semiconductor pillar OS. The second electrode 102 is disposed on and connected to the top OSt of each oxide semiconductor pillar OS. In some embodiments, the oxide semiconductor pillars OS are vertically disposed above the substrate 110. In some embodiments, the material of the oxide semiconductor pillars OS can be at least one of indium gallium zinc oxide (IGZO), manganese oxide (MnO2), zinc oxide (ZnO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc., and the present invention does not impose any limitations on this.

[0023] Character lines WL1-WL2 are disposed at different heights of the oxide semiconductor pillar OS. The term "height" used in this embodiment may also refer to the vertical distance from the same object, such as the substrate 110 or the first electrode 104. In other words, character lines WL1-WL2 can be considered as a double layer of WL. In some embodiments, one of the character lines (e.g., character line WL1) and the adjacent character line (e.g., character line WL2) are disposed at different heights of the oxide semiconductor pillar OS. In some embodiments, the minimum distance s1 between character lines WL1 and WL2 is longer than the horizontal distance s2 between character lines WL1 and WL2. The horizontal distance s2 is the spacing between character lines WL1 and WL2 along the XX line. This invention increases the distance between word lines WL1 and WL2 by placing them at different heights, thereby reducing WL-WL coupling (neighboring WL interference) effects or increasing the feasibility of reducing the unit cell size in 4F2 DRAM. In the cross-sectional view of Figure 2, each word line WL1-WL2 is a rectangle with vertical edges.

[0024] In FIG. 1, one of the word lines WL1 or WL2 surrounds a set of oxide semiconductor pillars OS along a direction parallel to a plane (substrate 110 of FIG. 2), and the oxide semiconductor pillars OS are disposed perpendicular to the plane. A gate oxide layer 106 is disposed between each oxide semiconductor pillar OS and each word line WL1-WL2. In some embodiments, the vertical channel transistor structure 100 further includes an insulating layer 108, the material of which may include oxide or other suitable insulating material. The oxide semiconductor pillars OS, the gate oxide layer 106, and the word lines WL1-WL2 may be disposed in the insulating layer 108. In some embodiments, the gate oxide layer 106 is also disposed between each oxide semiconductor pillar OS and the insulating layer 108.

[0025] FIG3 is a cross-sectional view of a vertical channel transistor structure according to some embodiments of the present invention, wherein the same element symbols as in the previous embodiment are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content of the previous embodiment, and will not be repeated here.

[0026] In Figure 3, the vertical channel transistor structure 300 has word lines WL1' and WL2', and both word lines WL1' and WL2' are trapezoidal in shape. This trapezoidal structure is obtained through natural etching characteristics, and the minimum distance s3 between word lines WL1' and WL2' can be greater than the minimum distance in the above embodiment (as shown by the minimum distance s1 in Figure 2). In other words, the vertical channel transistor structure 300 may be superior to the previous embodiment in reducing the WL-WL coupling effect.

[0027] Figures 4A to 4H are cross-sectional views of the manufacturing process of a vertical channel transistor structure according to some embodiments of the present invention.

[0028] Referring to FIG4A, a plurality of first electrodes 402 are formed on a substrate 400. A first insulating layer 404 may be formed on the first electrodes 402, and then a conductive material layer 406 may be deposited on the first insulating layer 404. In some embodiments, the first insulating layer 404 may be an oxide or other suitable material. A first patterned mask PM1 is formed on the conductive material layer 406 to expose a portion of the conductive material layer 406. In some embodiments, the first patterned mask PM1 may be a patterned photoresist formed by a photolithography process.

[0029] Referring to Figure 4B, the conductive material layer 406 in Figure 4A is etched back using the first patterned mask PM1 in Figure 4A as an etching mask, thereby forming the first character line WL1 at a first height h1 above the first electrode 402. Due to the etching characteristics, the outlines of the two adjacent first character lines WL1 and the first insulating layer 404 between them present an inverted trapezoidal shape. The first patterned mask PM1 in Figure 4A will be removed later.

[0030] Referring to FIG4C, a second insulating layer 408 is formed on the first character line WL1, and then another conductive material layer 410 is deposited on the second insulating layer 408 above the first character line WL1. In some embodiments, the method of forming the second insulating layer 408 includes depositing oxide to fill the gaps and cover the first character line WL1, and then performing CMP (chemical mechanical polishing). A second patterned mask PM2 is formed on the conductive material layer 410 to expose a portion of the conductive material layer 410. In some embodiments, the second patterned mask PM2 may be a patterned photoresist formed by a photolithography process.

[0031] Referring to FIG4D, the conductive material layer 410 in FIG4C is etched back using the second patterned mask PM2 in FIG4C as an etching mask to form a second character line WL2 at a second height h2 above the first electrode 402, wherein the first height h1 is different from the second height h2. In this embodiment, the first height h1 is shorter than the second height h2. Due to the etching characteristics, the outlines of the two adjacent second character lines WL2 and the second insulating layer 408 between them present an inverted trapezoidal shape. The second patterned mask PM2 in FIG4C will be removed later.

[0032] Referring to FIG4E, a third insulating layer 412 is formed on the second character line WL2. In some embodiments, the method of forming the third insulating layer 412 includes depositing oxide to fill the gap and cover the second character line WL2, and then performing CMP.

[0033] Referring to FIG4F, a third patterned mask PM3 is formed on the third insulating layer 412. In some embodiments, the third patterned mask PM3 may be a patterned photoresist formed via a photolithography process. The third patterned mask PM3 has a first opening O1 aligned with the first character line WL1. The third patterned mask PM3 has a second opening O2 aligned with the second character line WL2.

[0034] Referring to Figure 4G, the third patterned mask PM3 in Figure 4F is used as an etching mask to etch the third insulating layer 412, the second character line WL2, the second insulating layer 408, and the first character line WL1 until the first electrode 402 is exposed, thereby forming a plurality of channel holes HO that respectively penetrate the first character line WL1 and the second character line WL2. After removing the third patterned mask PM3 in Figure 4F, a gate oxide layer 414 is formed on the sidewall of the channel holes HO, and then a plurality of oxide semiconductor pillars OS are formed in the channel holes HO. The oxide semiconductor pillars OS can be in direct contact with the first electrode 402. In some embodiments, each oxide semiconductor pillar OS is inverted trapezoidal in shape.

[0035] Referring to Figure 4H, a plurality of second electrodes 416 are formed on the oxide semiconductor pillar OS.

[0036] In summary, from a process perspective, the feasibility of a two-layer WLs process is achievable. Moreover, from an electrical perspective, WL-WL coupling can be further reduced.

[0037] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0038] FIG1 is a top view of multiple vertical channel transistor structures according to some embodiments of the present invention. FIG2 is a cross-sectional view of the vertical channel transistor structure of FIG1. ​​FIG3 is a cross-sectional view of the vertical channel transistor structure according to some embodiments of the present invention. FIG4A to FIG4H are cross-sectional views of the manufacturing process of the vertical channel transistor structure according to some embodiments of the present invention.

Claims

1. A vertical channel transistor structure, comprising: A plurality of oxide semiconductor pillars, wherein each of the oxide semiconductor pillars has a top end and a bottom end; A first electrode is disposed below and connected to the bottom end of each of the oxide semiconductor pillars; A second electrode is disposed above and connected to the top of each of the oxide semiconductor pillars; Multiple character lines are disposed at different heights of the multiple oxide semiconductor pillars, wherein, in a cross-sectional view, each character line is trapezoidal in shape; and a gate oxide layer is disposed between each oxide semiconductor pillar and each character line.

2. The vertical channel transistor structure as claimed in claim 1, wherein one of the plurality of word lines and another of the plurality of word lines adjacent thereto are disposed at different heights of the plurality of oxide semiconductor pillars.

3. The vertical channel transistor structure as claimed in claim 2, wherein the minimum distance between one of the plurality of character lines and another of the plurality of character lines adjacent to it is greater than the horizontal distance between one of the plurality of character lines and another of the plurality of character lines adjacent to it.

4. The vertical channel transistor structure as claimed in claim 1, wherein one of the plurality of character lines surrounds a set of the plurality of oxide semiconductor pillars in a direction parallel to the plane, and the plurality of oxide semiconductor pillars are disposed perpendicular to the plane.

5. A vertical channel transistor structure, comprising: A plurality of oxide semiconductor pillars, each of the oxide semiconductor pillars having a top end and a bottom end, wherein, in a cross-sectional view, each oxide semiconductor pillar is inverted trapezoidal in shape; a first electrode disposed below and connected to the bottom end of each oxide semiconductor pillar; a second electrode disposed above and connected to the top end of each oxide semiconductor pillar; a plurality of word lines disposed at different heights of the plurality of oxide semiconductor pillars; and a gate oxide layer disposed between each oxide semiconductor pillar and each word line.

6. The vertical channel transistor structure as claimed in claim 5, wherein one of the plurality of word lines and another of the plurality of word lines adjacent thereto are disposed at different heights of the plurality of oxide semiconductor pillars.

7. The vertical channel transistor structure as claimed in claim 6, wherein the minimum distance between one of the plurality of character lines and another of the plurality of character lines adjacent to it is greater than the horizontal distance between one of the plurality of character lines and another of the plurality of character lines adjacent to it.

8. The vertical channel transistor structure as claimed in claim 5, wherein one of the plurality of character lines surrounds a set of the plurality of oxide semiconductor pillars in a direction parallel to the plane, and the plurality of oxide semiconductor pillars are disposed perpendicular to the plane.

9. A method for manufacturing a vertical channel transistor structure, comprising: Multiple first electrodes are formed on the substrate; A first character line is formed at a first height above the first electrode; A second character line is formed at a second height above the first electrode, wherein the first height is different from the second height; a plurality of channel holes are formed, respectively penetrating the first character line and the second character line; a gate oxide layer is formed on the sidewall of each of the channel holes; a plurality of oxide semiconductor pillars are formed in the plurality of channel holes; and a plurality of second electrodes are formed on the plurality of oxide semiconductor pillars.

10. A method of manufacturing a vertical channel transistor structure as claimed in claim 9, wherein the first height is higher than the second height.

11. A method for manufacturing a vertical channel transistor structure as claimed in claim 9, wherein the method for forming the first word line comprises: A first insulating layer is formed on the plurality of first electrodes; A conductive material layer is deposited on the first insulating layer; A first patterned mask is formed on the conductive material layer; And using the first patterned mask as an etching mask, the conductive material layer is etched back.

12. A method for manufacturing a vertical channel transistor structure as claimed in claim 9, wherein the method for forming the second character line comprises: A second insulating layer is formed on the first character line; A conductive material layer is deposited on the second insulating layer; A second patterned mask is formed on the conductive material layer; And using the second patterned mask as an etching mask, the conductive material layer is etched back.

13. A method for manufacturing a vertical channel transistor structure as claimed in claim 9, wherein the method for forming the plurality of channel holes includes: A third insulating layer is formed on the second character line; A third patterned mask is formed on the third insulating layer; And using the third patterned mask as an etching mask, the third insulating layer, the second character line and the first character line are etched until the plurality of first electrodes are exposed.

14. A method of manufacturing a vertical channel transistor structure as claimed in claim 13, wherein the third patterned mask has a first opening aligned with the first character line.

15. A method of manufacturing a vertical channel transistor structure as claimed in claim 13, wherein the third patterned mask has a second opening aligned with the second character line.

Images