Memory device and manufacturing method thereof

Abstract

A memory device includes: a cell semiconductor layer respectively including sub-cell regions arranged in a first direction, and contact regions between the sub-cell regions, wherein the sub-cell regions include memory cells; and a circuit semiconductor layer on the cell semiconductor layer and including a circuit configured to control the memory cells. The cell semiconductor layer includes: sub-wordlines extending in the first direction from the sub-cell regions to adjacent contact regions; odd wordline interconnection lines extending from an odd sub-cell region to adjacent contact regions; and even wordline interconnection lines extending from an even sub-cell region to the adjacent contact regions.

Images