Memory device

Abstract

A memory device includes a substrate, a stacked structure, first slits and second slits. The substrate has a memory array region and a staircase region. The stacked structure includes a first gate stacked structure and second gate stacked structures. The first gate stacked structure is located over the memory array region, and the second gate stacked structures are located over the staircase region. The first and the second gate stacked structures include gate layers and first insulating layers stacked alternately. The first slits and second slits are arranged alternatively in a first direction and extending in a second direction. The first slit includes a first sub-slit extending over the staircase region and a second sub-slit extending over the memory array region, and a spacer is between the first and the second sub-slit. The second slits extend from over the memory array region to over the staircase region.

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