Memory device

Abstract

A memory device includes a substrate, a buffer layer, a stacked structure, and a channel pillar. The buffer layer is on the substrate. The stacked structure is located on the buffer layer, in which the stacked structure includes a plurality of gate layers and a plurality of first insulating layers stacked alternately. The channel pillar extends through the stacked structure and is embedded in the buffer layer, in which the channel pillar includes a charge storage structure and a channel layer, the charge storage structure is located between the plurality of gate layers and the channel pillar.

Description

[Technical Field]

[0001] This disclosure and some embodiments relate to a memory element. [Previous Technology]

[0002] Non-volatile memory has the advantage that stored data will not be lost after power failure, and is therefore widely used in personal computers and other electronic devices. Currently, the most commonly used three-dimensional memory in the industry includes NOR memory and NAND memory. In addition, another type of three-dimensional memory is AND memory, which can be used in multi-dimensional memory arrays, offering high integration density and high area utilization, as well as fast operating speed. Therefore, the development of three-dimensional memory devices has gradually become a current trend. [Summary of the Invention]

[0003] A memory element according to some embodiments of this disclosure includes a substrate, a buffer layer, a gate stack structure, and a channel pillar. The buffer layer is on the substrate. The gate stack structure is located on the buffer layer, wherein the gate stack structure includes a plurality of gate layers and a plurality of first insulating layers stacked alternately on top of each other. The channel pillar extends through the gate stack structure and is embedded in the buffer layer, wherein the channel pillar includes a charge storage structure and a channel layer, the charge storage structure being located between the gate layer and the channel layer.

Implementation Method

[0004] Figure 1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments. Figure 1B shows a partial three-dimensional view of a portion of the memory array in Figure 1A. Figures 1C and 1D show cross-sectional views along tangent I-I' of Figure 1B. Figure 1E shows a top view along tangent II-II' of Figures 1B, 1C, and 1D.

[0005] Figure 1A is a schematic diagram of two blocks BLOCK(i) and BLOCK(i+1) comprising a vertical AND memory array 10 configured in columns and rows. Block BLOCK(i) includes memory array A(i). A column of memory array A(i) (e.g., the (m+1)th column) is a set of AND memory cells 20 having a common word line (e.g., WL(i)m+1). The AND memory cells 20 of each column (e.g., the (m+1)th column) of memory array A(i) correspond to the common word line (e.g., WL(i)m+1) and are coupled to different source pillars (e.g., SP(i)n and SP(i)n+1) and drain pillars (e.g., DP(i)n and DP(i)n+1), thereby making the AND memory cells 20 logically configured in a column along the common word line (e.g., WL(i)m+1).

[0006] A row (e.g., the nth row) of memory array A(i) is a set of AND memory cells 20 having a common source pillar (e.g., SP(i)n) and a common drain pillar (e.g., DP(i)n). Each row (e.g., the nth row) of memory array A(i) has AND memory cells 20 corresponding to different word lines (e.g., WL(i)m+1 and WL(i)m) and coupled to a common source pillar (e.g., SP(i)n) and a common drain pillar (e.g., DP(i)n). Therefore, the AND memory cells 20 of memory array A(i) are logically arranged in a row along the common source pillar (e.g., SP(i)n) and the common drain pillar (e.g., DP(i)n). In a physical layout, depending on the manufacturing method applied, rows or columns may be twisted, configured in a honeycomb pattern, or otherwise for high density or other reasons.

[0007] In Figure 1A, in block BLOCK (i), the AND memory cells 20 in the nth row of memory array A (i) share a common source pillar (e.g., SP (i)n) and a common drain pillar (e.g., DP (i)n). The AND memory cells 20 in the (n+1)th row share a common source pillar (e.g., SP (i)n+1) and a common drain pillar (e.g., DP (i)n+1).

[0008] A common source terminal (e.g., SP(i)n) is coupled to a common source line (e.g., SLn); a common drain terminal (e.g., DP(i)n) is coupled to a common bit line (e.g., BLn). A common source terminal (e.g., SP(i)n+1) is coupled to a common source line (e.g., SLn+1); a common drain terminal (e.g., DP(i)n+1) is coupled to a common bit line (e.g., BLn+1).

[0009] Similarly, block BLOCK (i+1) includes memory array A (i+1), which is similar to memory array A (i) in block BLOCK (i). A column of memory array A (i+1) (e.g., the (m+1)th column) is a set of AND memory cells 20 having a common word line (e.g., WL (i+1)m+1). The AND memory cells 20 of each column (e.g., the (m+1)th column) of memory array A (i+1) correspond to a common word line (e.g., WL (i+1)m+1) and are coupled to different source pillars (e.g., SP (i+1)n and SP (i+1)n+1) and drain pillars (e.g., DP (i+1)n and DP (i+1)n+1). A row (e.g., the nth row) of memory array A(i+1) is a set of AND memory cells 20 having a common source (e.g., SP(i+1)n) and a common drain (e.g., DP(i+1)n). Each row (e.g., the nth row) of memory array A(i+1) has AND memory cells 20 corresponding to different word lines (e.g., WL(i+1)m+1 and WL(i+1)m) and coupled to a common source (e.g., SP(i+1)n) and a common drain (e.g., DP(i+1)n). Therefore, the AND memory cells 20 of memory array A(i+1) are logically arranged in a row along the common source (e.g., SP(i+1)n) and the common drain (e.g., DP(i+1)n).

[0010] Block (i+1) shares source lines (e.g., SL n and SL n+1) and bit lines (e.g., BL n and BL n+1) with block (i). Therefore, source line SL n and bit line BL n are coupled to the nth row of AND memory cell 20 in the AND memory array A (i) of block (i), and are also coupled to the nth row of AND memory cell 20 in the AND memory array A (i+1) of block (i). Similarly, source line SL n+1 and bit line BL n+1 are coupled to the (n+1)th row of AND memory cell 20 in the AND memory array A (i) of block (i), and are also coupled to the (n+1)th row of AND memory cell 20 in the AND memory array A (i+1) of block (i).

[0011] Referring to Figures 1B to 1D, the memory array 10 may be disposed on the interconnect structure of a semiconductor die, such as above one or more active elements (e.g., transistors) formed on a semiconductor substrate. Therefore, the dielectric substrate 50 is, for example, a dielectric layer, such as a silicon oxide layer, formed above the metal interconnect structure on a silicon substrate. The memory array 10 may include a gate stack structure 52 and a plurality of channel pillars VC.

[0012] Referring to Figure 1B, a gate stack structure 52 is formed on a dielectric substrate 50 of an array region (not shown) and a stepped region (not shown). The gate stack structure 52 includes a plurality of gate layers (also called word lines) 38 vertically stacked on the surface 50s of the dielectric substrate 50 and multiple layers of insulating layers 54. In the Z direction, these gate layers 38 are electrically isolated from each other by insulating layers 54 disposed between them. The gate layers 38 extend in a direction parallel to the surface of the dielectric substrate 50. The gate layers 38 in the stepped region may have a stepped structure (not shown). Therefore, the lower gate layer 38 is longer than the upper gate layer 38, and the end of the lower gate layer 38 extends laterally beyond the end of the upper gate layer 38. Contact windows (not shown) for connecting the gate layers 38 may land at the ends of the gate layers 38 to connect each gate layer 38 to a respective conductor.

[0013] Referring to Figures 1B to 1D, the memory array 10 also includes a plurality of channel pillars VC, and the channel pillars VC contain channel layers 16. The channel layers 16 extend continuously through the gate stack structure 52. In some embodiments, the channel layers 16 may have a ring-shaped profile when viewed from a top angle. The material of the channel layers 16 may be a semiconductor, such as undoped polysilicon.

[0014] Referring to Figures 1B to 1D, the channel pillar VC also includes an isolation pillar 28, a first conductor pillar 32a, and a second conductor pillar 32b. In this example, the first conductor pillar 32a serves as the source pillar; the second conductor pillar 32b serves as the drain pillar. The first conductor pillar 32a, the second conductor pillar 32b, and the isolation pillar 28 each extend in a direction perpendicular to the surface of the gate layer 38 (i.e., the XY plane) (i.e., the Z direction). The first conductor pillar 32a and the second conductor pillar 32b are separated by the isolation pillar 28. The first conductor pillar 32a and the second conductor pillar 32b are electrically connected to the channel layer 16. The first conductor pillar 32a and the second conductor pillar 32b comprise doped polycrystalline silicon or metallic materials. The isolation pillar 28 is, for example, silicon nitride or silicon oxide.

[0015] Referring to Figures 1C and 1D, a charge storage structure 40 is disposed between the channel layer 16 and the multilayer gate layer 38. The charge storage structure 40 may include a tunneling layer (or bandgap engineered tunneling oxide layer) 14, a charge storage layer 12, and a barrier layer 36. The charge storage layer 12 is located between the tunneling layer 14 and the barrier layer 36. In some embodiments, the tunneling layer 14 and the barrier layer 36 comprise silicon oxide. The charge storage layer 12 comprises silicon nitride, or other materials capable of capturing charges. In some embodiments, as shown in Figure 1C, a portion of the charge storage structure 40 (the tunneling layer 14 and the charge storage layer 12) extends continuously in a direction perpendicular to the gate layer 38 (i.e., the Z direction), while another portion of the charge storage structure 40 (the barrier layer 36) surrounds the gate layer 38. In other embodiments, as shown in Figure 1D, the charge storage structure 40 (tunneling layer 14, charge storage layer 12, and barrier layer 36) surrounds the gate layer 38.

[0016] Referring to Figure 1E, the charge storage structure 40, the channel layer 16, and the source posts 32a and drain posts 32b are surrounded by the gate layer 38, defining the memory cell 20. The memory cell 20 can be operated in 1-bit or 2-bit manner using different operating methods. For example, when a voltage is applied to the source posts 32a and drain posts 32b, since the source posts 32a and drain posts 32b are connected to the channel layer 16, electrons can be transported along the channel layer 16 and stored in the entire charge storage structure 40, thus enabling 1-bit operation of the memory cell 20. Furthermore, for operations utilizing Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge storage structure 40 between the source posts 32a and drain posts 32b. For source-side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection operations, electrons or holes can be locally trapped in the charge storage structure 40 of one of the two adjacent source posts 32a and drain posts 32b, thus enabling unit cell (SLC, 1-bit) or multi-cell (MLC, greater than or equal to 2-bit) operations on the memory cell 20.

[0017] During operation, when a voltage is applied to the selected word line (gate layer) 38, for example, when a corresponding starting voltage (Vth) higher than that of the corresponding memory cell 20 is applied, the channel region of the channel layer 16 intersecting the selected word line 38 is turned on, allowing current to enter the drain post 32b from the bit line BL n or BL n+1 (shown in Figure 1B), and flow through the turned-on channel region to the source post 32a (e.g., in the direction indicated by arrow 60), and finally to the source line SL n or SL n+1 (shown in Figure 1B).

[0018] Figures 2 to 14 are cross-sectional schematic diagrams of a manufacturing process of a 3D AND flash memory element according to an embodiment of the present disclosure.

[0019] Referring to Figure 2, a substrate 100, a buffer layer 101, and a conductor layer 102 are provided. The substrate 100 is, for example, a silicon substrate. The material of the buffer layer 101 may be silicon oxide. The conductor layer 102 is, for example, a grounded polycrystalline silicon layer. The conductor layer 102 may also be referred to as a dummy gate, which can be used to close the leakage path. The substrate 100 includes an array region and a step region. A stacked structure SK is formed on the array region and the step region of the substrate 100 and on the conductor layer 102, and the stacked structure SK is patterned to form a step structure in the step region. The stacked structure SK may also be referred to as an insulating stacked structure SK. In this embodiment, the stacked structure SK is composed of an insulating layer 104 and an intermediate layer 106 sequentially and alternately stacked on the conductor layer 102. Furthermore, in this embodiment, the uppermost layer of the stacked structure SK is the insulating layer 104. The insulating layer 104 is, for example, a silicon oxide layer. The intermediate layer 106 is, for example, a silicon nitride layer. The intermediate layer 106 will be partially removed in subsequent processes. The number of insulating layers 104 and intermediate layers 106 can be determined according to actual needs.

[0020] The thickness of the buffer layer 101 disclosed herein is designed such that when trenches are subsequently formed in the stacked structure SK, the width of the trenches in the stacked structure SK is substantially uniform along the vertical direction to avoid poor contact between the source pillars (or drain pillars) subsequently formed in the trenches and the channel layer. In some embodiments, the thickness T1 of the buffer layer 101 is at least 30% of the thickness T2 of the stacked structure SK. In some embodiments, the thickness T1 of the buffer layer 101 does not exceed 300% of the thickness T2 of the stacked structure SK. When the thickness T1 of the buffer layer is less than the thickness disclosed above, the subsequently formed channel trenches (e.g., channel trench 108 in Figure 3) may completely penetrate the buffer layer 101, thereby damaging the underlying dielectric substrate 100. When the thickness T1 of the buffer layer is greater than the thickness disclosed above, it may easily cause warping of the substrate 100, resulting in uneven thickness of the deposited layer above the substrate 100 and the buffer layer 101.

[0021] Next, referring to Figure 3, a plurality of channel trenches 108 are formed in the stacked structure SK of the array region. The channel trenches 108 extend through the stacked structure SK and the conductor layer 102 and penetrate into the buffer layer 101. In this embodiment, the channel trenches 108 have a circular outline when viewed from the above perspective, but the invention is not limited thereto. In other embodiments, the channel trenches 108 may have other shapes, such as elliptical or polygonal (not shown).

[0022] In this disclosure, the channel trench 108 is formed in the stacked structure SK by an etching process with high power and low selectivity. The high-power etching process is a dry etching process performed on the stacked structure SK, conductor layer 102, and buffer layer 101, such that the etching process has low selectivity for the intermediate layer 106 and insulating layer 104, conductor layer 102, and buffer layer 101 in the stacked structure SK. Therefore, the channel trench 108 penetrates the stacked structure SK and conductor layer 102, and the channel trench 108 exposes the buffer layer 101. The channel trench 108 formed using this etching process has sidewalls substantially perpendicular to the bottom surface of the buffer layer 101. Therefore, the width of the channel trench 108 is substantially uniform from bottom to top. In some embodiments, the thickness T1 of the buffer layer 101 is at least 30% of the thickness T2 of the stacked structure SK. In some embodiments, the thickness T1 of the buffer layer 101 does not exceed 300% of the thickness T2 of the stacked structure SK. When the thickness T1 of the buffer layer is less than the thickness disclosed above, the channel trench 108 may completely penetrate the buffer layer 101, thereby damaging the underlying dielectric substrate 100. When the thickness T1 of the buffer layer is greater than the thickness disclosed above, it may easily cause warping of the substrate 100, resulting in uneven thickness of the deposited layer above the substrate 100 and the buffer layer 101. In some embodiments, the power of this etching process is between 20 kHz and 400 kHz.

[0023] Next, referring to Figure 4, a protective layer 110, a charge storage structure 140, and a channel layer 116 are formed on the sidewall of the channel trench 108. The protective layer 110 is, for example, a silicon oxide layer. The charge storage structure 140 may include a tunneling layer (such as tunneling layer 14 in Figure 1C), a charge storage layer (such as charge storage layer 12 in Figure 1C), and a barrier layer (such as barrier layer 36 in Figure 1C). The tunneling layer is, for example, silicon oxide. The charge storage layer is, for example, silicon nitride. The barrier layer is, for example, silicon oxide or a material with a high dielectric constant greater than or equal to 7, such as aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), lanthanum oxide (La₂O₅), transition metal oxides, lanthanide oxides, or combinations thereof. The material of the channel layer 116 may be a semiconductor, such as undoped polycrystalline silicon. The protective layer 110 is formed by methods such as thermal oxidation, chemical vapor deposition, or atomic layer deposition. The charge storage structure 140 and the channel layer 116 are formed, for example, by forming a charge storage structure material, a channel material, and a spacer wall material on the stacked structure SK and within the channel trench 108. Then, an etch-back process is performed to locally remove the charge storage structure material, the channel material, and the spacer wall material to form the charge storage structure 140, the channel layer 116, and a spacer wall (not shown). The protective layer 110, the charge storage structure 140, and the channel layer 116 cover the sidewalls of the channel trench 108, exposing the bottom of the channel trench 108. The protective layer 110, the charge storage structure 140, and the channel layer 116 may extend through the stacked structure SK and into the buffer layer 101. The channel layer 116 is, for example, annular in its top view. In some embodiments, the channel layer 116 may have a circular outline when viewed from a top angle, but this disclosure is not limited thereto. In other embodiments, the channel layer 116 may also have other shapes (e.g., elliptical or polygonal) when viewed from a different angle. The gap walls will be removed in subsequent processes.

[0024] Next, referring to Figure 5, insulating filler material is filled into the stacked structure SK and the channel trench 108. The insulating filler material is, for example, low-temperature silicon oxide or high-temperature silicon oxide. The insulating filler material filled into the channel trench 108 forms an insulating filler layer 124, leaving a circular hole in the center of the insulating filler layer 124. Then, an anisotropic etching process is performed to enlarge the circular hole to form a hole 109. In this embodiment, the hole 109 extends through the conductor layer 102, and its bottom surface is located between the top and bottom surfaces of the buffer layer 101.

[0025] Next, referring to Figure 6, an insulating material layer is formed on the insulating fill layer 124 and in the via 109. Then, an anisotropic etching process is performed to remove a portion of the insulating material layer to form isolation pillars 128 in the via 109. The isolation pillars 128 are formed between the channel layers 116. The material of the isolation pillars 128 is different from the material of the insulating fill layer 124. The material of the isolation pillars 128 is, for example, silicon nitride.

[0026] Next, referring to Figure 7, a patterning process is performed to form holes 130a and 130b in the insulating fill layer 124. The outlines of holes 130a and 130b may be tangent to the outline of the isolation pillar 128. The outlines of holes 130a and 130b may also extend beyond the outline of the isolation pillar 128. The outlines of holes 130a and 130b may be tangent to the outline of the channel layer 116. The outlines of holes 130a and 130b may also extend beyond the outline of the channel layer 116. That is, the sidewalls of the formed holes 130a and 130b can expose a portion of the isolation pillar 128 and the channel layer 116. In this disclosure, holes 130a and 130b are formed in the insulating fill layer 124 by a dry etching process with high power and low selectivity. The holes 130a and 130b formed using this etching process have sidewalls substantially perpendicular to the bottom surface of the buffer layer 101. Therefore, the widths of holes 130a and 130b are substantially the same from bottom to top. In other words, the sidewalls of holes 130a and 130b expose a portion of the isolation pillars 128 and the channel layer 116 from bottom to top. In some embodiments, the power of this etching process is between 20 kHz and 400 kHz.

[0027] Next, referring to Figure 8, conductor pillars 132a and 132b are formed in holes 130a and 130b. Conductor pillars 132a and 132b can serve as source pillars and drain pillars, respectively. Conductor pillars 132a and 132b are formed in and electrically connected to channel layer 116, and are separated by isolation pillars 128. The conductor pillars 132a and 132b are formed, for example, by forming a conductor material on insulating fill layer 124 and in holes 130a and 130b, and then forming them by an etch-back process. The material of conductor pillars 132a and 132b is, for example, doped polysilicon. At this point, channel pillars VC can be formed in channel trench 108 (see Figure 6). Channel pillars VC extend through stacked structure SK and are embedded in buffer layer 101. The channel pillar VC may include a charge storage structure 140, a channel layer 116, an isolation pillar 128, and conductor pillars 132a and 132b.

[0028] In this disclosure, since the widths of holes 130a and 130b are substantially the same from bottom to top, a portion of the isolation pillar 128 and the channel layer 116 are exposed on the sidewalls of holes 130a and 130b from bottom to top. As a result, the conductor pillars 132a and 132b formed in holes 130a and 130b contact the channel layer 116 from bottom to top. In other words, since the widths of conductor pillars 132a and 132b are substantially the same from bottom to top, even the sidewalls at the ends of conductor pillars 132a and 132b will contact the channel layer 116, and the sidewalls at the ends of the charge storage structure 140 will contact conductor pillars 132a and 132b. Problems of poor contact between conductor pillar 132a (or conductor pillar 132b) and the channel layer 116 can be reduced. Furthermore, the sidewalls at the ends of the isolation pillar 128 also contact conductor pillars 132a and 132b.

[0029] Referring to Figure 9, a patterning process, such as a photolithography and etching process, is performed on the stacked structure SK and the conductor layer 102 to form a slit trench 133 that runs through the stacked structure SK and the conductor layer 102. In some embodiments, the bottom of the slit trench 133 exposes the buffer layer 101, and the bottom of the slit trench 133 is higher than the bottom of the isolation pillar 128. In some embodiments, the slit trench 133 may extend along a first direction (e.g., the X direction in Figure 9).

[0030] Referring to Figure 10, the conductor layer 102 is laterally removed from the separation trench 133 using an etching process, such as a wet etching process. A suitable etchant for the wet etching process is selected to remove the conductor layer 102 without substantially removing other material layers. Therefore, after the conductor layer 102 is removed, a horizontal groove HR1 is formed between the stacked structure SK and the buffer layer 101, and the sidewalls of the protective layer 110 are exposed. It should be noted that although the conductor layer 102 is removed in Figure 10, it remains in certain regions throughout the flash memory device to maintain its function. For example, the conductor layer 102 is removed only in the array region.

[0031] Referring to Figure 11, an etching process is used to laterally remove the protective layer 110, charge storage structure 140, channel layer 116, and conductor pillars 132a and 132b from the horizontal groove HR1, thereby forming a horizontal groove HR2 that exposes the sidewalls of the isolation pillars 128. In this disclosure, the etching process for laterally removing the protective layer 110 and charge storage structure 140 from the horizontal groove HR1 can be a dry etching process, and its parameters can be adjusted to etch the protective layer 110 and charge storage structure 140 in the horizontal groove HR1 without substantially removing the insulating layer 104 and intermediate layer 106 in the stacked structure SK. The etching process for laterally removing the channel layer 116 and conductor pillars 132a and 132b from the horizontal groove HR1 can be a dry etching process or a wet etching process.

[0032] Referring to Figure 12, an insulating layer 145 is formed on the buffer layer 101 and in the horizontal groove HR2, such that the insulating layer 145 contacts the sidewall of the isolation pillar 128. The insulating layer 145 is located between the stacked structure SK and the buffer layer 101. In other words, in Figures 11 and 12, the insulating layer 145 is used to replace a portion of the conductor layer 102 and a portion of the channel pillar VC. In some embodiments, the insulating layer 145 is formed by methods such as thermal oxidation, chemical vapor deposition, or atomic layer deposition. In some embodiments, the insulating layer 145 is, for example, silicon oxide, and is made of a different material from the isolation pillar 128.

[0033] In this disclosure, after the insulating layer 145 is formed, the channel pillar VC includes a memory pillar VC1 and an auxiliary pillar VC2. The memory pillar VC1 is formed in the stacked structure SK, and the auxiliary pillar VC2 is formed in the buffer layer 101. The memory pillar VC1 and the auxiliary pillar VC2 are separated by the insulating layer 145. An isolation pillar 128 extends from the memory pillar VC1 to the auxiliary pillar VC2 and penetrates the insulating layer 145. In subsequent memory cell operations, the memory pillar VC1 will serve as the channel region of the memory cell, while the auxiliary pillar VC2 will not participate in the memory cell operation. In some embodiments, the vertical height H2 of the auxiliary pillar VC2 is 20% to 100% of the vertical height of the memory pillar H1.

[0034] Specifically, when forming the insulating layer 145, the insulating layer 145 penetrates the conductor pillars 132a and 132b, such that the memory pillar VC1 formed in the stacked structure SK includes the upper conductor pillar 132aU of conductor pillar 132a and the upper conductor pillar 132bU of conductor pillar 132b, and the isolation pillar 128 electrically isolates the upper conductor pillar 132aU and the upper conductor pillar 132bU. The auxiliary pillar VC2 includes the lower conductor pillar 132aL of conductor pillar 132a and the lower conductor pillar 132bL of conductor pillar 132b, with the lower conductor pillar 132aL located below the upper conductor pillar 132aU and the lower conductor pillar 132bL located below the upper conductor pillar 132bU. The insulating layer 145 separates the lower conductor pillar 132aL and the upper conductor pillar 132aU, respectively. Furthermore, the insulating layer 145 also penetrates the charge storage structure 140 and the channel layer 116, such that the memory pillar VC1 includes the charge storage structure 140U and the channel layer 116U on the insulating layer 145, and the auxiliary pillar VC2 includes the charge storage structure 140L and the channel layer 116L below the insulating layer 145. It should be noted that since the charge storage structure 140L and the channel layer 116L of the auxiliary pillar VC2 do not actually have charge storage function or cannot function as channels, the charge storage structure 140L of the auxiliary pillar VC2 can also be referred to as the dielectric structure 140L, and the channel layer 116L can also be referred to as the polycrystalline silicon layer 116L. The dielectric structure 140L and the charge storage structure 140U are separated by the insulating layer 145 and extend along the same axial direction, as are the polycrystalline silicon layer 116L and the channel layer 116U. In this disclosure, after the insulating layer 145 is formed, the widths of the conductor upper pillars 132aU and 132bU are substantially the same from bottom to top.

[0035] Referring to Figure 13, a partial replacement process is performed on the intermediate layer 106. First, an etching process, such as a wet etching process, is performed to remove the multilayer intermediate layer 106 surrounding the partition trench 133. The etching solution used in the etching process (e.g., hot phosphoric acid) is injected into the partition trench 133, and then the contact portion of the multilayer intermediate layer 106 is removed. When the multilayer intermediate layer 106 between the channel layer 116 and the partition trench 133 is removed, since the protective layer 110 is made of a different material than the intermediate layer 106, the protective layer 110 can serve as an etching stop layer to protect the charge storage structure 140 and the channel layer 116. The etching process continues, and by controlling the time pattern, most of the multilayer intermediate layer 106 is removed to form multiple horizontal grooves HR3. The protective layer 110 on the sidewall of the intermediate layer 106 is removed after the above etching process. In some embodiments, prior to the partial replacement process, a removal process may be performed to remove residues on the sidewalls of the partition trench 133 used to form the insulating layer 145. In some embodiments, prior to the partial replacement process, the partition trench 133 may be widened and deepened so that the insulating layer 145 may be partially removed to expose the buffer layer 101.

[0036] Next, multiple gate layers (or conductor layers) 138 are formed in the plurality of horizontal grooves HR3 to replace the original intermediate layer 106 with gate layers 138. Gate layers 138 are, for example, tungsten. In some embodiments, a barrier layer is also formed before forming the multiple gate layers 138. The barrier layer is made of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof. Thus, a gate stack structure 152 can be formed on the insulating layer 145, and the gate stack structure 152 includes a plurality of gate layers 138 and a plurality of insulating layers 104 stacked alternately on top of each other.

[0037] Referring to Figure 14, a separation slit SLT is formed in the separation trench 133. The method of forming the separation slit SLT includes filling the gate stack structure 152 and the separation trench 133 with insulating material, and then removing excess insulating substrate material and conductor material on the gate stack structure 152 via an etch-back process or a planarization process to form a substrate and conductor layer. The insulating material is, for example, silicon oxide. The conductor material is, for example, polycrystalline silicon. The excess insulating substrate material and conductor material on the gate stack structure 152 are then removed via an etch-back process or a planarization process to form a substrate and conductor layer. The substrate and conductor layer are collectively referred to as the separation slit SLT. In some embodiments, the separation slit SLT may also be entirely filled with insulating material without any conductor layer. In still other embodiments, the separation slit SLT may also be a substrate, and the substrate covers the air gap without any conductor layer. The separating slit SLT extends along a first direction (e.g., the X direction in Figure 14) through the gate stack structure 152 and the insulating layer 145, such that the insulating layer 145 contacts the separating slit SLT and the isolation post 128 in a second direction (e.g., the Y direction in Figure 14).

[0038] Subsequently, a contact window (not shown) is formed in the stepped region. The contact window lands at the end of the gate layer 138 in the stepped region and is electrically connected to it.

[0039] In summary, the formed flash memory element includes a substrate 100, a buffer layer 101, a gate stack structure 152, and a channel pillar VC. The buffer layer 101 is on the substrate 100. The gate stack structure 152 is located on the buffer layer 101, wherein the gate stack structure 152 includes a plurality of gate layers 138 and a plurality of first insulating layers 104 stacked alternately on each other. The channel pillar VC extends through the gate stack structure 152 and is embedded in the buffer layer 101, wherein the channel pillar VC includes a charge storage structure 140U and a channel layer 116U, the charge storage structure 140U being located between the gate layer 138 and the channel layer 116U.

[0040] The channel pillar VC includes a memory pillar VC1 and an auxiliary pillar VC2. The memory pillar VC1 is in the gate stack structure 152 and includes a charge storage structure 140U, a channel layer 116U, an upper conductor pillar 132aU, and an upper conductor pillar 132bU. The auxiliary pillar VC2 is in the buffer layer 101 and includes a dielectric structure 140L, a polysilicon layer 116L, a lower conductor pillar 132aL, and a lower conductor pillar 132bL. The upper conductor pillars 132aU and 132bU are electrically isolated by an isolation pillar 128, and the memory pillar VC1 and the auxiliary pillar VC2 are separated by an insulating layer 145.

[0041] The conductor pillars 132aU and 132bU disclosed herein are formed by a dry etching process with high power and low selectivity, thus having sidewalls substantially perpendicular to the bottom surface of the buffer layer 101. In other words, the widths of the conductor pillars 132aU and 132bU are substantially the same from bottom to top. Within the height range of the gate stack structure 152, especially near the bottom of the gate stack structure 152, the sidewalls of the conductor pillars 132aU and 132bU ensure contact with the channel layer 116U, thereby avoiding poor contact between the conductor pillars 132aU (or 132bU) and the channel layer 116U. In order to avoid the channel pillars VC extending beyond the height range of the gate stack structure 152 from negatively impacting the operation of the memory devices, the present disclosure uses an insulating layer 145 to separate the channel pillars VC into memory pillars VC1 and auxiliary pillars VC2. In this way, the auxiliary pillar VC2 in the buffer layer 101 will not electrically connect the memory pillar VC1 to any gate layer 138, and therefore will not cause interference during memory element operation.

[0042] The above embodiments are illustrated using 3D AND flash memory. However, the embodiments of the present invention are not limited thereto, and the embodiments disclosed herein can also be applied to 3D NOR flash memory or 3D NAND flash memory. [Simplified Explanation of the Diagram]

[0043] Figure 1A shows a circuit diagram of a 3D AND flash memory array according to some embodiments. Figure 1B shows a partial three-dimensional view of a portion of the memory array in Figure 1A. Figures 1C and 1D show cross-sectional views along tangent I-I' in Figure 1B. Figure 1E shows a top view along tangent II-II' in Figures 1B, 1C, and 1D. Figures 2 to 14 are schematic cross-sectional views illustrating a manufacturing process of a 3D AND flash memory element according to an embodiment of the present disclosure. [Biomaterial Storage]

[0045] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A memory element comprising: a substrate; a buffer layer on the substrate; a stacked structure on the buffer layer, wherein the stacked structure includes a plurality of gate layers and a plurality of first insulating layers stacked alternately on top of each other; a second insulating layer between the stacked structure and the buffer layer; and a channel pillar extending through the stacked structure and embedded in the buffer layer, wherein the channel pillar includes a charge storage structure and a channel layer, the charge storage structure being located between the plurality of gate layers and the channel layer, the channel pillar having a memory pillar and an auxiliary pillar, the memory pillar being located in the stacked structure, the auxiliary pillar being located in the buffer layer, wherein the memory pillar and the auxiliary pillar are separated by the second insulating layer.

2. The memory element as claimed in claim 1, wherein the channel post has an isolation post that extends from the memory post to the auxiliary post and penetrates the second insulating layer.

3. The memory element as claimed in claim 2, wherein the memory pillar includes a first conductor upper pillar and a second conductor upper pillar, and the isolation pillar electrically isolates the first conductor upper pillar from the second conductor upper pillar.

4. The memory element as claimed in claim 3, wherein the auxiliary pillar includes a first conductor lower pillar and a second conductor lower pillar, the first conductor lower pillar being located below the first conductor upper pillar and the second conductor lower pillar being located below the second conductor upper pillar, wherein the second insulating layer separates the first conductor lower pillar, the first conductor upper pillar, the second conductor lower pillar, and the second conductor upper pillar.

5. The memory element as claimed in claim 2, wherein the second insulating layer and the isolation pillar are made of different materials.

6. The memory element as claimed in claim 1, wherein the auxiliary pillar comprises a dielectric structure and a polysilicon layer, the dielectric structure and the charge storage structure being separated by the second insulating layer and extending along the same axis, and the polysilicon layer and the channel layer being separated by the second insulating layer and extending along the same axis.

7. The memory element as claimed in claim 1, wherein the vertical height of the auxiliary pillar is 20% to 100% of the vertical height of the memory pillar.

8. The memory element as claimed in claim 1 further includes a separating slit extending along a first direction through the stacked structure and the second insulating layer, such that the second insulating layer contacts the separating slit and the channel post in a second direction.

9. The memory element as described in claim 1, wherein the thickness of the buffer layer is at least 30% greater than the thickness of the stacked structure.

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