Methods of equalizing gate heights in embedded non-volatile memory on hkmg technology

TW202636758APending Publication Date: 2026-09-01INFINEON TECHNOLOGIES LLC
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Patent Information

Application Number
TW115120125
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-05-08
Filing Date
2025-02-05
Publication Date
2026-09-01

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Abstract

Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor disposed within at least one recess(es). The devices further include a logic area in which HV FETs, input / output (I / ) FETs, and low voltage (LV) / core FETs are formed thereon. Other embodiments are also described.
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