Memory unit and manufacturing method thereof
Patent Information
- Application Number
- TW114106049
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-19
- Publication Date
- 2026-09-01
- Estimated Expiration
- 2045-02-18
AI Technical Summary
Ferroelectric memory cells experience polarization deterioration due to oxygen vacancies at the electrode/ferroelectric layer interface, leading to charge trapping and oxidation, which limits their durability and operational lifespan.
A memory cell structure with an interface capping layer comprising a first tungsten nitride layer providing tensile tension and a second tungsten carbonitride layer blocking oxygen ions, combined with an optimized annealing process using a high-temperature furnace with protective wafers, to enhance polarization and prevent oxidation.
The solution significantly improves the durability and polarization of the memory cell, enabling operations exceeding 10^11 cycles without degradation, with enhanced resistance to oxidation and improved response time.
Smart Images
Figure TWG2TA001073728_001 
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Abstract
Description
[Technical Field]
[0001] This invention relates to a memory cell and its manufacturing method, particularly a memory cell containing a tungsten nitride compound and a carbonitride compound and its manufacturing method. [Previous Technology]
[0002] With the rapid development of technology, various types of electronic devices are now ubiquitous, including personal computers, laptops, computers, smartphones, etc.
[0003] Among them, memory devices are essential devices in various electronic devices. These memory devices include a plurality of memory cells. The memory cells can have logic "1" representing a higher potential and logic "0" representing a lower potential to represent binary bit information, which are maintained (stored) until the storage state of the memory cell is changed.
[0004] In recent years, the rapid development of industries such as the Internet of Things, mobile devices, high-speed computers and smart cars has greatly boosted the application demand for massive computing architectures such as artificial intelligence (AI) and edge computing. As a result, existing high-capacity storage components such as DRAM and NAND Flash can no longer keep up with the demand in terms of power consumption and data access speed.
[0005] The global memory industry has entered an era where it must seek new alternative technologies, and among the new memory technology options, "ferroelectric memory" is the most promising.
[0006] HfO2 is a material that is very familiar to semiconductors. It has been widely used in high-k dielectrics of CMOS and dielectrics of DRAM capacitors since below 28nm. Later, it was used in resistive switching materials of ReRAM.
[0007] In a typical FeRAM memory, the polarization of the ferroelectric capacitor element increases with the number of operations (wake-up effect), and then gradually deteriorates (fatigue effect). The final number of operations that the ferroelectric capacitor can perform is limited by the breakdown of the ferroelectric layer.
[0008] The fatigue effect comes from the oxygen vacancies generated by TiOx at the TiN electrode / HfO2 ferroelectric layer interface under repeated operation, which causes charge trapping. These trapped charges may form new electric dipoles and result in ferroelectric domain wall pinning. The collapse of the ferroelectric layer is also related to the continuous accumulation of oxygen vacancies, forming permanent leakage current paths.
[0009] In view of the above problems, the present invention provides a memory cell and a method for manufacturing the same. The memory cell includes an interface capping layer disposed on a ferroelectric layer. The interface capping layer includes a first interface layer and a second interface layer. The first interface layer provides interface tensile tension, which increases the polarization of the memory cell. The second interface layer blocks the diffusion of oxygen ions from the ferroelectric layer into the first interface layer, preventing oxidation of the first interface layer and further preventing oxidation of a top electrode, thereby improving the durability of the memory cell. The present invention further optimizes the annealing process of a memory device. After heating a high-temperature furnace to an annealing temperature, the memory cell in the middle of the high-temperature furnace is annealed to form the memory device. A plurality of protective wafers are disposed before and after the memory cell to provide appropriate stress protection for the memory cell. [Summary of the Invention]
[0010] One object of the present invention is to provide a memory cell and a method for manufacturing the same, wherein an interface cover layer is formed in the memory cell, the interface cover layer comprising a first interface layer and a second interface layer, the first interface layer providing interface tensile tension, the interface tensile tension increasing the polarization of the memory cell; the second interface layer blocking oxygen ions, preventing oxidation of the first interface layer, further preventing oxidation of a top electrode, and optimizing the annealing process.
[0011] To achieve the above objectives, the present invention provides a method for manufacturing a memory cell, which first provides a silicon substrate, then forms a bottom electrode on the silicon substrate, then forms a ferroelectric layer on the bottom electrode, and then forms an interface cover layer comprising a first interface layer and a second interface layer on the ferroelectric layer. The area of the interface cover layer is less than or equal to the area of the ferroelectric layer. The material of the first interface layer is selected from tungsten nitride compound (WNx), and the material of the second interface layer is selected from tungsten carbonitride compound (WCxN). y), wherein the first interface layer is disposed on the second interface layer; then, a top electrode is formed on the interface cover layer to form at least one memory cell on the silicon substrate, wherein the area of the top electrode is equal to the area of the interface cover layer; finally, the memory cell is subjected to an annealing process to form a memory device; wherein in the step of annealing the memory cell to form a memory device, the memory cell is placed in the middle of a high-temperature furnace and annealed for a certain annealing time to form the memory device. The memory cell in the middle of the high-temperature furnace is annealed to form the memory device, and a plurality of protective wafers are disposed before and after the memory cell to provide appropriate stress protection for the memory cell.
[0012] The present invention provides an embodiment in which the high-temperature furnace is heated to an annealing temperature greater than or equal to 400 °C by a plurality of thermocouples.
[0013] The present invention provides an embodiment in which a plurality of protective wafers are disposed before and after the memory cell to protect the memory cell with appropriate stress.
[0014] The present invention provides an embodiment in which, in the step of forming a bottom electrode on the silicon substrate and in the step of forming a top electrode on the interface cover layer, an radio frequency sputtering process is used to perform the steps of forming the bottom electrode on the silicon substrate and forming the top electrode on the interface cover layer.
[0015] The present invention provides an embodiment in which an atomic layer deposition (ALD) process is used in the steps of forming a ferroelectric layer on the bottom electrode and forming an interface capping layer on the ferroelectric layer to form the ferroelectric layer through atomic arrangement, and the step of forming the interface capping layer on the ferroelectric layer is performed by forming the interface capping layer through atomic arrangement. The first interface layer (WNx) provides interface tensile tension, thereby increasing the polarization of the memory cell; the second interface layer (WCxNy) blocks the diffusion of oxygen ions from the ferroelectric layer to the first interface layer, preventing the oxidation of the first interface layer, and further preventing the oxidation of the top electrode, thereby improving the durability of the memory cell.
[0016] In view of the above objectives, the present invention further provides a memory cell structure applied to a memory device, the memory device comprising a plurality of memory cells and a silicon substrate, each memory cell comprising a bottom electrode, a ferroelectric layer, an interface capping layer and a top electrode, the bottom electrode being disposed on the silicon substrate; the ferroelectric layer being disposed on the bottom electrode; the interface capping layer being disposed on the ferroelectric layer, the interface capping layer comprising a first interface layer and a second interface layer, the first interface layer being disposed on the second interface layer, the area of the interface capping layer being less than or equal to the area of the ferroelectric layer, the material of the first interface layer being selected from tungsten nitride compound (WNx), the material of the second interface layer being selected from tungsten carbonitride compound (WCxNy); and the top electrode being disposed on the interface capping layer, the area of the top electrode being equal to the area of the interface capping layer. The first interface layer (WNx) provides interfacial tensile tension, which increases the polarization of the memory cell; the second interface layer (WCxNy) blocks the diffusion of oxygen ions from the ferroelectric layer to the first interface layer, preventing the oxidation of the first interface layer and further preventing the oxidation of the top electrode, thereby improving the durability of the memory cell.
[0017] The present invention provides another embodiment, wherein the material of the ferroelectric layer is selected from the group consisting of zirconium hafnium oxide (HfZrOx), silicon hafnium oxide (HfSiOx), hafnium oxide (HfOx), yttrium hafnium oxide (HfYOx), thorium hafnium oxide (HfGdOx), strontium hafnium oxide (HfSrOx), titanium strontium oxide (SrTiOx), calcium strontium titanate (SrCaTiO3), Ag(Nb1-xTax)O3, barium strontium titanate (BaSrTiO3), barium titanate (BaTiO3), zirconium oxide (ZrOx), or aluminum hafnium oxide (HfAlOx). The materials are selected from one of the following groups: zirconium (Zr), hafnium (Hf), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), silicon tantalumide (TaSi), tantalum carbonitride (TaCN), titanium aluminum nitride (TiAlN), zinc (Zn), nickel (Ni), nickel silicon (NiSi), ruthenium (Ru), carbon (C), silicon (Si), silicon nitride (SiNx), germanium (Ge), platinum (Pt), aluminum (Al), aluminum nitride (AlN), yttrium (Y), thorium (Gd), strontium (Sr), tungsten (W), tungsten silicon (WSi), tungsten nitride (WN), gallium (Ga), and gallium nitride (GaN).
[0018] The present invention provides another embodiment in which the coefficient of thermal expansion of the interface cover layer is lower than that of the top electrode, so as to avoid deformation of the memory cell.
[0019] The present invention provides another embodiment, wherein the interface capping layer is formed on the ferroelectric layer through atomic arrangement, and the first interface layer is formed on the second interface layer through atomic arrangement, the second interface layer is formed on the ferroelectric layer through atomic arrangement, the first interface layer provides an interface tensile tension between the top electrode and the second interface layer, and the first interface layer provides an interface tensile tension between the top electrode and the second interface layer, thereby increasing the polarization degree of the memory cell.
[0020] The present invention provides another embodiment in which the second interface layer blocks oxygen ions generated by the ferroelectric layer to prevent the oxidation of the first interface layer and further prevent the oxidation of the top electrode, thereby improving the durability of the memory cell.
Implementation Method
[0021] To enable your review committee to have a better understanding of the features and effects achieved by the present invention, preferred embodiments and detailed descriptions are provided below:
[0022] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. Moreover, the specification and claims do not distinguish elements by differences in name, but by differences in the overall technology of the elements. The term "comprising" as used throughout the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to". Furthermore, the term "coupled" here includes any direct and indirect means of connection. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly connected to the second device, or can be indirectly connected to the second device through other devices or other means of connection.
[0023] In view of the fact that the polarization of conventional ferroelectric memory increases with the number of operations (wake-up effect) and then gradually deteriorates (fatigue effect); oxygen vacancies are generated at the interface between the bottom electrode and the ferroelectric layer under repeated operations, resulting in charge trapping; the top electrode and the first interface layer are oxidized due to the diffusion of oxygen ions in the ferroelectric layer, reducing the durability of the memory cell.
[0024] The present invention provides a memory cell and a method for manufacturing the same. The memory cell includes an interface capping layer disposed on a ferroelectric layer. The interface capping layer includes a first interface layer and a second interface layer. The first interface layer provides interface tensile tension, which increases the polarization of the memory cell. The second interface layer blocks oxygen ions to prevent oxidation of the first interface layer and further prevents oxidation of a top electrode. Furthermore, the annealing process of the memory device is optimized by heating a high-temperature furnace to an annealing temperature and then annealing the memory cell in the middle. A plurality of protective wafers are disposed before and after the memory cell to protect the memory cell with appropriate stress.
[0025] In the following, the invention will be described in detail by way of the embodiments illustrated in the drawings. However, the concept of the invention may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein.
[0026] First, please refer to Figures 1 to 3, which are schematic diagrams of the memory cell structure of the present invention. As shown in the figures, the memory cell 20 of the present invention is applied to a memory device 10. The memory device 10 includes a plurality of memory cells 20 and a silicon substrate 30. Each memory cell 20 includes: a bottom electrode 40 disposed on the silicon substrate 30; a ferroelectric layer 50 disposed on the bottom electrode 40; and an interface capping layer. Layer (ICL) 60, disposed on the ferroelectric layer 50, the interface cover layer 60 includes a first interface layer 61 and a second interface layer 62, the material of the first interface layer 61 is selected from tungsten nitride compound (WNx), the material of the second interface layer 62 is selected from tungsten carbonitride compound (WCxNy), wherein the first interface layer 61 is disposed on the second interface layer 62; and a top electrode 70, disposed on the interface cover layer 60.
[0027] The interface capping layer 60 is formed on the ferroelectric layer 50 through atomic arrangement, and the first interface layer 61 is formed on the second interface layer 62 through atomic arrangement. The second interface layer 62 is formed on the ferroelectric layer 50 through atomic arrangement. The first interface layer 61 provides an interface tensile tension between the top electrode 70 and the second interface layer 62. The first interface layer 61 is disposed between the second interface layer 62 and the top electrode 70 to provide an interface tensile tension between the second interface layer 62 and the top electrode 70, thereby increasing the polarization degree of the memory cell 20. The second interface layer 62 is disposed between the ferroelectric layer 50 and the first interface layer 61 to block the diffusion of oxygen ions generated by the ferroelectric layer 50 to the first interface layer 61, preventing the first interface layer 61 from oxidizing, and further preventing the top electrode 70 from oxidizing, thereby improving the durability of the memory cell 20.
[0028] In this embodiment, the bottom electrode 40 has a thickness of 40 nm; the ferroelectric layer has a thickness of 10 nm; the first interface layer has a thickness of 2 nm; the second interface layer has a thickness of 2 nm; and the top electrode has a thickness of >30 nm.
[0029] Referring again to Figures 1 and 3, the area of the interface cover layer 60 is less than or equal to the area of the ferroelectric layer 50, and the area of the top electrode 70 is equal to the area of the interface cover layer 60. The material of the ferroelectric layer 50 is selected from the group consisting of zirconium hafnium oxide (HfZrOx), silicon hafnium oxide (HfSiOx), hafnium oxide (HfOx), yttrium hafnium oxide (HfYOx), thorium hafnium oxide (HfGdOx), strontium hafnium oxide (HfSrOx), titanium strontium oxide (SrTiOx), calcium strontium titanate (SrCaTiO3), Ag(Nb1-xTax)O3, barium strontium titanate (BaSrTiO3), barium titanate (BaTiO3), zirconium oxide (ZrOx), or aluminum hafnium oxide (HfAlOx).
[0030] The materials of the bottom electrode 40 and the top electrode 70 are selected from the group consisting of zirconium (Zr), hafnium (Hf), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), silicon tantalumide (TaSi), tantalum carbonitride (TaCN), titanium aluminum nitride (TiAlN), zinc (Zn), nickel (Ni), nickel silicon (NiSi), ruthenium (Ru), carbon (C), silicon (Si), silicon nitride (SiNx), germanium (Ge), platinum (Pt), aluminum (Al), aluminum nitride (AlN), yttrium (Y), thorium (Gd), strontium (Sr), tungsten (W), tungsten silicon (WSi), tungsten nitride (WN), gallium (Ga), and gallium nitride (GaN).
[0031] Wherein, the coefficient of thermal expansion of the interface covering layer 60 is lower than that of the top electrode 70.
[0032] Continuing from the above, please refer to Figure 4, which is a flowchart of a method for manufacturing a memory cell according to an embodiment of the present invention. As shown in the figure, the steps of an embodiment of the method for manufacturing a memory cell according to the present invention are as follows:
[0033] Step S10: Provide a silicon substrate;
[0034] Step S20: Form a bottom electrode on a silicon substrate;
[0035] Step S30: Form a ferroelectric layer on the bottom electrode;
[0036] Step S40: Form an interface capping layer comprising a first interface layer and a second interface layer on the ferroelectric layer;
[0037] Step S50: Form a top electrode on the interface capping layer;
[0038] Step S60: Form memory cells on a silicon substrate; and
[0039] Step S70: The memory cell undergoes an annealing process to form a memory device.
[0040] In step S10, a silicon substrate 30 is provided in the manufacturing process of the memory cell 20 of the present invention. The material of the silicon substrate 30 is selected from single crystal silicon, polycrystalline silicon, silicon nitride (Si3N4) or silicon carbide (SiC).
[0041] In step S20, the bottom electrode 40 is formed on the silicon substrate 30 using an radio frequency sputtering process. The material of the bottom electrode 40 is selected from the group consisting of zirconium (Zr), hafnium (Hf), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), silicon tantalum nitride (TaSi), tantalum carbonitride (TaCN), titanium aluminum nitride (TiAlN), zinc (Zn), nickel (Ni), nickel silicon nitride (NiSi), ruthenium (Ru), carbon (C), silicon (Si), silicon nitride (Si3N4), germanium (Ge), platinum (Pt), aluminum (Al), aluminum nitride (AlN), yttrium (Y), thorium (Gd), strontium (Sr), tungsten (W), tungsten silicon nitride (WSi), tungsten nitride (WN), gallium (Ga), and gallium nitride (GaN).
[0042] In step S30, an atomic layer deposition (ALD) process is used to form the ferroelectric layer 50 on the bottom electrode 40. The material of the ferroelectric layer 50 is selected from the group consisting of zirconium hafnium oxide (HfZrOx), silicon hafnium oxide (HfSiOx), hafnium oxide (HfOx), yttrium hafnium oxide (HfYOx), thorium hafnium oxide (HfGdOx), strontium hafnium oxide (HfSrOx), titanium strontium oxide (SrTiOx), calcium strontium titanate (SrCaTiO3), Ag(Nb1-xTax)O3, barium strontium titanate (BaSrTiO3), barium titanate (BaTiO3), zirconium oxide (ZrOx), or aluminum hafnium oxide (HfAlOx).
[0043] In step S40, the atomic layer deposition (ALD) process is used to form the interface capping layer 60 on the ferroelectric layer 50, and the first interface layer 61 and the second interface layer 62 are formed sequentially on the ferroelectric layer 50. The area of the interface capping layer 60 is less than or equal to the area of the ferroelectric layer 50.
[0044] In step S50, the top electrode 70 is formed on the interface cover layer 60 using the radio frequency sputtering process. The material of the top electrode 70 is selected from the group consisting of zirconium (Zr), hafnium (Hf), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), silicon tantalumide (TaSi), tantalum carbonitride (TaCN), titanium aluminum nitride (TiAlN), zinc (Zn), nickel (Ni), nickel silicon (NiSi), ruthenium (Ru), carbon (C), silicon (Si), silicon nitride (SiNx), germanium (Ge), platinum (Pt), aluminum (Al), aluminum nitride (AlN), yttrium (Y), thorium (Gd), strontium (Sr), tungsten (W), tungsten silicon (WSi), tungsten nitride (WN), gallium (Ga), and gallium nitride (GaN). The area of the top electrode 70 is equal to the area of the interface cover layer 60. The coefficient of thermal expansion of the interface cover layer 60 is lower than that of the top electrode 70. Since the first interface layer 61 is located between the second interface layer 62 and the top electrode 70, it can provide interface tensile tension, thereby increasing the polarization degree of the memory cell 20.
[0045] In step S70, referring further to Figure 5, which is a schematic diagram of the annealing process environment of the manufacturing method of the memory cell of the present invention, the wafer on which the memory cell 20 is disposed is placed in the middle of a high-temperature furnace 100 and annealed for a period of time to form a memory device 10. The high-temperature furnace 100 is heated to an annealing temperature by a plurality of thermocouples 101. The annealing time is 0.5 hours to 1.5 hours and the annealing temperature is less than or equal to 400 °C. The thermocouples 101 control the annealing temperature within ±2 °C of temperature error. For example, in the high-temperature furnace 100, the annealing temperature is heated to the specified temperature by the thermocouples 101 and filled with nitrogen gas at 5000 standard milliliters / minute (5 SLM). After 2 minutes, the wafer containing the memory cell 20 is placed in the high-temperature furnace 100. After annealing for 1 hour, the wafer containing the memory cell 20 is removed from the high-temperature furnace 100 after another 2 minutes. Furthermore, multiple protection wafers 25 are placed before and after the wafer containing the memory cell 20 in the high-temperature furnace 100, for example, 3 protection wafers 25 before and after, to provide thermal stress protection and protect the memory cell 20, thereby enabling its application in the back-end process (BEOL process) or batch process (Batch process).
[0046] Referring again to Figure 5, which is a schematic diagram of the annealing process environment of the manufacturing method of the memory cell of the present invention, in step S70, nitrogen (N2) is introduced into the high-temperature furnace 100 at a rate of 5000 standard milliliters per minute through an MFC flow meter, so that the high-temperature furnace 100 is a nitrogen atmosphere environment. The high-temperature furnace 100 is heated to <400 °C through the thermocouples 101. The interior of the high-temperature furnace 100 is roughly divided into three regions: front section, middle section, and rear section, corresponding to the heating regions of the thermocouples 101. The wafer containing the memory cell 20 is placed in the middle section region of the high-temperature furnace 100. The protective wafers 25 are set in front of and behind the wafer containing the memory cell 20, that is, the protective wafers 25 are set in the front section region and the rear section region of the high-temperature furnace 100 to provide thermal stress protection and protect the wafer containing the memory cell 20.
[0047] Through the above-mentioned annealing process, the interface cover layer 60 and the ferroelectric layer 50 of the memory cell 20 are recrystallized, thereby further reducing the existing constant on-time (COT) of the memory cell 20 of the present invention, thus improving the response time of the memory cell 20.
[0048] Referring to Figures 6A and 6B, which are schematic diagrams of the working voltage versus residual polarization (2Pr value) and the material of the interface capping layer versus the change in residual polarization value in one embodiment of the present invention, the second interface layer 62 of the interface capping layer 60 blocks oxygen ions, resulting in a reduction in oxide formation and thus increasing the 2Pr value. As shown in Figure 6A, when the material of the second interface layer 62 is tungsten nitride and tungsten carbide with a moiré ratio of 1:1, the working voltage is gradually increased from ±0.5V to ±4.0V, with an increase of 0.5V in each stage. As shown in Figure 6B, the change in residual polarization (2Pr value) of pure tungsten nitride and tungsten carbonitride compound is shown. Tungsten carbonitride compound refers to a mixture of tungsten carbide compound and tungsten nitride compound (WNx), for example: tungsten nitride compound / tungsten carbide (WNx / W 2C), tungsten nitride compound / tungsten carbide (WNx / WC) and tungsten nitride compound / tungsten acetylene (WNx / WC 2), solid squares indicate an operating voltage of 4V and open squares indicate an operating voltage of 2V. It can be seen that the residual polarization value of the tungsten carbide compound is better than that of the pure tungsten nitride compound. In this embodiment, the thickness of the ferroelectric layer is 10nm and the thickness of the interface capping layer is 4nm.
[0049] Referring to Figure 7, which is a schematic diagram of the change of residual polarization value of the working voltage of the memory cell of the present invention, as shown in the figure, in the embodiment of the present invention, the interface capping layer of the present invention is provided on the ferroelectric layer with a thickness of 5nm, which has better polarization change, especially the performance under ±1V working voltage, and can be applied to cache memory. In this embodiment, the operating environment is a nitrogen (N2) environment, the working voltage is ±1V to ±2.5V, the voltage of each stage is 0.5V, the working temperature is 400°C, and the working time is 1 hour.
[0050] Referring to Figure 8, which is a graph showing the relationship between the residual polarization value and the pulse width of the memory cell of the present invention after wake-up, it can be seen that the memory cell of the present invention exhibits good polarization performance after wake-up. Specifically, for the residual polarization value with an operating voltage of 2V to 4V and a pulse width between 10⁻⁸ seconds and 10⁻³ seconds, it can be seen that the wider the pulse width, i.e. the larger the number of seconds, the greater the residual polarization value.
[0051] Referring to Figure 9, which is a test result of the durability of the memory cell of the present invention, it can be seen that the memory cell of the present invention has good durability. In this embodiment, with a working voltage of 3V and an access time of 50 nanoseconds (ns), the number of times it operates in the on state (+Pr) and the off state (-Pr) can reach more than 10^11 times.
[0052] In summary, the present invention relates to a memory cell and a method for manufacturing the same. The memory cell includes a top electrode, a ferroelectric layer, an interface capping layer, and a bottom electrode, which are sequentially disposed on a silicon substrate for use in a memory device. The interface capping layer is disposed on the ferroelectric layer and includes a first interface layer and a second interface layer. The first interface layer provides interface tensile tension, which increases the polarization degree of the memory cell. The second interface layer is disposed between the ferroelectric layer and the first interface layer. Between these layers, oxygen ions generated by the ferroelectric layer are prevented from diffusing to the first interface layer, thus preventing oxidation of the first interface layer and further preventing oxidation of the top electrode, thereby improving the durability of the memory cell 20. Furthermore, an annealing process is provided for the memory device, in which a high-temperature furnace is heated to an annealing temperature and the memory cell in the middle is annealed. Furthermore, multiple protective wafers are set in front of and behind the memory cell in the high-temperature furnace to provide thermal stress protection for the memory cell.
[0053] Therefore, this invention is indeed novel, inventive and industrially applicable, and should undoubtedly meet the requirements for patent application under the Patent Law of our country. Therefore, we hereby file an invention patent application in accordance with the law, and earnestly pray that the Bureau will grant the patent as soon as possible.
[0054] However, the above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. All equivalent changes and modifications made to the shape, structure, features and spirit described in the claims of the present invention should be included in the scope of the claims of the present invention. [Simplified Explanation of the Diagram]
[0055] Figure 1: A schematic diagram of the memory cell structure according to one embodiment of the present invention; Figure 2: A schematic diagram of a transmission electron microscope image according to one embodiment of the present invention; Figure 3: Another schematic diagram of the memory cell structure according to one embodiment of the present invention; Figure 4: A flowchart of the manufacturing method of the memory cell according to one embodiment of the present invention; Figure 5: A schematic diagram of the annealing process environment according to one embodiment of the present invention; Figures 6A and 6B: Schematic diagrams of the effect of voltage on residual polarization (2Pr value) and the influence of material on residual polarization (2Pr value) according to one embodiment of the present invention; Figure 7: A schematic diagram of the effect of voltage on residual polarization (2Pr value) of the memory cell according to one embodiment of the present invention; Figure 8: A graph showing the relationship between residual polarization value and pulse width of the memory cell after wake-up according to one embodiment of the present invention; and Figure 9: A graph showing the durability test results of the memory cell according to one embodiment of the present invention.
Claims
1. A method for manufacturing a memory cell, comprising the steps of: providing a silicon substrate; forming a bottom electrode on the silicon substrate; forming a ferroelectric layer on the bottom electrode; forming an interface capping layer on the ferroelectric layer, the area of the interface capping layer being less than or equal to the area of the ferroelectric layer, the interface capping layer comprising a first interface layer and a second interface layer, the material of the first interface layer being selected from tungsten nitride compound, the material of the second interface layer being selected from tungsten carbonitride compound, the first interface layer being formed on the second interface layer; forming a top electrode on the interface capping layer, the area of the top electrode being equal to the area of the interface capping layer; forming at least one memory cell on the silicon substrate; and performing an annealing process on the memory cell to form a memory device. In the step of annealing the memory unit to form a memory device, the memory unit is placed in the middle of a high-temperature furnace and annealed for a certain period of time to form the memory device.
2. The method of manufacturing a memory cell as claimed in claim 1, wherein in the step of performing an annealing process on the memory cell to form a memory device, the high-temperature furnace is heated to an annealing temperature less than or equal to 400°C by a plurality of thermocouples, the annealing temperature being used to drive the interface capping layer and the ferroelectric layer to recrystallize.
3. The method for manufacturing a memory cell as claimed in claim 1, wherein in the step of performing an annealing process on the memory cell to form a memory device, a plurality of protective wafers are disposed before and after the memory cell to provide thermal stress protection for the wafer in which the memory cell is located.
4. The method for manufacturing a memory cell as claimed in claim 1, wherein in the step of forming a bottom electrode on the silicon substrate and in the step of forming a top electrode on the interface capping layer, an radio frequency sputtering process is used to perform the steps of forming the bottom electrode on the silicon substrate and forming the top electrode on the interface capping layer.
5. The method for manufacturing a memory cell as claimed in claim 1, wherein in the step of forming a ferroelectric layer on the bottom electrode and in the step of forming an interface capping layer on the ferroelectric layer, an atomic layer deposition (ALD) process is used to form the ferroelectric layer by atomic arrangement, and the step of forming the interface capping layer on the ferroelectric layer is performed by forming the interface capping layer by atomic arrangement.
6. A memory cell used in a memory device, the memory device comprising a plurality of memory cells and a silicon substrate, each memory cell comprising: a bottom electrode disposed on the silicon substrate; a ferroelectric layer disposed on the bottom electrode; an interface cover layer disposed on the ferroelectric layer, the area of the interface cover layer being less than or equal to the area of the ferroelectric layer, the interface cover layer comprising a first interface layer and a second interface layer, the material of the first interface layer being selected from tungsten nitride compound, the material of the second interface layer being selected from tungsten carbonitride compound, wherein the first interface layer is disposed on the second interface layer; and a top electrode disposed on the interface cover layer, the area of the top electrode being equal to the area of the interface cover layer.
7. The memory cell as described in claim 6, wherein the material of the ferroelectric layer is selected from the group consisting of zirconium hafnium oxide (HfZrOx), silicon hafnium oxide (HfSiOx), hafnium oxide (HfOx), yttrium hafnium oxide (HfYOx), thorium hafnium oxide (HfGdOx), strontium hafnium oxide (HfSrOx), titanium strontium oxide (SrTiOx), calcium strontium titanate (SrCaTiO3), Ag(Nb1-xTax)O3, barium strontium titanate (BaSrTiO3), barium titanate (BaTiO3), zirconium oxide (ZrOx), or aluminum hafnium oxide (HfAlOx), and the bottom electrode and the top electrode are made of... The material is selected from one of the following groups: zirconium (Zr), hafnium (Hf), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), silicon tantalumide (TaSi), tantalum carbonitride (TaCN), titanium aluminum nitride (TiAlN), zinc (Zn), nickel (Ni), nickel siliconide (NiSi), ruthenium (Ru), carbon (C), silicon (Si), silicon nitride (SiNx), germanium (Ge), platinum (Pt), aluminum (Al), aluminum nitride (AlN), yttrium (Y), thorium (Gd), strontium (Sr), tungsten (W), tungsten siliconide (WSi), tungsten nitride (WN), gallium (Ga), and gallium nitride (GaN).
8. The memory cell as described in claim 6, wherein the coefficient of thermal expansion of the interface cover layer is lower than that of the top electrode.
9. The memory cell as claimed in claim 6, wherein the interface capping layer is formed on the ferroelectric layer through an atomic arrangement, and the first interface layer is formed on the second interface layer through an atomic arrangement, the second interface layer is formed on the ferroelectric layer through an atomic arrangement, and the first interface layer provides an interface tensile tension between the top electrode and the second interface layer.
10. The memory cell as claimed in claim 6, wherein the second interface layer blocks oxygen ions generated by the ferroelectric layer.