Memory device

Abstract

The memory cell of this invention includes a variable resistor element and a switching element. A first wiring is connected to the memory cell. A first driver is configured to generate a first potential on the first wiring based on the terminal voltage of the memory cell. A comparator circuit is configured to output first data with a first level when the first potential exceeds a reference potential, and to output first data with a second level when the first potential is lower than the reference potential. A register holds the first data and outputs a first signal with a level based on the first data. A second driver is configured to receive the first signal and, in response to an external instruction to apply stress to the memory cell, apply stress when the first signal has a first level, and not apply stress when the first signal has a second level.

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