Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a substrate, a device isolation structure, a gate structure, a plurality of contact plugs, an interlayer dielectric (ILD) layer and an oxide material. The device isolation structure is disposed in the substrate to define an active region. The gate structure is disposed on the substrate and crosses the active region. The contact plugs are respectively disposed on both sides of the gate structure and on the gate structure. The interlayer dielectric layer covers the gate structure and has a plurality of annular openings, and each of the annular openings surrounds each of the contact plugs. The oxide material is filled in the annular openings, and an air gap is formed in the oxide material, wherein one air gap surrounds one contact plug.

Description

Technical Field

[0001] This invention relates to a semiconductor manufacturing process, and more particularly to a semiconductor device and a method of manufacturing the same. Prior Technology

[0002] As component sizes shrink, the distance between components and circuits in semiconductor devices is getting closer and closer. Therefore, one of the current concerns is the impact of parasitic capacitance, such as the parasitic capacitance generated between the gate and the contact plug in a transistor, as well as the parasitic capacitance generated between adjacent contact plugs. Since the generation of parasitic capacitance can lead to problems such as RC delay, it will affect the device performance. Summary of the Invention

[0003] This invention provides a semiconductor device and its manufacturing method, which can solve the problem of parasitic capacitance and the controversy surrounding its impact on component performance, such as RC delay.

[0004] A semiconductor device according to the present invention includes at least a substrate, a device isolation structure, a gate structure, a plurality of contact plugs, an interlayer dielectric (ILD) layer, and an oxide material. The device isolation structure is disposed in the substrate to define an active region. The gate structure is disposed on the substrate and spans the active region. Contact plugs are respectively disposed on both sides of the gate structure and on the gate structure. The interlayer dielectric layer covers the gate structure and has a plurality of annular openings, each annular opening surrounding each contact plug. The oxide material fills the annular openings and has air gaps within the oxide material, one of which surrounds a contact plug.

[0005] In one embodiment of the present invention, the above-mentioned oxide material and the above-mentioned interlayer dielectric layer are provided between the air gap and the contact plug.

[0006] In one embodiment of the present invention, the semiconductor device may further include an etch stop layer, which is conformally disposed on the surface of the gate structure.

[0007] In one embodiment of the present invention, the gate structure includes a gate oxide layer, a gate layer, and a spacer wall. The gate oxide layer is formed on the surface of the active region, and the gate layer is formed on the gate oxide layer. The spacer wall is formed on the sidewall of the gate layer.

[0008] In one embodiment of the present invention, the active region includes a source and a drain, which are respectively formed on both sides of the gate structure.

[0009] In one embodiment of the present invention, the semiconductor device may further include a metal silicate layer disposed on the surface of the active region and the gate layer.

[0010] In one embodiment of the present invention, the contact plugs in the air gap surrounding contact plugs are coupled to the gate structure and to the drain of the active region.

[0011] In one embodiment of the present invention, the contact plugs in the air gap surrounding contact plugs are coupled to the gate structure and to the source and drain electrodes of the active region.

[0012] A method for manufacturing a semiconductor device according to the present invention includes the following steps: Forming a device isolation structure within a substrate to define an active region. Forming a gate structure across the active region on the substrate. Forming an interlayer dielectric layer on the substrate covering the substrate and the gate structure. Forming a plurality of contact plugs in the interlayer dielectric layer, respectively coupling the active region and the gate structure. Forming a plurality of annular openings in the interlayer dielectric layer, each annular opening surrounding each contact plug. Depositing an oxide material on the substrate to cover the upper part of each annular opening and forming an air gap therein.

[0013] In another embodiment of the invention, after the air gap is formed, the oxide material other than the annular opening can be removed to expose the contact plug.

[0014] In another embodiment of the invention, the manufacturing method described above may further include forming a wire layer on the exposed contact plug.

[0015] In another embodiment of the invention, an etch stop layer may be conformally deposited on the surface of the gate structure before forming the interlayer dielectric layer.

[0016] In another embodiment of the present invention, the method of forming a gate structure includes forming a gate oxide layer on the surface of the active region, forming a gate layer on the gate oxide layer, and forming a gap wall on the sidewall of the gate layer.

[0017] In another embodiment of the invention, a metal silicate layer may be formed on the surface of the active region and the surface of the gate layer before forming the interlayer dielectric layer.

[0018] To make the above features of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0019] Figure 1 is a top view of a semiconductor device according to a first embodiment of the present invention. Figure 2 is a cross-sectional view of line XX in Figure 1. Figure 3 is a top view of a semiconductor device according to a second embodiment of the present invention. Figures 4A, 6A, 7A and 8A are top views of the manufacturing process of a semiconductor device according to a third embodiment of the present invention. Figures 4B, 5, 6B, 7B, 8B, 9, and 10 are cross-sectional views of the manufacturing process of a semiconductor device according to the third embodiment. Implementation

[0020] The present invention can be understood by referring to the following detailed description and the accompanying drawings. Furthermore, the dimensions of the various regions in the drawings are for illustrative purposes only and are not intended to limit the scope of the invention.

[0021] Figure 1 is a top view of a semiconductor device according to a first embodiment of the present invention. Figure 2 is a cross-sectional view along line XX of Figure 1.

[0022] Referring to Figures 1 and 2, the semiconductor device includes at least a substrate 100, a device isolation structure 102, a gate structure 104, several contact plugs 106d, 106g, and 106s, an interlayer dielectric (ILD) layer 108, and an oxide material 110. For simplicity, Figure 1 omits some components, showing only the outline of the gate structure 104, the contact plugs 106d, 106g, and 106s, and the oxide material 110. The substrate 100 partially shows the device isolation structure 102 and the active region AA. In some embodiments, the substrate 100 is a semiconductor substrate, such as a silicon substrate. The device isolation structure 102 is disposed in the substrate 100 to define the active region AA. In some embodiments, the device isolation structure 102 is, for example, an STI. The gate structure 104 is disposed on the substrate 100 and spans the active region AA. The contact plugs 106s are disposed on one side of the gate structure 104, and the contact plugs 106d are disposed on the other side of the gate structure 104. Contact plugs 106g are disposed on gate structure 104. In some embodiments, the materials of contact plugs 106d, 106g, and 106s are, for example, metals, such as tungsten. Furthermore, a barrier layer (not shown), such as a Ti / Ti layer, may be provided between contact plugs 106d, 106g, and 106s and surrounding structures (such as interlayer dielectric layer 108 and oxide material 110). Interlayer dielectric layer 108 covers gate structure 104 and has several annular openings CO, each annular opening CO surrounding each contact plug 106d, 106g, and 106s. Oxide material 110 fills the annular openings CO and has an air gap 112 within oxide material 110, one of which surrounds one of contact plugs 106d, 106g, and 106s. In some embodiments, oxide material 110 may be selected from materials with low dielectric constants, which can further reduce the generated parasitic capacitance.

[0023] In some embodiments, an oxide material 110 and an interlayer dielectric layer 108 are present between the air gap 112 and the contact plug 106s. In some embodiments, an oxide material 110 and an interlayer dielectric layer 108 are present between the air gap 112 and the contact plug 106d. Furthermore, although a cross-section of the contact plug 106g is not shown, an oxide material 110 and an interlayer dielectric layer 108 may also be present between the air gap 112 and the contact plug 106g.

[0024] In some embodiments, the gate structure 104 may include a gate oxide layer 114, a gate layer 116, and a spacer wall 118. The gate oxide layer 114 is formed on the surface of the active region AA, and the gate layer 116 is formed on the gate oxide layer 114. The spacer wall 118 is formed on the sidewall of the gate layer 116. In some embodiments, the material of the gate layer 116 is, for example, polycrystalline silicon. In some embodiments, the material of the spacer wall 118 is, for example, silicon nitride.

[0025] In some embodiments, the semiconductor device of the first embodiment may further include an etch stop layer 120, conformally disposed on the surface of the gate structure 104. In some embodiments, the material of the etch stop layer 120 is, for example, silicon nitride, silicon oxynitride (SiON), silicon carbide (SiCN), etc. Therefore, the etch stop layer 120 is located between the gate structure 104 and the interlayer dielectric layer 108. The etch stop layer 120 generally serves as a stop layer in the etching process during the formation of the contact plugs 106d, 106g, and 106s, preventing the contact plugs 106d, 106g, and 106s from affecting the gate structure 104 due to alignment errors. Moreover, the etch stop layer 120 in the first embodiment can also serve as a stop layer during the etching process to form the annular opening CO, so the annular opening CO will be located on the etch stop layer 120, such that the air gap 112 in the annular opening CO is located above the etch stop layer 120.

[0026] In some embodiments, the active region AA includes a source 101s and a drain 101d, which are formed on opposite sides of the gate structure 104. In some embodiments, the semiconductor device of FIG2 may further include a metal silicate layer 122, which may be disposed on the surfaces of the active region AA and the gate layer 116. Therefore, the contact plugs 106s, 106g, and 106d can directly contact the metal silicate layer 122 and are electrically coupled to the source 101s, the gate layer 116, and the drain 101d respectively through the metal silicate layer 122.

[0027] In the first embodiment, the air gap 112 surrounds the contact plug 106g, which is coupled to the gate structure 104, and the contact plugs 106s and 106d, which are coupled to the source and drain of the active region AA. In other embodiments, the air gap 112 surrounds the contact plug 106g, which is coupled to the gate structure 104, and the contact plug 106d, which is coupled to the drain of the active region AA, because the voltage flowing through these two locations is relatively large, and the air gap 112 is needed to reduce the parasitic capacitance that arises as a result.

[0028] Referring again to Figure 2, a conductor layer 124 may be formed above the contact plugs 106s and 106d, respectively connecting the contact plugs 106s and 106d. In some embodiments, the material of the conductor layer 124 is, for example, a metal, such as copper or aluminum.

[0029] Figure 3 is a top view of a semiconductor device according to a second embodiment of the present invention, wherein the same element symbols as in Figure 1 are used to represent the same or similar elements or regions, and the content of the first embodiment can be referred to, so it will not be repeated here.

[0030] Referring to Figure 3, the semiconductor device of the second embodiment is structurally similar to that of the semiconductor device of the first embodiment, except that the positions of the gate structure 300 and the contact plug 302g coupled to the gate structure 300 differ from those of the first embodiment. In some embodiments, the gate structure 300 has the same cross-section as the gate structure 104 in Figure 2, but is slightly shorter in length; and the contact plug 302g is disposed above the gate structure 300, and from the top view, the contact plug 302g overlaps with the active region AA.

[0031] Figures 4A to 10 are schematic diagrams of the manufacturing process of a semiconductor device according to a third embodiment of the present invention, wherein Figures 4A and 4B are different views of the same stage; Figures 6A and 6B are different views of the same stage; Figures 7A and 7B are different views of the same stage; and Figures 8A and 8B are different views of the same stage. Moreover, for the sake of simplicity, some components are omitted in the upper views.

[0032] Referring first to Figures 4A and 4B, a device isolation structure 402 is formed within a substrate 400 to define an active region AA. In some embodiments, the substrate 400 is a semiconductor substrate, such as a silicon substrate. In some embodiments, the device isolation structure 402 is, for example, an STI (Surface Mount Technology). Then, a gate structure 404 spanning the active region AA is formed on the substrate 400. In some embodiments, the method of forming the gate structure 404 includes forming a gate oxide layer 406 on the surface 400s of the active region AA, forming a gate 408 layer on the gate oxide layer 406, and forming a spacer wall 410 on the sidewall of the gate layer 408. In some embodiments, the material of the gate layer 408 is, for example, polycrystalline silicon. In some embodiments, the material of the spacer wall 410 is, for example, silicon nitride. Subsequently, a source electrode 401s and a drain electrode 401d can be formed within the active region AA using an ion implantation process, and a metal silicide layer 412 is formed on the surface 400s of the active region AA and the surface of the gate layer 408. In some embodiments, the method of forming the metal silicate layer 412 includes first depositing a metal layer and then performing a thermal process to react the metal with silicon to form a metal silicate, followed by removing the unreacted metal.

[0033] Referring to Figure 5, an etch stop layer 414 can be conformally deposited on the surface of the gate structure 404, and then an interlayer dielectric layer 416 can be formed on the substrate 400, but this is not limited to this. In some embodiments, the etch stop layer 414 can be omitted. In some embodiments, the material of the etch stop layer 414 is, for example, silicon nitride, silicon oxynitride (SiON), silicon carbide (SiCN), etc.

[0034] Referring to Figures 6A and 6B, several contact plugs 418s, 418d, and 418g are formed in the interlayer dielectric layer 416, respectively coupling to the source 401s and drain 401d of the active region AA and the gate layer 408 of the gate structure 404. If a metal silicate layer 412 is present, the contact plugs 418s, 418d, and 418g will be in direct contact with the metal silicate layer 412. In some embodiments, the method of forming contact plugs 418s, 418d, and 418g includes first forming an opening in the interlayer dielectric layer 416 using a photolithography process, with an etch stop layer 414 used as an etch stop layer, then removing the etch stop layer 414 until a metal silicate layer 412 is exposed, forming a barrier layer and a metal material in the opening, and optionally performing a planarization process (such as CMP) to form contact plugs 418s, 418d, and 418g. In some embodiments, the material of contact plugs 418s, 418d, and 418g is, for example, tungsten, and the barrier layer (not shown) therein is, for example, a Ti / Ti layer. In some embodiments, contact plugs 418s, 418d, and 418g can be formed together; or, contact plugs 418s and 418d are formed together, and contact plug 418g is formed using another photolithography process.

[0035] Referring to Figures 7A and 7B, a plurality of annular openings O2 are formed in the interlayer dielectric layer 416, each annular opening O2 surrounding each contact plug 418s, 418d, and 418g. In some embodiments, the method of forming the annular openings O2 includes forming a patterned mask layer 420 (such as photoresist) using a lithography process, which has a circular opening O1 and exposes a portion of the interlayer dielectric layer 416 and the top of the entire contact plugs 418s, 418d, and 418g; then the interlayer dielectric layer 416 is etched to remove the exposed interlayer dielectric layer 416 but not to etch the contact plugs 418s, 418d, and 418g. If the structure has an etch stop layer 414, the etch stop layer 414 can be used as a stop layer for the etching process, so that the annular openings O2 are located above the etch stop layer 414. Since the contact plugs 418s, 418d and 418g generally have a cross-section that is wider at the top and narrower at the bottom, some interlayer dielectric layer 416 may be retained between the lower half of the annular opening O2 and the contact plugs 418s, 418d or 418g.

[0036] Referring to Figures 8A and 8B, after removing the patterned masking layer 420 in Figure 7B, an oxide material 422 is deposited on the substrate 400 to cover the upper part of each annular opening O2 and form an air gap AG therein. The oxide material 422 can be an oxide with poor trenching ability, such as a TEOS oxide or an oxide layer deposited by ALD; but is not limited thereto. In some embodiments, the oxide material 422 can be a material with a low dielectric constant. The position of the air gap AG can be controlled by the choice of process and material, and the air gap AG is formed within the entire annular opening O2 and around the contact plugs 418s, 418d, and 418g, thereby reducing the parasitic capacitance generated between the gate layer 408 and the contact plugs 418s, 418d, and the parasitic capacitance generated between adjacent contact plugs (e.g., contact plugs 418s and 418d, contact plugs 418g and 418d, or contact plugs 418g and 418s).

[0037] Referring to Figure 9, the oxide material 422 other than the annular opening O2 can be removed by methods such as oxide CMP, exposing the contact plugs 418s, 418d and 418g.

[0038] Referring to Figure 10, a conductor layer 424 is formed on the exposed contact plugs 418s, 418d, and 418g. In some embodiments, the conductor layer 424 is made of a metal, such as copper or aluminum.

[0039] Based on the above, the present invention uses an air gap surrounding the entire contact plug to reduce the parasitic capacitance generated between the gate and the contact plug, as well as the parasitic capacitance generated between adjacent contact plugs. Therefore, it can avoid problems such as RC delay and thus improve the device performance.

[0040] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0041] 100, 400: Base 101s, 401s: Source pole 101d, 401d: Drain 102, 402: Component isolation structure 104, 300, 404: Gate structure 106d, 106g, 106s, 302g, 418d, 418g, 418s: Contact plugs 108, 416: Interlayer dielectric layer 110 and 422 oxide materials 112. AG: Air gap 114, 406: Gate oxide layer 116, 408: Gate layer 118, 410: Spacer wall 120, 414: Etching stop layer 122, 412: Metal silicide layers 124, 424: Conductor layer 400s: surface 420: Patterned dome layer AA: Active Zone CO, O2: Annular opening O1: Circular opening

Claims

1. A semiconductor device, comprising: Base; A component isolation structure is provided in the substrate to define the active region; A gate structure is disposed on the substrate and spans the active region; A plurality of contact plugs are respectively disposed on both sides of the gate structure and on the gate structure; an interlayer dielectric layer covers the gate structure and has a plurality of annular openings, and each annular opening surrounds each contact plug. And an oxide material, filling the plurality of annular openings, and having a plurality of air gaps within the oxide material, wherein the plurality of air gaps surround the plurality of contact plugs, and the oxide material and the interlayer dielectric layer are between the air gaps and the contact plugs.

2. The semiconductor device as claimed in claim 1 further includes an etch stop layer conformally disposed on the surface of the gate structure.

3. The semiconductor device as claimed in claim 1, wherein the gate structure comprises: A gate oxide layer is formed on the surface of the active region; A gate layer is formed on the gate oxide layer; And the spacer wall, formed on the sidewall of the gate layer.

4. The semiconductor device as claimed in claim 3, wherein the active region includes a source and a drain, respectively formed on both sides of the gate structure.

5. The semiconductor device as claimed in claim 3 further includes a metal silicate layer disposed on the surfaces of the active region and the gate layer.

6. The semiconductor device of claim 1, wherein the plurality of air gaps surround the contact plugs of the plurality of contact plugs coupled to the gate structure and the contact plugs coupled to the drain of the active region.

7. The semiconductor device of claim 1, wherein the plurality of air gaps surround the contact plugs among the plurality of contact plugs coupled to the gate structure and the contact plugs coupled to the source and drain of the active region.

8. A method for manufacturing a semiconductor device, comprising: A component isolation structure is formed within the substrate to define the active region; A gate structure spanning the active region is formed on this substrate; An interlayer dielectric layer is formed on the substrate to cover the substrate and the gate structure; a plurality of contact plugs are formed in the interlayer dielectric layer to couple the active region and the gate structure respectively; a plurality of annular openings are formed in the interlayer dielectric layer, each annular opening surrounding each contact plug; And an oxide material is deposited on the substrate to cover the upper part of each of the annular openings and form an air gap therein, and the oxide material and the interlayer dielectric layer are between the air gap and each of the contact plugs.

9. A method of manufacturing a semiconductor device as claimed in claim 8, wherein after forming the air gap, the method further includes removing the oxide material other than the annular opening and exposing the plurality of contact plugs.

10. The method of manufacturing a semiconductor device as described in claim 9, further comprising: A conductor layer is formed on the exposed plurality of contact plugs.

11. A method of manufacturing a semiconductor device as claimed in claim 8, wherein prior to forming the interlayer dielectric layer, the method further comprises: An etch stop layer is conformally deposited on the surface of the gate structure.

12. A method of manufacturing a semiconductor device as claimed in claim 8, wherein the method of forming the gate structure comprises: A gate oxide layer is formed on the surface of the active region; A gate layer is formed on the gate oxide layer; And a gap wall is formed on the sidewall of the gate layer.

13. A method of manufacturing a semiconductor device as claimed in claim 12, wherein prior to forming the interlayer dielectric layer, the method further comprises: A metal silicate layer is formed on the surface of the active region and the surface of the gate layer.

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