Vertical device formed by self-aligned sequential patterning of top transistor and bottom transistor

Abstract

A method may include providing a nanosheet device stack that includes a lower patterned device stack and a upper patterned device stack, disposed above the lower patterned device stack, where the lower patterned device stack is disposed on a substrate base. The method may further include forming a lower dummy gate layer around the lower patterned device stack, and forming a upper dummy gate layer around the upper patterned device stack. The method may also include patterning the upper dummy gate layer to form a upper dummy gate around the upper patterned device stack, wherein an upper gate slot is formed. The method may also include patterning the lower dummy gate layer using the upper gate slot, wherein a gate slot is formed that extends through the lower patterned device stack and the upper patterned device stack.

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