Semiconductor device

Abstract

A semiconductor device includes a substrate having a first conductivity type. A trench is disposed in the substrate and extended along a first direction, and a gate electrode is disposed in the trench. A first body region having a second conductivity type is disposed in the substrate and located in a first area. A second body region having the second conductivity type is located in the first area, disposed directly below the first body region, and in direct contact with the first body region. The second body region has a doping concentration higher than that of the first body region. A source region having the first conductivity type is disposed in the first body region. A source contact passes through the source region and extends downward into the first body region. In addition, a drain region having the first conductivity type is disposed on the back side of the substrate.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor technology, and in particular to the structure of a semiconductor device incorporating transistors with different threshold voltages. [Previous Technology]

[0002] Power transistors are commonly used in power electronics technology. Power metal-oxide semiconductor field effect transistors (MOSFETs) are the most commonly used components in power conversion systems. They include horizontal structures, such as laterally-diffused metal-oxide semiconductor (LDMOS) MOSFETs, and vertical structures, such as trench gate MOSFETs. In the latter, the gate is located in a trench.

[0003] In recent years, in response to the development of various electronic products, the power and layout density of power MOSFETs have also increased. Trench gate MOSFETs have the advantages of reducing the size of component units and reducing parasitic capacitance, and are therefore widely used in many different fields, such as battery management, power supplies, and charging systems. However, conventional trench gate MOSFETs still have many aspects to be improved in order to meet the performance requirements of power transistors in various applications. [Summary of the Invention]

[0004] In view of this, the present disclosure proposes a semiconductor device whose structure includes transistors with different threshold voltages, thereby improving the safe operating area (SOA) to meet the performance requirements in various electronic circuit applications.

[0005] According to some embodiments of this disclosure, a semiconductor device is provided, including a substrate, a trench, a gate electrode, a first body region, a second body region, a source region, a source contact, and a drain region. The substrate has a first conductivity type, the trench extends along a first direction and is disposed in the substrate, and the gate electrode is disposed within the trench. The first body region has a second conductivity type and is disposed in the substrate, located within the first body region. The second body region has a second conductivity type and is located within the first body region, disposed directly below the first body region, contacting the first body region, and the doping concentration of the second body region is higher than that of the first body region. The source region has a first conductivity type and is disposed in the first body region. The source contact extends downward through the source region into the first body region. The drain region has a first conductivity type and is disposed on the back side of the substrate.

[0006] According to some embodiments of this disclosure, a semiconductor device is provided, including a substrate, a trench, a gate electrode, a source region, and a body region. The substrate has a first conductivity type, the trench extends along a first direction and is disposed in the substrate, and the gate electrode is disposed within the trench. The source region has a first conductivity type and is close to the gate electrode. The body region extends along the first direction and includes a first segment and a second segment, wherein the first segment includes the first body region and the second body region, the second segment includes the first body region, and the doping concentration of the second body region is higher than the doping concentration of the first body region. The first segment constitutes a part of a first transistor having a first threshold voltage, and the second segment constitutes a part of a second transistor having a second threshold voltage, and the first threshold voltage is higher than the second threshold voltage.

[0007] According to one embodiment of the present disclosure, a semiconductor device is provided, including a substrate, a trench, a gate electrode, a source region, and a plurality of body regions. The substrate has a first conductivity type, the trench extends along a first direction and is disposed in the substrate, and the gate electrode is disposed within the trench. The source region has a first conductivity type and is adjacent to the gate electrode. The plurality of body regions extend along the first direction and are spaced apart by the substrate. The surface of each body region adjacent to the substrate includes a bottom surface extending along the first direction and a side surface extending along a third direction. Each body region includes a first body region with lower doping and a second body region with higher doping, the second body region being disposed below the first body region. When a bias voltage is applied to the gate electrode, a first current channel and a second current channel are formed. The first current channel enters each body region from the bottom surface, passes through the second body region and the first body region to reach the source region; the second current channel enters each body region from the side surface, passes only through the first body region but not through the second body region to reach the source region.

Implementation Method

[0008] This disclosure provides several different embodiments that can be used to implement different features of this disclosure. For the sake of simplicity, this disclosure also describes examples of specific components and arrangements. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following statement regarding "a first feature is formed on or above a second feature" may mean "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments in this disclosure may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate any correlation between different embodiments and / or configurations.

[0009] Furthermore, regarding the spatially related descriptive terms mentioned in this disclosure, such as "below," "low," "down," "above," "above," "up," "top," "bottom," and similar terms, for ease of description, their usage is to describe the relative relationship between one element or feature and another (or more) elements or features in the diagram. In addition to the orientation shown in the diagram, these spatially related terms are also used to describe the possible orientation of the semiconductor device during use and operation. As the orientation of the semiconductor device varies (rotation of 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0010] Although this disclosure uses terms such as first, second, third, etc., to describe various elements, components, regions, layers, and / or sections, it should be understood that such elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another element, component, region, layer, and / or section, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of this disclosure, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0011] The terms "about" or "substantially" used in this disclosure generally mean within 20%, more preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate quantities, that is, the meaning of "about" or "substantially" may be implied even without specific description of "about" or "substantially".

[0012] The terms “coupled,” “coupled,” and “electrically connected” used in this disclosure include any means of direct or indirect electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other means of connection.

[0013] Although the invention disclosed herein is described below by way of specific embodiments, the inventive principles disclosed herein can also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details have been omitted, and these omitted details are within the knowledge scope of those skilled in the art.

[0014] This disclosure relates to the structure of a semiconductor device containing transistors with different threshold voltages. Some embodiments of this disclosure, through the configuration of source contacts, source regions and / or body regions, wherein the body region includes a first body region with lower doping and a second body region with higher doping, enable the semiconductor device to achieve parallel electrical connection of a first transistor with a first threshold voltage to a second transistor with a second threshold voltage without external circuit control, thereby improving the safe operating area (SOA) of the semiconductor device and meeting the performance requirements of power components in various electronic circuit applications.

[0015] Figure 1 is a top view of a semiconductor device 100A according to an embodiment of the present disclosure, wherein the dashed frame indicates a first region 101 and a second region 102, the second region 102 being located between the two first regions 101. Figure 2 is a cross-sectional view of the semiconductor device 100A drawn along the tangent line AA in Figure 1 according to an embodiment of the present disclosure. Figure 3 is a cross-sectional view of the semiconductor device 100A according to some embodiments of the present disclosure, wherein the cross-sections (a) and (b) are both obtained along the tangent line BB in Figure 1, (a) of Figure 3 is an embodiment of the semiconductor device 100A without the field plate 116, and (b) of Figure 3 is another embodiment of the semiconductor device 100A including the field plate 116. Referring to Figures 1 and 3, semiconductor device 100A includes a substrate 103, a trench 110, a gate electrode 114, a body region 130, a source region 140, a source contact 120, a drain region 160, and a drain electrode 170. In some embodiments, the substrate 103 has a first conductivity type, such as an N-type semiconductor substrate, and the substrate 103 may also be referred to as an N-drift region. The trench 110 extends along a first direction (e.g., the Y-axis direction) and is disposed in the substrate 103. In one embodiment, as shown in Figure 3(a), the gate electrode 114 and a dielectric layer 112 are disposed within the trench 110, and the dielectric layer 112 surrounds the side and bottom surfaces of the gate electrode 114, and the dielectric layer 112 may serve as a gate dielectric layer. In another embodiment, as shown in Figure 3(b), a gate electrode 114, a dielectric layer 112A, a field plate 116, and a dielectric layer 112B may be disposed within the trench 110. The field plate 116 is disposed below the gate electrode 114 and longitudinally separated from it. The field plate 116 can disperse the electric field, which helps to improve the breakdown voltage of the semiconductor device. The dielectric layer 112A surrounds the side and bottom surfaces of the gate electrode 114, and the dielectric layer 112B surrounds the side and bottom surfaces of the field plate 116. The dielectric layer 112A can serve as the gate dielectric layer. In some embodiments, the gate electrode 114 and the field plate 116 are composed, for example, polycrystalline silicon, and the dielectric layers 112A, 112B are composed, for example, silicon oxide, silicon nitride, or a combination thereof.

[0016] Referring to Figures 1 and 3, the body region 130 has a second conductivity type, such as a P-type doped region, and is disposed in the substrate 103 and located within the first region 101. The body region 130 includes a first body region 131 and a second body region 132, wherein the second body region 132 is disposed directly below the first body region 131 and contacts the first body region 131, and the doping concentration of the second body region 132 is higher than that of the first body region 131. Furthermore, the bottom surface of the second body region 132 is higher than the bottom surface of the gate electrode 114. The source region 140 has a first conductivity type, such as an N-type heavily doped region, and is disposed in the first body region 131. An interlayer dielectric layer 180 is disposed above the substrate 103, and the source contact 120 extends downward into the first body region 131 through the interlayer dielectric layer 180 and the source region 140. Furthermore, the semiconductor device 100A also includes a heavily doped region 134 having a second conductivity type, such as a P-type heavily doped region, disposed directly below the source contact 120 and contacting the bottom of the source contact 120. The heavily doped region 134 is embedded in the first body region 131 and contacts the second body region 132, and the doping concentration of the heavily doped region 134 is higher than the doping concentration of the second body region 132. In some embodiments, the bottom surface of the heavily doped region 134 may be located in the first body region 131 or the second body region 132, or the bottom surface of the heavily doped region 134 may be on the same plane as the top surface of the second body region 132. Since the doping concentration of the heavily doped region 134 is higher than the doping concentration of the first body region 131 and the second body region 132 respectively, the parasitic bipolar junction transistor (BJT) effect can be reduced by the arrangement of the heavily doped region 134, which is beneficial to reducing the on-resistance of the semiconductor device.

[0017] Referring to Figures 1 and 2, the source contact 120 includes a first portion 121 and a second portion 122 separated in a first direction (e.g., the Y-axis direction), and the first portion 121 and the second portion 122 are respectively located within two first regions 101. A portion 103P of the substrate is located within the second region 102, adjacent to the side of the first body region 131 and the side of the second body region 132, and the portion 103P of the substrate is located between the first portion 121 and the second portion 122 of the source contact 120. Furthermore, the drain region 160 has a first conductivity type, such as an N-type heavily doped region, and is disposed on the back side of the substrate 103, and the drain electrode 170 is disposed below the drain region 160. When the semiconductor device 100A is turned on, current flows vertically upward from the drain region 160 through the substrate 103 and flows to the source region 140. In addition, the source region 140 shown in Figure 2 is a view of the relative position of the source region 140 and the source contact 120 from the YZ plane direction. The source region 140 is laterally adjacent to the source contact 120 in the X-axis direction. The source region 140 is not located in the source contact 120, and the bottom surface of the source region 140 is higher than the bottom surface of the source contact 120.

[0018] Additionally, referring to Figures 1 and 2, the semiconductor device 100A includes a plurality of body regions 130 extending along a first direction (e.g., the Y-axis direction). These body regions 130 are spaced apart by a portion 103P of a substrate. As shown in Figure 2, the surface of each body region 130 adjacent to the substrate 103 includes a bottom surface BS extending along the first direction (e.g., the Y-axis direction) and a side surface SW extending along a third direction (e.g., the Z-axis direction). Furthermore, each of the body regions 130 includes a first body region 131 with lower doping and a second body region 132 with higher doping, and the second body region 132 is disposed below the first body region 131. When a bias voltage is applied to the gate electrode 114 in the trench 110, a first current channel 151 and a second current channel 152 are formed. The first current channel 151 enters each body region 130 from the bottom surface BS, passes through the second body region 132 and the first body region 131, and reaches the source region 140. The second current channel 152 enters each body region 130 from the side surface SW, passes through only the first body region 131, but does not pass through the second body region 132, and reaches the source region 140. The first current channel 151 has a first path length L1 passing through the first body region 131, and the second current channel 152 has a second path length L2 passing through the first body region 131, and the first path length L1 is less than the second path length L2.

[0019] Referring to Figure 2, in semiconductor device 100A, the second body region 132 and the first body region 131 in the first region 101 constitute a part of the first transistor. The first transistor has a first threshold voltage. The first current channel 151 flows vertically from the substrate 103 through the second body region 132 and the first body region 131 in sequence, and flows to the source region 140. In addition, the first body region 131 in the first region 101 constitutes a part of the second transistor. The second transistor has a second threshold voltage. The second current channel 152 first flows vertically upward from the substrate 103, then flows laterally from a portion 103P of the substrate through the first body region 131, and flows to the source region 140. Since the first path length L1 of the first current channel 151 through the first body region 131 is less than the second path length L2 of the second current channel 152 through the first body region 131, and the first current channel 151 also flows through the second body region 132 with higher doping compared to the second current channel 152, the first threshold voltage of the first transistor is higher than the second threshold voltage of the second transistor, so that the semiconductor device 100A can provide two transistors with different threshold voltages and connected in parallel.

[0020] Figure 4 is a top view of a semiconductor device 100B according to another embodiment of the present disclosure, wherein the dashed frame indicates the first region 101 and the first segment 130A and the second segment 130B of the body region 130. Figure 5 is a cross-sectional view of a semiconductor device 100B according to some embodiments of the present disclosure, wherein (a) and (b) are cross-sections of the second transistor 100B2 taken along the cross-sectional tangent DD in Figure 4, and (c) and (d) are cross-sections of the first transistor 100B1 taken along the cross-sectional tangent CC in Figure 4. Figure 5(a) and (c) are embodiments of the semiconductor device 100B without the field plate 116, and Figure 5(b) and (d) are embodiments of the semiconductor device 100B including the field plate 116. Referring to Figure 4, the source contact 120 of the semiconductor device 100B includes a first portion 121 and a second portion 122 interconnected in a first direction (e.g., the Y-axis direction). In a second direction (e.g., the X-axis direction), the first portion 121 has a first width W1, and the second portion 122 has a second width W2, with the first width W1 being greater than the second width W2. Additionally, referring to Figure 5, the semiconductor device 100B also includes a heavily doped region 134 having a second conductivity type, such as a P-type heavily doped region, disposed directly below the source contact 120 and contacting the bottom of the source contact 120. The heavily doped region 134 includes a first heavily doped region 134A and a second heavily doped region 134B. In the embodiment of Figure 4, the first heavily doped region 134A is formed by etching the first portion 121 of the source contact 120 during the fabrication process, and the second heavily doped region 134B is formed by etching the second portion 122 of the source contact 120. Thus, in the second direction (e.g., the X-axis direction), the width of the first heavily doped region 134A can be correspondingly greater than the width of the second heavily doped region 134B.

[0021] Referring to (c) and (d) of Figure 5, a first distance d1 is present between the first portion 121 of the source contact 120 and the trench 110, and the first portion 121 of the source contact 120 can provide a first transistor 100B1 having a first threshold voltage. Furthermore, a first heavily doped region 134A has a second conductivity type, such as a P-type heavily doped region, and is disposed directly below the first portion 121 of the source contact 120 and contacts the bottom of the first portion 121. The doping concentration of the first heavily doped region 134A is higher than the doping concentration of the second body region 132. The first heavily doped region 134A is buried in the first body region 131 and contacts the second body region 132.

[0022] Referring to Figures 5(a) and (b), a second distance d2 exists between the second portion 122 of the source contact 120 and the trench 110, wherein the first distance d1 is smaller than the second distance d2, and the second portion 122 of the source contact 120 can provide a second transistor 100B2 having a second threshold voltage. Furthermore, a second heavily doped region 134B has a second conductivity type, such as a P-type heavily doped region, and is disposed directly below the second portion 122 of the source contact 120, contacting the bottom of the second portion 122. The doping concentration of the second heavily doped region 134B is the same as the doping concentration of the first heavily doped region 134A. The second heavily doped region 134B is buried in the first body region 131 and contacts the second body region 132.

[0023] Furthermore, in some embodiments, as shown in Figures 5(a) and (c), the gate electrode 114 and the dielectric layer 112 are disposed within the trench 110, and the dielectric layer 112 can serve as the gate dielectric layer, surrounding the side and bottom surfaces of the gate electrode 114. In other embodiments, as shown in Figures 5(b) and (d), a field plate 116 can also be disposed directly below the gate electrode 114 within the trench 110, and the field plate 116 is longitudinally separated from the gate electrode 114. The dielectric layer 112A can serve as the gate dielectric layer, surrounding the gate electrode 114, and the dielectric layer 112B surrounds the field plate 116. The electric field can be dispersed by the field plate 116, which helps to improve the breakdown voltage of the semiconductor device 100B.

[0024] Referring to Figures 4 and 5, the body region 130 of the semiconductor device 100B extends along a first direction (e.g., the Y-axis direction) and includes a first segment 130A and a second segment 130B. The first segment 130A constitutes a part of a first transistor 100B1, which has a first threshold voltage. The cross-section of the first segment 130A is shown in Figures 5(c) and (d), and it includes a first body region 131 and a second body region 132, with the doping concentration of the second body region 132 being higher than that of the first body region 131. Additionally, the second segment 130B constitutes a part of a second transistor 100B2, which has a second threshold voltage. The cross-section of the second segment 130B is shown in Figures 5(a) and (b), and it also includes the first body region 131 and the second body region 132. Source region 140 is disposed in the first body region 131 of both the first segment 130A and the second segment 130B. Source contact 120 extends along a first direction (e.g., the Y-axis direction) and includes a first portion 121 and a second portion 122, wherein the first portion 121 is located in the first segment 130A and the second portion 122 is located in the second segment 130B. Furthermore, a first heavily doped region 134A is located in the first segment 130A, and a second heavily doped region 134B is located in the second segment 130B. The size of the first heavily doped region 134A is larger than the size of the second heavily doped region 134B.

[0025] In the semiconductor device 100B, the first width W1 of the first portion 121 of the source contact 120 is greater than the second width W2 of the second portion 122. Therefore, in the second direction (e.g., the X-axis direction), the first distance d1 between the first portion 121 and the trench 110 is less than the second distance d2 between the second portion 122 and the trench 110. Furthermore, in the process of manufacturing the semiconductor device 100B, the first heavily doped region 134A is formed by etching the opening of the first portion 121 of the source contact 120, and the second heavily doped region 134B is formed by etching the opening of the second portion 122 of the source contact 120. Thus, the width of the first heavily doped region 134A is correspondingly greater than the width of the second heavily doped region 134B, resulting in a higher concentration of the second conductivity type dopant in the body region 130 within the first segment 130A and a lower concentration of the second conductivity type dopant in the body region 130 within the second segment 130b. This causes the first threshold voltage of the first transistor 100B1 to be higher than the second threshold voltage of the second transistor 100B2, thereby allowing the semiconductor device 100B to provide two transistors with different threshold voltages connected in parallel. Other components of the semiconductor device 100B can be found in the descriptions in Figures 2 and 3 above, and will not be repeated here.

[0026] Figure 6 is a top view of a semiconductor device 100C according to another embodiment of the present disclosure, wherein the frame lines indicate the first region 101 and the second region 102, and the first segment 130A and the second segment 130B of the body region 130. Figure 7 is a cross-sectional view of a semiconductor device 100C according to some embodiments of the present disclosure, wherein (a) and (b) are cross-sections of the second transistor 100C2 taken along the tangent line FF of the cross-section located in the second segment 130B in Figure 6, and (c) and (d) are cross-sections of the first transistor 100C1 taken along the tangent line EE of the cross-section located in the first segment 130A in Figure 6; (a) and (c) of Figure 7 are embodiments of the semiconductor device 100C without the field plate 116, and (b) and (d) of Figure 7 are other embodiments of the semiconductor device 100C including the field plate 116. Referring to Figures 6 and 7, in semiconductor device 100C, second region 102 is adjacent to first region 101, and the first body region 131, source region 140, and source contact 120 of body region 130 all extend laterally from first region 101 into second region 102 along a first direction (e.g., the Y-axis direction). However, the second body region 132 of body region 130 is not disposed within second region 102; the second body region 132 is only disposed in region PB2, wherein the doping concentration of the second body region 132 is higher than that of the first body region 131. Referring to Figures 6 and 7, by having different configurations of the first body region 131 and the second body region 132 within first region 101 and second region 102, semiconductor device 100C's first region 101 can provide a first transistor 100C1 with a first threshold voltage, and the second region 102 can provide a second transistor 100C2 with a second threshold voltage, wherein the first threshold voltage is higher than the second threshold voltage.

[0027] Referring to Figure 7, the semiconductor device 100C further includes a heavily doped region 134 having a second conductivity type, such as a P-type heavily doped region, disposed directly below the source contact 120 and contacting the bottom of the source contact 120, and the doping concentration of the heavily doped region 134 is higher than the doping concentration of the second body region 132. Furthermore, the heavily doped region 134 is buried in the first body region 131 of both the first region 101 and the second region 102, and the heavily doped region 134 in the first region 101 can contact the second body region 132. Additionally, in some embodiments, as shown in Figures 7(a) and (c), a gate electrode 114 and a dielectric layer 112 are disposed within the trench 110. In other embodiments, as shown in (b) and (d) of Figure 7, a gate electrode 114, a field plate 116, a dielectric layer 112A and a dielectric layer 112B are disposed in the trench 110. For details of these components, please refer to the relevant description in Figure 5 above, and will not be repeated here.

[0028] Referring again to Figures 6 and 7, the body region 130 extends along a first direction (e.g., the Y-axis direction) and includes a first segment 130A and a second segment 130B. The cross-section of the first segment 130A is shown in Figures 7(c) and (d), and it includes a first body region 131 and a second body region 132. The cross-section of the second segment 130B is shown in Figures 7(a) and (b), and it includes the first body region 131 but does not include the second body region 132. Furthermore, the source region 140 of the semiconductor device 100C is disposed in the first body region 131 and extends simultaneously into the first segment 130A and the second segment 130B. The first segment 130A constitutes a part of the first transistor 100C1, and causes the first transistor 100C1 to have a first threshold voltage. The second segment 130B constitutes a part of the second transistor 100C2, and causes the second transistor 100C2 to have a second threshold voltage. Since the first segment 130A contains an additional second body region 132 with a higher dopant concentration than the second segment 130B, the first threshold voltage of the first transistor 100C1 is higher than the second threshold voltage of the second transistor 100C2.

[0029] In the semiconductor device 100C, the body region 130 of the first region 101 includes a second body region 132, while the body region 130 in the second region 102 does not include the second body region 132. By different configurations of the second body region 132 in different regions, the semiconductor device 100C can provide two transistors with different threshold voltages connected in parallel. Other components of the semiconductor device 100C can be referred to in the descriptions of Figures 2 and 3 above, and will not be repeated here.

[0030] Figure 8 is a top view of a semiconductor device 100D according to another embodiment of the present disclosure, wherein the frame lines indicate the first region 101 and the second region 102, and the first segment 130A and the second segment 130B of the body region 130. Figure 9 is a cross-sectional view of a semiconductor device 100D according to some embodiments of the present disclosure, wherein (a) and (b) are cross-sections of the second transistor 100D2 taken along the cross-sectional tangent HH in Figure 8, and (c) and (d) are cross-sections of the first transistor 100D1 taken along the cross-sectional tangent GG in Figure 8; Figure 9(a) and (c) are embodiments of the semiconductor device 100D without the field plate 116, and Figure 9(b) and (d) are other embodiments of the semiconductor device 100D including the field plate 116. Referring to Figure 8, in semiconductor device 100D, second region 102 is adjacent to first region 101, and both first body region 131 and source contact 120 extend laterally from first region 101 into second region 102 along a first direction (e.g., the Y-axis direction). However, second body region 132 and source region 140 are only disposed within first region 101, but not within second region 102. Referring to Figures 8 and 9, in semiconductor device 100D, as shown in Figures 9(c) and (d), first region 101 includes second body region 132 and source region 140; as shown in Figures 9(a) and (b), second region 102 does not include second body region 132 and source region 140, such that first region 101 can provide a first transistor 100D1 with a first threshold voltage, and second region 102 provides a second transistor 100D2 with a second threshold voltage, wherein the first threshold voltage is higher than the second threshold voltage.

[0031] Referring to Figure 9, the semiconductor device 100D further includes a heavily doped region 134 having a second conductivity type, such as a P-type heavily doped region, disposed directly below the source contact 120 and contacting the bottom of the source contact 120, and the doping concentration of the heavily doped region 134 is higher than the doping concentration of the second body region 132. Furthermore, the heavily doped region 134 is buried in the first body region 131 of the first region 101 and the second region 102, and the heavily doped region 134 in the first region 101 can contact the second body region 132.

[0032] Referring again to Figures 8 and 9, the body region 130 extends along a first direction (e.g., the Y-axis direction) and includes a first segment 130A and a second segment 130B. The cross-section of the first segment 130A is shown in Figures 9(c) and (d), including a source region 140, a first body region 131, and a second body region 132, with the doping concentration of the second body region 132 being higher than that of the first body region 131. The cross-section of the second segment 130B is shown in Figures 9(a) and (b), including the first body region 131 but excluding the second body region 132 and the source region 140. The first segment 130A constitutes a part of the first transistor 100D1, giving the first transistor 100D1 a first threshold voltage. The second segment 130B constitutes a part of the second transistor 100D2, giving the second transistor 100D2 a second threshold voltage.

[0033] Regarding the first transistor 100D1, since the first segment 130A includes a second body region 132 and a source region 140 more than the second segment 130B, the current of the first transistor 100D1 can flow sequentially from the bottom surface of the first transistor 100D1 through the second body region 132 and the first body region 131, and then flow upwards to the source region 140. Regarding the second transistor 100D2, since the second segment 130B does not have a second body region 132 and a source region 140, the current of the second transistor 100D2 first flows upwards through the first body region 131, and then flows laterally along the first direction (e.g., the Y-axis direction) to the source region 140 in the first segment 130A.

[0034] In the semiconductor device 100D, a source region 140 is disposed within the body region 130 of the first region 101, and a second body region 132 with a high doping concentration is also provided. The body region 130 of the second region 102 does not include a second body region 132 and does not have a source region 140, but only a first body region 131 with a low doping concentration. By using different configurations of the second body region 132 and the source region 140 in different regions, the semiconductor device 100D can provide two transistors with different threshold voltages connected in parallel. Other components of the semiconductor device 100D can be referred to in the descriptions of Figures 2, 3, and 5 above, and will not be repeated here.

[0035] According to some embodiments of this disclosure, by configuring the source contact, source region, body region, and / or second body region differently in different areas of the semiconductor device, or by adjusting the width of the source contact, different transistors with different threshold voltages connected in parallel can be generated in the semiconductor device without external circuit control. This improves the safe operating area (SOA) of the semiconductor device to meet the performance requirements of power components in various electronic circuit applications. Furthermore, according to the semiconductor device disclosed herein, different transistors with different threshold voltages can be formed simultaneously in the same process step, without the need for additional process steps and photomasks, and is compatible with current semiconductor processes, thereby saving manufacturing costs. The above are merely preferred embodiments of the present invention. All equivalent variations and modifications made within the scope of the claims of this invention should be considered within the scope of this invention. [Simplified Explanation of the Diagram]

[0036] To make the following text easier to understand, reference can be made to the drawings and detailed textual descriptions while reading this disclosure. The specific embodiments described herein, along with the corresponding drawings, are explained in detail to illustrate the working principles of the specific embodiments of this disclosure. Furthermore, for clarity, the features in the drawings may not be drawn to scale, and therefore the dimensions of some features in certain drawings may be intentionally enlarged or reduced. Figure 1 is a top view of a semiconductor device according to an embodiment of this disclosure, wherein the frame lines indicate a first region and a second region. Figure 2 is a cross-sectional view of a semiconductor device drawn along the tangent line AA in Figure 1 according to an embodiment of this disclosure. Figure 3 is a cross-sectional view of a semiconductor device according to some embodiments of this disclosure, wherein the cross-sections (a) and (b) are obtained along the tangent line BB in Figure 1. Figure 4 is a top view of a semiconductor device according to another embodiment of this disclosure, wherein the frame lines indicate a first region, and a first segment and a second segment of the body region. Figure 5 is a cross-sectional schematic diagram of a semiconductor device according to some embodiments of the present disclosure, wherein (a) and (b) are cross-sections of the second transistor taken along the tangent line DD in Figure 4, and (c) and (d) are cross-sections of the first transistor taken along the tangent line CC in Figure 4. Figure 6 is a top view schematic diagram of a semiconductor device according to another embodiment of the present disclosure, wherein the frame lines indicate the first region and the second region, as well as the first segment and the second segment of the body region. Figure 7 is a cross-sectional schematic diagram of a semiconductor device according to some embodiments of the present disclosure, wherein (a) and (b) are cross-sections of the second transistor taken along the tangent line FF in Figure 6, and (c) and (d) are cross-sections of the first transistor taken along the tangent line EE in Figure 6. Figure 8 is a top view schematic diagram of a semiconductor device according to another embodiment of the present disclosure, wherein the frame lines indicate the first region and the second region, as well as the first segment and the second segment of the body region. Figure 9 is a schematic cross-sectional view of a semiconductor device illustrated according to some embodiments of the present disclosure, wherein (a) and (b) are cross-sections of a second transistor taken along the cross-sectional tangent HH in Figure 8, and (c) and (d) are cross-sections of a first transistor taken along the cross-sectional tangent GG in Figure 8.

Claims

1. A semiconductor device, comprising: A substrate having a first conductivity type; A groove, extending along a first direction, is disposed in the substrate; A gate electrode is disposed within the trench; a first body region having a second conductivity type is disposed in the substrate and located within the first region; a second body region having the second conductivity type is located within the first region, disposed directly below the first body region, in contact with the first body region, and the doping concentration of the second body region is higher than that of the first body region; a source region having the first conductivity type is disposed within the first body region; a source contact extends downward through the source region into the first body region; And a drain electrode region having the first conductivity type is disposed on the back side of the substrate.

2. The semiconductor device as claimed in claim 1 further includes a second region located between the two first regions, wherein the source contact includes a first portion and a second portion separated in the first direction, respectively located within the two first regions.

3. The semiconductor device as claimed in claim 2, wherein a portion of the substrate is located within the second region, adjacent to the side of the first body region and the side of the second body region, and the portion of the substrate is located between the first portion and the second portion of the source contact.

4. The semiconductor device as claimed in claim 3, wherein the first body region in the first region constitutes part of a second transistor, the second transistor having a second threshold voltage, a second current channel flowing laterally through the first body region from the portion of the substrate, the second body region and the first body region in the first region constitute part of a first transistor, the first transistor having a first threshold voltage, a first current channel flowing vertically sequentially through the second body region and the first body region from the substrate, and the first threshold voltage being higher than the second threshold voltage.

5. The semiconductor device as claimed in claim 1, wherein the source contact includes a first portion having a first width in a second direction and a second portion having a second width, and the first width is greater than the second width.

6. The semiconductor device as claimed in claim 5, wherein a first distance is provided between the first portion of the source contact and the trench, a second distance is provided between the second portion of the source contact and the trench, and the first distance is less than the second distance.

7. The semiconductor device as claimed in claim 5, wherein the first portion and the second portion of the source contact are interconnected, the first portion provides a first transistor having a first threshold voltage, the second portion provides a second transistor having a second threshold voltage, and the first threshold voltage is higher than the second threshold voltage.

8. The semiconductor device as claimed in claim 5 further includes a first heavily doped region having the second conductivity type, disposed directly below the first portion of the source contact, in contact with the first portion, and wherein the doping concentration of the first heavily doped region is higher than the doping concentration of the second body region.

9. The semiconductor device as claimed in claim 8 further includes a second heavily doped region having the second conductivity type, disposed directly below the second portion of the source contact, contacting the second portion, wherein in the second direction, the width of the first heavily doped region is greater than the width of the second heavily doped region, and both the first heavily doped region and the second heavily doped region are embedded in the first body region.

10. The semiconductor device as claimed in claim 1, further comprising a second region adjacent to the first region, wherein the first body region, the source region and the source contact all extend laterally from the first region into the second region, and the second body region is not disposed within the second region.

11. The semiconductor device of claim 10, wherein the first region provides a first transistor having a first threshold voltage, the second region provides a second transistor having a second threshold voltage, and the first threshold voltage is higher than the second threshold voltage.

12. The semiconductor device as claimed in claim 1 further includes a second region adjacent to the first region, wherein the first body region and the source contact both extend laterally from the first region into the second region, and neither the second body region nor the source region is disposed within the second region.

13. The semiconductor device of claim 12, wherein the first region provides a first transistor having a first threshold voltage, the second region provides a second transistor having a second threshold voltage, and the first threshold voltage is higher than the second threshold voltage.

14. The semiconductor device as claimed in claims 1, 10 or 12 further includes a heavily doped region having the second conductivity type, disposed directly below the source contact, contacting the bottom of the source contact, and the doping concentration of the heavily doped region is higher than the doping concentration of the second body region.

15. The semiconductor device of claim 14, wherein the heavily doped region is buried in the first body region and the heavily doped region in the first body region contacts the second body region.

16. A semiconductor device, comprising: A substrate having a first conductivity type; A groove, extending along a first direction, is disposed in the substrate; A gate electrode is disposed within the trench; a source region having the first conductivity type is located close to the gate electrode; and a body region extending along the first direction includes a first segment and a second segment, the first segment including a first body region and a second body region, the second segment including the first body region, and the doping concentration of the second body region being higher than that of the first body region; wherein the first segment constitutes part of a first transistor having a first threshold voltage, the second segment constitutes part of a second transistor having a second threshold voltage, and the first threshold voltage being higher than the second threshold voltage.

17. The semiconductor device as claimed in claim 16, wherein the second segment does not include the second body region, and the source region is disposed in the first body region of both the first segment and the second segment.

18. The semiconductor device as claimed in claim 16, wherein the second segment does not include the second body region, and the source region is disposed in the first segment but not in the second segment.

19. The semiconductor device of claim 16, wherein the second segment further includes the second body region, and the source region is disposed in the first body region of both the first segment and the second segment, the semiconductor device further comprising: A source contact extends along the first direction and includes a first portion and a second portion. In a second direction, the width of the first portion is greater than the width of the second portion, wherein the first portion is located in the first segment and the second portion is located in the second segment.

20. The semiconductor device as claimed in claim 19, further comprising: A heavily doped region having a second conductivity type is disposed directly below the source contact and in contact with the bottom of the source contact, including a first heavily doped region and a second heavily doped region, respectively located in the first segment and the second segment, wherein the size of the first heavily doped region is larger than the size of the second heavily doped region.

21. A semiconductor device, comprising: A substrate having a first conductivity type; A groove, extending along a first direction, is disposed in the substrate; A gate electrode is disposed within the trench; a source region having the first conductivity type is located adjacent to the gate electrode; and a plurality of body regions extending along the first direction, the plurality of body regions being spaced apart by the substrate, each body region having a bottom surface extending along the first direction and a side surface extending along a second direction adjacent to the substrate; wherein each body region includes a first body region with lower doping and a second body region with higher doping, the second body region being disposed below the first body region; and when the gate electrode is biased, a first current channel and a second current channel are formed, the first current channel entering each body region from the bottom surface, passing through the second body region and the first body region to reach the source region; the second current channel entering each body region from the side surface, passing only through the first body region but not through the second body region to reach the source region.

22. The semiconductor device as claimed in claim 21, wherein the first current channel has a first path length through the first body region, the second current channel has a second path length through the first body region, and the first path length is less than the second path length.

Images