Semiconductor layout pattern and manufacturing method thereof

Abstract

The invention provides a semiconductor layout pattern, which comprises a substrate, wherein the substrate comprises a plurality of ternary content addressable memory (TCAM) cells, wherein the layouts of at least two TCAM cells are mirror symmetrical to each other along a symmetry axis, and each TCAM cell comprises a plurality of transistors. The substrate comprises a plurality of fin structures arranged in a Y direction and a plurality of gate structures arranged along an X direction, wherein the gate structures comprise a first gate structure connected with a search line SLB and a second gate structure not connected with the search line SLB, wherein the first gate structure is arranged in parallel with the second gate structure, the first gate structure does not overlap with the symmetry axis, and the second gate structure overlaps with the symmetry axis.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a layout pattern of a Content Addressable Memory (CAM) and a method for manufacturing it. Prior Technology

[0002] Generally, when performing digital data operations, the amount of data to be processed is enormous. Some applications (such as network routers) require large amounts of dynamically updated stored data, which cannot be pre-sorted, making real-time data retrieval difficult. To effectively speed up data searching for this large amount of randomly stored data, Content Addressable Memory (CAM) is used to solve various search problems. Content Addressable Memory (also known as associative memory) acts like a large lookup table, finding the addresses of matching keywords based on the input keywords. This is achieved through a special hardware architecture design of CAM, allowing the searched keywords to be compared simultaneously with the data stored in the CAM, and outputting the addresses of data matching the input keywords. The data associated with the keywords can then be found using the keyword addresses found by the CAM.

[0003] Content-addressable memory can include binary content-addressable memory (BCAM) and tertiary content-addressable memory (TCAM). In BCAM, each bit has two states, 0 or 1, while in TCAM, each bit has three states: 0, 1, and a "don't care" state, hence the name "tertiary". It is this third state feature of TCAM that enables both exact match searches and fuzzy match searches. Summary of the Invention

[0004] This invention provides a semiconductor layout pattern comprising a substrate on which a plurality of ternary content addressable memory (TCAM) cells are included, wherein at least two TCAM cells are mirror-symmetrical about each other along an axis of symmetry, and each TCAM cell includes a plurality of transistors. The substrate includes a plurality of fin structures arranged in a Y direction and a plurality of gate structures arranged in an X direction, wherein some of the gate structures span the fin structures and constitute the plurality of transistors of the TCAM cell, wherein the plurality of gate structures includes a first gate structure connected to a search line (SLB) and a second gate structure not connected to the SLB, wherein the first gate structure and the second gate structure are arranged parallel to each other and the first gate structure does not overlap with the axis of symmetry, while the second gate structure overlaps with the axis of symmetry.

[0005] The present invention further provides a method for fabricating a semiconductor layout pattern, comprising providing a substrate and forming a plurality of ternary content addressable memory (TCAM) cells on the substrate, wherein the layout of at least two TCAM cells is mirror-symmetrical about each other along an axis of symmetry, wherein each TCAM cell includes a plurality of transistors, the substrate includes a plurality of fin structures arranged in a Y direction and a plurality of gate structures arranged in an X direction, wherein some of the gate structures span the fin structures and constitute the plurality of transistors of the TCAM cell, wherein the plurality of gate structures includes a first gate structure connected to a search line SLB and a second gate structure not connected to the search line SLB, wherein the first gate structure and the second gate structure are arranged in parallel and the first gate structure does not overlap with the axis of symmetry, while the second gate structure overlaps with the axis of symmetry.

[0006] The present invention is characterized in that, when two Tri-State Addressable Memory Cells (TCAMs) are arranged on a substrate, if the gate structure is directly divided at the junction of the two TCAMs by a continuous strip cutting pattern, uneven pattern density is likely to occur. To solve this problem, in the present invention, the cutting area at the junction of the two TCAMs is divided into multiple segments, arranged in an alternating manner in, for example, a rhomboid shape. In this way, the gate structure after cutting will be more uniformly distributed, which is beneficial to improving the overall quality of the semiconductor device. In addition, the present invention connects the first metal layer, which is prone to coupling effects, to the voltage source through the upper contact plug to avoid the occurrence of coupling effects. Furthermore, in some embodiments of the present invention, in addition to forming a fin structure, multiple dummy fin structures are also formed and distributed next to the fin structure, which can improve the pattern uniformity of the overall layout. Simple Explanation of the Diagram

[0007] To facilitate understanding of the following text, reference should be made to the accompanying drawings and detailed textual descriptions while reading this invention. The specific embodiments described herein, along with the corresponding drawings, are used to explain in detail the specific embodiments of the invention and to elucidate the working principles of these embodiments. Furthermore, for clarity, the features in the drawings may not be drawn to scale; therefore, the dimensions of some features in certain drawings may be intentionally enlarged or reduced. Figure 1 illustrates the circuit diagram of a three-state content addressable memory in a first embodiment of the present invention. Figure 2 illustrates the layout pattern of a three-state content addressable memory cell in the first embodiment of the present invention. Figure 3 illustrates a side-by-side layout of two tri-state content addressable memory cells in the first embodiment of the present invention. Figures 4, 5, and 6 illustrate the side-by-side layout of two tri-state content-addressable memory cells in the second embodiment of the present invention. Figure 7 shows a cross-sectional view obtained along section line B-B' in Figure 6, which emphasizes the contact plug, the first metal layer, and the relationship between the contact plug and the first metal layer. Figure 8 is a cross-sectional view obtained from the section line A-A' in Figure 4, which emphasizes the relationship between the base, the fin structure and the dummy fin structure. Implementation

[0008] Although this document discusses specific configurations and arrangements, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0009] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include those specific features, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0010] Generally, terms can be understood, at least in part, based on their usage in context. For example, the term “one or more” (at least in part, depending on context) as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a plural combination of features, structures, or characteristics. Similarly, terms such as “a,” “an,” or “the” can again be understood to express a singular usage or to convey a plural usage, at least in part, depending on context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can conversely allow for additional factors that are not necessarily explicitly described, at least in part, depending on context.

[0011] It should be readily understood that the meanings of “on top of,” “above,” and “above” in the disclosed content of this case should be interpreted in the broadest sense, such that “on top of” not only means “directly” on something, but also includes the meaning of being on something and having intermediate features or layers between them, and that “above” or “above” not only means being on or above something, but also includes the meaning of not having intermediate features or layers (i.e., being directly on something).

[0012] Furthermore, for ease of description, as illustrated in the figures, spatial relative terms such as "below," "under," "lower," "above," and "higher" can be used to describe the relationship of one or more elements or features to another. In addition to the orientations depicted in the figures, the spatial relative terms are intended to encompass different orientations of elements in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptions used herein can be interpreted accordingly.

[0013] As used herein, the term "substrate" refers to the material on which layers of material are subsequently added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0014] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entire lower or upper layer structure, or may have a extent smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on and / or below it. A single layer may contain multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0015] In this embodiment, a ternary content addressable memory (TCAM) is disclosed, which includes two six-transistor static random access memories (6T-SRAMs) composed of six transistors and a comparator logic circuit composed of four transistors. More specifically, please refer to Figure 1, which illustrates the circuit diagram of the ternary content addressable memory in the first embodiment of the present invention. As shown in Figure 1, a ternary content addressable memory (TCAM) of the present invention is composed of two six-transistor units (six-transistor static random access memories) 6T-SRAM1 and 6T-SRAM2 and a comparator logic circuit CL. The six-transistor unit 6T-SRAM1 includes a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first pass gate transistor PG1, and a second pass gate transistor PG2. The 6T-SRAM2 six-transistor cell includes a third pull-up transistor PU3, a fourth pull-up transistor PU4, a third pull-down transistor PD3, a fourth pull-down transistor PD4, a third transmission gate transistor PG3, and a fourth transmission gate transistor PG4. The comparator logic circuit CL includes two interconnected first transistors T1 and T2, and two interconnected third transistors T3 and T4. The first pull-up transistor PU1 and the first pull-down transistor PD1 form a first inverter INV1, and the second pull-up transistor PU2 and the second pull-down transistor PD2 form a second inverter INV2. The first inverter INV1 and the second inverter INV2 constitute a latch circuit, allowing data to be latched to storage nodes N1 and N2. Similarly, the third pull-up transistor PU3 and the third pull-down transistor PD3 form a third inverter INV3, and the fourth pull-up transistor PU4 and the fourth pull-down transistor PD4 form a fourth inverter INV4. The third inverter INV3 and the fourth inverter INV4 form a latch circuit, which allows data to be latched to storage nodes N1 and N2.

[0016] Taking a 6T-SRAM1 six-transistor unit as an example, the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, the second pull-down transistor PD2, the first transmission gate transistor PG1, and the second transmission gate transistor PG2 together constitute a six-transistor static random access memory (6T-SRAM). Furthermore, the first pull-up transistor PU1 and the second pull-up transistor PU2 serve as active loads; they can also be replaced by ordinary resistors as pull-up elements, in which case it becomes a four-transistor static random access memory (4T-SRAM). In this embodiment, one source region of each of the first pull-up transistor PU1 and the second pull-up transistor PU2 is electrically connected to a voltage source Vcc (not shown), and one source region of each of the first pull-down transistor PD1 and the second pull-down transistor PD2 is electrically connected to a voltage source Vss (not shown). As for the six-transistor unit 6T-SRAM2, it has similar characteristics and connection methods to the aforementioned six-transistor unit 6T-SRAM1. Please refer to Figure 1 for details, which will not be repeated here.

[0017] Generally speaking, the first pull-up transistor PU1, the second pull-up transistor PU2, the third pull-up transistor PU3, and the fourth pull-up transistor PU4 of a 6T-SRAM memory cell are composed of P-type metal oxide semiconductor (PMOS) transistors, while the first pull-down transistor PD1, the second pull-down transistor PD2, the third pull-down transistor PD3, the fourth pull-down transistor PD4, and the first transmission gate transistor PG1, the second transmission gate transistor PG2, the third transmission gate transistor PG3, and the fourth transmission gate transistor PG4 are composed of N-type metal oxide semiconductor (NMOS) transistors.

[0018] Taking the 6T-SRAM1 six-transistor cell as an example, at storage node N1, the gates of the first pull-down transistor PD1 and the first pull-up transistor PU1 are electrically connected, as are the drains of the second pull-down transistor PD2, the second pull-up transistor PU2, and the first transmission gate transistor PG1. Similarly, at storage node N2, the gates of the second pull-down transistor PD2 and the second pull-up transistor PU2 are electrically connected, as are the drains of the first pull-down transistor PD1, the first pull-up transistor PU1, and the first transmission gate transistor PG1. The 6T-SRAM2 six-transistor cell has similar characteristics and connection methods to the 6T-SRAM1 six-transistor cell described above, which can be referred to in Figure 1 and will not be repeated here. The gates of the first transmission gate transistor PG1 and the second transmission gate transistor PG2 located in the six-transistor cell 6T-SRAM1 are coupled to the word line WL1, and the gates of the first transmission gate transistor PG1 and the second transmission gate transistor PG2 located in the six-transistor cell 6T-SRAM2 are coupled to the word line WL2. The sources of the first transmission gate transistor PG1 and the second transmission gate transistor PG2 are coupled to the corresponding bit line BLB and bit line BL, respectively.

[0019] As shown in Figure 1, in this embodiment, the gate of the second transistor T2 is connected to the storage node N2 of the 6T-SRAM, that is, the gate of the second transistor T2 is connected to the gates of the second pull-up transistor PU2 and the second pull-down transistor PD2. The second transistor T2 is connected in series with the first transistor T1, that is, the drain of the second transistor T2 is connected to the source of the first transistor T1. The drain of the first transistor T1 is connected to a voltage source (e.g., a voltage source Vss), the gate of the first transistor T1 is connected to a search line SLB, and the source of the second transistor T2 is connected to a match line ML.

[0020] On the other hand, the connection methods of the third transistor T3 and the fourth transistor T4 are similar to and symmetrical to those of the first transistor T1 and the second transistor T2, respectively. The gate of the third transistor T3 is connected to the storage node N2 of the 6T-SRAM2, meaning the gate of the third transistor T3 is connected to the gates of the fourth pull-up transistor PU4 and the fourth pull-down transistor PD4. The fourth transistor T4 is connected in series with the third transistor T3, meaning the drain of the fourth transistor T4 is connected to the source of the third transistor T3. The drain of the fourth transistor T4 is connected to a voltage source (e.g., a voltage source Vss), and the gate of the fourth transistor T4 is connected to the search line SL. The source of the third transistor T3 is connected to the matching line ML. The aforementioned search line SLB is the complementary search line bar of the search line SL mentioned here. Both are used to input complementary or different signals for comparison, which is a well-known technique in the art.

[0021] The 6T-SRAM described above can be used as a signal storage unit in a tri-state addressable memory, while the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4, which are connected to the 6T-SRAM, are used as the comparison logic circuit of the tri-state addressable memory. In other words, a tri-state addressable memory in this embodiment is composed of two 6T-SRAMs and four other transistors.

[0022] In practice, the matching line ML can be pre-charged to a high potential. Then, the search lines SL and SLB can be supplied with either a high or low potential to turn the first transistor T1 and the fourth transistor T4 on or off. This allows the signals from the search lines SL and SLB to be compared with the signals previously stored in the 6T-SRAM. For example, a high potential can be defined as signal 1, and a low potential as signal 0. Depending on the application, the signals of the search lines SL and SLB can be set to (0,1), (1,0), or (0,0). Signals (0,1) or (1,0) are compared with the signals stored in the 6T-SRAM at storage node N1. If the comparison matches, the electrical signal of the matching line ML remains high; otherwise, if the comparison does not match, the electrical signal of the matching line ML drops from high to low. Additionally, the signal (0,0) represents a "don't care" state, allowing for fuzzy comparison. The above circuitry constitutes the Tri-State Content Addressable Memory (TCAM) described in this invention. Other related technologies concerning the principles and logic comparison methods of content addressable memory are well-known in the art and will not be elaborated upon in this paragraph.

[0023] Figure 2 illustrates the layout pattern of a tri-state addressable memory cell in the first embodiment of the present invention. As shown in Figure 2, in order to form tri-state addressable memory cells in each region, multiple fin structures F, multiple gate structures G (e.g., polysilicon gates, but not limited thereto), and multiple conductive layers are formed on the substrate 10. In Figure 2, the conductive layer overlapping with the gate structure G is defined as MP, and the conductive layer not overlapping with the gate structure G is defined as MD. The conductive layers MP and MD can be made of the same material, such as metals, such as tungsten, cobalt, copper, aluminum, gold, silver, etc., but are not limited thereto. Both the conductive layers MP and MD have the function of connecting elements. Therefore, in some embodiments, the conductive layers MP and MD can be regarded as the same layer structure. Additionally, it includes a contact plug V0 for connecting the gate structure G or the conductive layer MP / MD to other signal sources, such as wires or bit lines BL / BLB, word lines WL1 / WL2, search lines SL / SLB, matching lines ML, voltage sources Vcc / Vss, etc.

[0024] In some embodiments of the present invention, the fin structure F may be replaced by a diffusion region; the fin structure F will still be used as an example for the following description. The gate structure G spans the fin structure F and is combined to form the aforementioned transistors, including a first pull-up transistor PU1, a second pull-up transistor PU2, a third pull-up transistor PU3, a fourth pull-up transistor PU4, a first pull-down transistor PD1, a second pull-down transistor PD2, a third pull-down transistor PD3, a fourth pull-down transistor PD4, a first transmission gate transistor PG1, a second transmission gate transistor PG2, a third transmission gate transistor PG3, a fourth transmission gate transistor PG4, a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. Each transistor can be electrically connected to various signal sources, such as bit lines BL / BLB, word lines WL1 / WL2, search lines SL / SLB, and matching lines ML, via subsequently formed metal wires or contact structures. For clarity of illustration, in Figure 2 and the layout diagrams of various embodiments of the present invention, the names of transistors or connected signal sources are directly marked at the corresponding positions in the layout diagrams to indicate that a specific transistor is formed at that position or that the position is connected to a specific signal source.

[0025] When two or more tri-state addressable memory cells (TCAMs) are arranged adjacent to each other, refer to Figures 2 and 3. Figure 3 illustrates a layout pattern of two tri-state addressable memory cells side by side in the first embodiment of the present invention. The left half of Figure 3 contains the same tri-state addressable memory cell TCAM as in Figure 2, while the right half contains another tri-state addressable memory cell TCAM2. The tri-state addressable memory cells TCAM and TCAM2 are mirror images of each other along the axis of symmetry I. The tri-state addressable memory cells TCAM and TCAM2 have generally symmetrical circuit patterns. For simplicity, these symmetrical components will not be described again.

[0026] As shown in Figure 3, the tri-state addressable memory cell TCAM and the tri-state addressable memory cell TCAM2 are arranged side by side, but the gate structure G at the axis of symmetry I is cut off. In this way, the tri-state addressable memory cell TCAM and the tri-state addressable memory cell TCAM2 are electrically insulated from each other, and can be regarded as two independent components. More specifically, after the gate structure G is fabricated, multiple continuous strip-shaped gate structures are formed. At this point, these continuous strip-shaped structures can be cut into multiple separate gate structures by, for example, an etching process, thus separating the tri-state addressable memory cell TCAM and the tri-state addressable memory cell TCAM2.

[0027] However, the applicant discovered that cutting multiple gate structures G at the point of overlap with the axis of symmetry I (i.e., along the Y direction) in the aforementioned gate cutting step would lead to two problems. One is that the cutting pattern extends along the longitudinal direction (Y direction) and cuts multiple gate structures G. However, since the length of the cutting pattern in the Y direction is relatively long, its width in the X direction also needs to be maintained at a certain value. Otherwise, if the aspect ratio of the cutting pattern is too high, it is easy for the cutting pattern to break during exposure, resulting in incomplete cutting of the gate structures G. The other problem is that between two adjacent TCAMs, all the gate structures G are cut along the axis of symmetry I, which can easily lead to uneven pattern density, affecting the quality of subsequent components.

[0028] To address the above two issues, in other embodiments of the present invention, an improved layout pattern and manufacturing method for a three-state addressable memory cell are provided, as detailed in Figures 4 to 8 below. The circuit diagram is the same as in the above embodiments and can be referred to Figure 1. The following description will focus on different embodiments of the present invention. For simplicity, the description will primarily focus on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the various embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between embodiments.

[0029] Figures 4, 5, and 6 illustrate a side-by-side layout of two tri-state content-addressable memory cells in the second embodiment of the present invention. As shown in Figure 4, this embodiment also includes two adjacent tri-state content-addressable memory cells TCAM and TCAM2, which are mirror-symmetrical along the axis of symmetry I. The difference from the previous embodiment is that, on the axis of symmetry I between TCAM and TCAM2, not all gate structures G are cut off at the axis of symmetry I; rather, some gate structures G are cut off at the axis of symmetry I, while others are not. More specifically, as shown in Figure 4, gate structures G1, G2, G3, and G4 can be defined among the multiple gate structures G in Figure 4. In this embodiment, gate structures G1-G4 are all gate structures G. Gate structures G1 and G4 are connected to the search line SL / SLB via contact plug V0, while gate structures G2 and G3 are not connected to other components and can be considered as dummy gate structures. In this embodiment, gate structures G1, G2, G3, and G4 partially overlap each other in the Y direction. In this embodiment, gate structures G1 and G4 do not overlap with the axis of symmetry I, while gate structures G2 and G3 are not cut off at the axis of symmetry I. Therefore, gate structures G2 and G3 overlap with the axis of symmetry I. In other words, the difference between this embodiment and the previous embodiment is that, during the gate structure cutting step, not all gate structures G overlapping with the axis of symmetry I are cut off. Instead, a portion of the gate structures G overlapping with the axis of symmetry I are cut in an interlaced manner, and the other portion of the gate structures G are not cut off at the axis of symmetry I.

[0030] Furthermore, referring to the dashed outlines of the cutting regions C1, C2, C3, and C4 in Figure 4, these regions C1-C4 represent the areas where the gate structure G is cut. In other words, the gate structure G located within the cutting regions C1-C4 will be removed. As can be seen from Figure 4, the four adjacent cutting regions C1-C4 are arranged in an alternating pattern to resemble a rhombus shape. Therefore, the cuts that sever the gate structure G will also be distributed in a similar rhombus pattern.

[0031] In this embodiment, since the cutting regions C1-C4 are arranged in a rhomboid pattern, compared to the embodiment in Figure 3 above, the aspect ratio of each cutting region C1-C4 is smaller than that of the elongated cutting region extending along the entire axis of symmetry I. This allows the width of each cutting region C1-C4 to be reduced accordingly, which better avoids incomplete exposure due to an excessively large aspect ratio, thus preventing the gate structure G from being cut accurately. Furthermore, since the cutting regions C1-C4 are distributed more uniformly, the density uniformity of the overall semiconductor layout pattern can also be improved.

[0032] Next, please refer to Figures 5 and 6. After forming the aforementioned fin structure F, gate structure G, conductive layer MP, conductive layer MD, and contact plug V0, the first metal layer M1, contact plug V1, and second metal layer M2 are subsequently formed on top of these structures. The first metal layer M1 and the second metal layer M2 can connect different components on the same layer (in the XY plane), while the contact plugs V0 and V1 are mainly used to connect components between different layers in the vertical direction (perpendicular to the XY plane). To clarify the diagrams, Figures 5 and 6 indicate the signal sources connected to the metal wires next to the first metal layer M1 and the second metal layer M2, such as bit lines BL / BLB, word lines WL1 / WL2, search lines SL / SLB, matching lines ML, and voltage sources Vcc / Vss.

[0033] The materials of the first metal layer M1, the second metal layer M2, the contact plug V0, and the contact plug V1 are, for example, highly conductive metals such as tungsten, cobalt, copper, aluminum, gold, and silver, but are not limited thereto. To simplify the pattern design of the photomask, as shown in Figures 5-6, the first metal layer M1 formed in Figure 5 contains multiple metal patterns, most of which extend along the Y direction, while the second metal layer M2 in Figure 6 contains multiple metal patterns, most of which extend along the X direction. Furthermore, it is understood that although pattern layers such as the first metal layer M1 and the second metal layer M2 are shown in this embodiment, in some embodiments the semiconductor layout pattern may also include more stacked metal layers and metal plugs, such as the third metal layer M3 (not shown), the fourth metal layer M4 (not shown), the contact plug V2 (not shown), and the contact plug V3 (not shown), which are also within the scope of this invention.

[0034] It is worth noting that, referring to Figure 5, the first metal layer M1 contains multiple metal patterns extending along the Y direction. The metal pattern overlapping the axis of symmetry I is defined as the first metal conductor M1-1, and the metal patterns adjacent to the first metal conductor M1-1 on the left and right are defined as the second metal conductor M1-2 and the third metal conductor M1-3, respectively. In this embodiment, the first metal conductor M1-1 is not connected to the lower contact plug V0, but the second metal conductor M1-2 and the third metal conductor M1-3 are both connected to the lower contact plug V0. Thus, when the circuit is on, the low-potential first metal conductor M1-1 is located between the two high-potential second metal conductors M1-2 and the third metal conductor M1-3. The applicant has found that this configuration easily produces a coupling effect. Specifically, the high-potential metal conductors generate an electric field and affect the low-potential metal conductors, causing signal interference problems such as noise.

[0035] Another feature of the present invention is that, in order to solve the above-mentioned coupling effect problem, in this embodiment, the first metal wire M1-1 is connected to the second metal layer M2 through the upper contact plug V1, and then connected to the voltage source Vss, while the first metal wire M1-1 is not connected to the contact plug V0. Referring to Figures 6 and 7, Figure 7 shows a cross-sectional view obtained along section line B-B' in Figure 6. To clearly illustrate the features of this embodiment, Figure 7 mainly shows the relationship between the contact plug V0, the first metal layer M1, and the first metal layer M2; other components are omitted. Furthermore, in Figure 7, some contact plugs V0, indicated by dashed lines, are located below the first metal layer M1. This indicates that although these contact plugs V0 do not pass through section line B-B', they are located outside section line B-B' and are electrically connected to the first metal layer M1. As can be seen from Figure 7, the first metal wire M1-1 is located between the second metal wire M1-2 and the third metal wire M1-3. The second metal wire M1-2 and the third metal wire M1-3 are both connected to the lower contact plug V0 to the search line SLB. The second metal wire M1-1 does not contain a contact plug V0 below it, but is electrically connected to the second metal layer M2 through the upper contact plug V1, and is connected to the voltage source Vss.

[0036] In summary, in this embodiment, one method to solve the coupling problem is to ground the first metal wire M1-1 or connect it to a fixed voltage source (such as Vss). However, the second metal wires M1-2 and the third metal wires M1-3 on both sides of the first metal wire M1-1 are already connected to the contact plug V0. Therefore, connecting the first metal wire M1-1 to the voltage source Vss from the lower contact plug V0 would occupy additional space. Therefore, in this embodiment, electrically connecting the first metal wire M1-1 to the voltage source Vss via the upper contact plug V1 can effectively solve the above-mentioned coupling effect without occupying additional space.

[0037] Furthermore, another feature of the present invention is illustrated in Figure 8. Figure 8 is a cross-sectional view obtained along section line A-A' in Figure 4. To clearly illustrate the features of this embodiment, Figure 8 focuses primarily on the relationship between the substrate, the fin structure, and the dummy fin structure; other components are omitted and not shown. As shown in Figure 8, when forming the fin structure, to avoid uneven pattern density in the semiconductor layout—for example, a higher pattern density in areas where fin structures are formed and a lower pattern density in areas where no fin structures are formed—in some embodiments of the present invention, multiple dummy fin structures DF can be formed simultaneously on the substrate 10 while forming the fin structure F on the substrate 10. From the cross-sectional view, the width and height of the dummy fin structure DF are preferably smaller than the width and height of the fin structure F. In the present invention, the purpose of forming the dummy fin structure DF is to make the overall pattern more uniform and avoid the aforementioned problem of uneven pattern density. In subsequent steps, the dummy fin structure DF may be retained on the substrate 10, meaning that the gate structure G spans not only the fin structure F but also the dummy fin structure DF. Alternatively, in other embodiments, the dummy fin structure DF may be removed, which is also within the scope of this invention.

[0038] Based on the above description and figures, the present invention provides a semiconductor layout pattern comprising a substrate 10, on which a plurality of ternary content addressable memory (TCAM) cells are included, wherein at least two TCAM cells (TCAM1, TCAM2) are mirror-symmetrically arranged along a symmetry axis I, wherein each TCAM cell includes a plurality of transistors, and the substrate 10 includes a plurality of fin structures F arranged in a Y direction and a plurality of gate structures G arranged in an X direction, wherein some of the gate structures G span some of the fin structures F and constitute the plurality of transistors of the TCAM cell, wherein among the plurality of gate structures G, a first gate structure G1 is connected to a search line SLB and a second gate structure G2 is not connected to the search line SLB, wherein the first gate structure G1 and the second gate structure G2 are arranged in parallel, and the first gate structure G1 does not overlap with the symmetry axis I, while the second gate structure G2 overlaps with the symmetry axis I.

[0039] In some embodiments of the present invention, an extension direction of the symmetry axis I is parallel to an extension direction of each fin structure (both extending along the Y direction), and the extension direction of the symmetry axis I is perpendicular to an extension direction of each gate structure G (the gate structure G extends along the X direction).

[0040] In some embodiments of the present invention, each TCAM unit includes multiple transistors, including two six-transistor layout patterns (6T-SRAM1 and 6T-SRAM2) and a comparison logic circuit CL. Each six-transistor layout pattern includes: a first pull-up transistor (PU1) and a first pull-down transistor (PD1) forming a first inverter (INV1); a second pull-up transistor (PU2) and a second pull-down transistor (PD2) forming a second inverter (INV2); a first transmission gate transistor (PG1) and a second transmission gate transistor (PG2) connecting the first inverter and the second inverter; the comparison logic circuit CL includes a first transistor T1 and a second transistor T2 connected in series, and a third transistor T3 and a fourth transistor T4 connected in series, wherein the gate structure of the second transistor T2 is connected to the gate structure of the second pull-down transistor (PD2).

[0041] In some embodiments of the present invention, the first gate structure G1 spans a portion of the fin structure F and forms the first transistor T1, and the second gate structure G2 does not span the fin structure.

[0042] In some embodiments of the present invention, the plurality of gate structures G further include a third gate structure (such as gate structure G5 in Figure 4), the third gate structure G5 spans the fin structure F and constitutes the second transistor T2, wherein the third gate structure G5 and the second gate structure G2 are aligned with each other in the X direction.

[0043] In some embodiments of the present invention, the layout pattern includes a first metal layer (M1) containing a plurality of metal wires, and a first metal wire M1-1 contained in the first metal layer (M1) overlaps with the axis of symmetry, and a second metal wire M1-2 contained in the first metal layer (M1) is electrically connected to a first gate structure G1 via a zero-layer contact plug (V0), wherein, from a cross-sectional view, the zero-layer contact plug (V0) is located below the second metal wire M1-2.

[0044] In some embodiments of the present invention, the first metal wire M1-1 is electrically connected to a second metal layer (M2) via a first contact plug (V1) and connected to a voltage source (Vss).

[0045] In some embodiments of the present invention, as seen from a cross-sectional view, the first layer of contact plug (V1) is located above the first metal wire M1-1, and there is no contact plug V0 directly below the first metal wire M1-1 (as shown in Figure 7).

[0046] In some embodiments of the present invention, the first metal wire M1-1 and the second metal wire M1-2 are parallel to each other, the first metal wire M1-1 and the second metal wire M1-2 are adjacent to each other, and an extension direction of the first metal wire M1-1 is parallel to an extension direction of the axis of symmetry I.

[0047] In some embodiments of the present invention, a plurality of dummy fin structures DF are located on the substrate 10, and some of the dummy fin structures DF are located between the fin structures F, wherein the width and height of the dummy fin structures DF are smaller than the width and height of the fin structures F.

[0048] The present invention also provides a method for fabricating a semiconductor layout pattern, comprising providing a substrate 10, forming a plurality of ternary content addressable memory (TCAM) cells on the substrate 10, wherein the layout of at least two TCAM cells is mirror-symmetrical to each other along a symmetry axis I, wherein each TCAM cell includes a plurality of transistors, the substrate 10 includes a plurality of fin structures F arranged in a Y direction and a plurality of gate structures G arranged in an X direction, wherein some of the gate structures G span some of the fin structures F and constitute the plurality of transistors of the TCAM cell, wherein the plurality of gate structures G includes a first gate structure G1 connected to a search line SLB and a second gate structure G2 not connected to the search line SLB, wherein the first gate structure G1 and the second gate structure G2 are arranged in parallel, and the first gate structure G1 does not overlap with the symmetry axis I, while the second gate structure G2 overlaps with the symmetry axis I.

[0049] In some embodiments of the present invention, an extension direction of the symmetry axis I is parallel to an extension direction of each fin structure (both extending along the Y direction), and the extension direction of the symmetry axis I is perpendicular to an extension direction of each gate structure G (the gate structure G extends along the X direction).

[0050] In some embodiments of the present invention, each TCAM unit includes multiple transistors, including two six-transistor layout patterns (6T-SRAM1 and 6T-SRAM2) and a comparison logic circuit CL. Each six-transistor layout pattern includes: a first pull-up transistor (PU1) and a first pull-down transistor (PD1) forming a first inverter (INV1); a second pull-up transistor (PU2) and a second pull-down transistor (PD2) forming a second inverter (INV2); a first transmission gate transistor (PG1) and a second transmission gate transistor (PG2) connecting the first inverter and the second inverter; the comparison logic circuit CL includes a first transistor T1 and a second transistor T2 connected in series, and a third transistor T3 and a fourth transistor T4 connected in series, wherein the gate structure of the second transistor T2 is connected to the gate structure of the second pull-down transistor (PD2).

[0051] In some embodiments of the present invention, the first gate structure G1 spans a portion of the fin structure F and forms the first transistor T1, and the second gate structure G2 does not span the fin structure.

[0052] In some embodiments of the present invention, the plurality of gate structures G further include a third gate structure (such as gate structure G5 in Figure 4), the third gate structure G5 spans the fin structure F and constitutes the second transistor T2, wherein the third gate structure G5 and the second gate structure G2 are aligned with each other in the X direction.

[0053] In some embodiments of the present invention, a first metal layer (M1) is formed that includes a plurality of metal wires, and a first metal wire M1-1 included in the first metal layer (M1) overlaps with the axis of symmetry, and a second metal wire M1-2 included in the first metal layer (M1) is electrically connected to a first gate structure G1 via a zero-layer contact plug (V0), wherein, from a cross-sectional view, the zero-layer contact plug (V0) is located below the second metal wire M1-2.

[0054] In some embodiments of the present invention, the first metal wire M1-1 is electrically connected to a second metal layer (M2) via a first contact plug (V1) and connected to a voltage source (Vss).

[0055] In some embodiments of the present invention, as seen from a cross-sectional view, the first layer of contact plug (V1) is located above the first metal wire M1-1, and there is no contact plug V0 directly below the first metal wire M1-1 (as shown in Figure 7).

[0056] In some embodiments of the present invention, the first metal wire M1-1 and the second metal wire M1-2 are parallel to each other, the first metal wire M1-1 and the second metal wire M1-2 are adjacent to each other, and an extension direction of the first metal wire M1-1 is parallel to an extension direction of the axis of symmetry I.

[0057] In some embodiments of the present invention, a plurality of dummy fin structures DF are formed on the substrate 10, and some of the dummy fin structures DF are located between the fin structures F, wherein the width and height of the dummy fin structures DF are smaller than the width and height of the fin structures F.

[0058] In summary, the key feature of this invention is that when two Tri-State Addressable Memory Cells (TCAMs) are arranged on a substrate, if the gate structure is directly divided with a continuous long strip cutting pattern at the junction of the two TCAMs, uneven pattern density is likely to occur. To solve this problem, in this invention, the cutting area at the junction of the two TCAMs is divided into multiple segments, arranged in an alternating manner in, for example, a rhomboid shape. This results in a more uniform distribution of the gate structure after cutting, thus improving the overall quality of the semiconductor device. Furthermore, this invention connects the first metal layer, which is prone to coupling effects, to the voltage source via upper contact plugs to avoid coupling effects. Additionally, in some embodiments of this invention, besides forming a fin structure, multiple dummy fin structures are also formed and distributed beside the fin structure, thereby improving the pattern uniformity of the overall layout. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0059] 6T-SRAM1: Six-transistor static random access memory

[0060] 6T-SRAM2: Six-transistor static random access memory

[0061] 10: Base

[0062] BL: Bitline

[0063] BLB: Bitline

[0064] C1, C2, C3, C4: Cutting areas

[0065] CL: Comparison Logic Circuit

[0066] DF: Virtual fin structure

[0067] F: Fin-like structure

[0068] G: Gate structure

[0069] G1: Gate structure (first gate structure)

[0070] G2: Gate structure (second gate structure)

[0071] G3: Gate structure

[0072] G4: Gate structure

[0073] G5: Gate structure (third gate structure)

[0074] I: Axis of symmetry

[0075] INV1: First Inverter

[0076] INV2: Second Inverter

[0077] INV3: Third Inverter

[0078] INV4: Fourth Inverter

[0079] M1: First metal layer

[0080] M1-1: First metallic wire

[0081] M1-2: Second metal wire

[0082] M1-3: Third metal wire

[0083] M2: Second metal layer

[0084] MD: Conductive layer

[0085] MP: Conductive layer

[0086] ML: Matching line

[0087] N1: Storage Node

[0088] N2: Storage Node

[0089] PU1: First pull-up transistor

[0090] PU2: Second pull-up transistor

[0091] PU3: Third pull-up transistor

[0092] PU4: Fourth pull-up transistor

[0093] PD1: First pull-down transistor

[0094] PD2: Second pull-down transistor

[0095] PD3: Third pull-down transistor

[0096] PD4: Fourth pull-down transistor

[0097] PG1: First Transmission Thyristor

[0098] PG2: Second Transmission Thyristor

[0099] PG3: Third Transmission Thyristor

[0100] PG4: Fourth Transmission Thyristor

[0101] SL: Search Line

[0102] SLB: Search Line

[0103] T1: First transistor

[0104] T2: Second transistor

[0105] T3: Third transistor

[0106] T4: Fourth transistor

[0107] TCAM: Tri-state Addressable Memory

[0108] TCAM2: Tri-state Addressable Memory

[0109] V0: Contact plug

[0110] V1: Contact plug

[0111] Vcc: Voltage source

[0112] Vss: Voltage source

[0113] WL1: Character Line

[0114] WL2: Character Line

Claims

1. A semiconductor layout pattern comprising: a substrate having a plurality of ternary content addressable memory (TCAM) cells thereon, wherein at least two TCAM cells are mirror-symmetrical about each other along an axis of symmetry; wherein each TCAM cell includes a plurality of transistors, the substrate having a plurality of fin structures arranged in a Y direction and a plurality of gate structures arranged in an X direction, wherein some of the gate structures span the fin structures and constitute the plurality of transistors of the TCAM cell; and wherein the plurality of gate structures includes a first gate structure connected to a search line and a second gate structure not connected to the search line, wherein the first gate structure and the second gate structure are arranged parallel to each other, and the first gate structure does not overlap with the axis of symmetry, while the second gate structure overlaps with the axis of symmetry.

2. The semiconductor layout pattern as described in claim 1, wherein an extension direction of the axis of symmetry is parallel to an extension direction of each of the fin structures, and the extension direction of the axis of symmetry is perpendicular to an extension direction of each of the gate structures.

3. The semiconductor layout pattern as described in claim 1, wherein each TCAM unit includes two six-transistor layout patterns and a comparison logic circuit, wherein each six-transistor layout pattern includes: a first pull-up transistor (PU1) and a first pull-down transistor (PD1) forming a first inverter (INV1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2) forming a second inverter (INV2), and a first transmission gate transistor (PG1) and a second transmission gate transistor (PG2) connecting the first inverter and the second inverter; the comparison logic circuit includes a first transistor T1 and a second transistor T2 connected in series, and a third transistor T3 and a fourth transistor T4 connected in series, wherein the gate structure included in the second transistor T2 is connected to the gate structure of the second pull-down transistor (PD2).

4. The semiconductor layout pattern as described in claim 3, wherein the first gate structure spans a portion of the fin structure and constitutes the first transistor T1, and the second gate structure does not span the fin structure.

5. The semiconductor layout pattern as described in claim 3, wherein the plurality of gate structures further includes a third gate structure that spans the fin structure and forms the second transistor T2, wherein the third gate structure and the second gate structure are aligned with each other in the X direction.

6. The semiconductor layout pattern as described in claim 1, wherein the layout pattern includes a first metal layer (M1) including a plurality of metal wires, and a first metal wire included in the first metal layer (M1) overlaps with the axis of symmetry, and a second metal wire included in the first metal layer (M1) is electrically connected to the first gate structure via a zero-layer contact plug (V0), wherein, from a cross-sectional view, the zero-layer contact plug (V0) is located below the second metal wire.

7. The semiconductor layout pattern as described in claim 6, wherein the first metal wire is electrically connected to a second metal layer (M2) via a first contact plug (V1) and connected to a voltage source (Vss).

8. The semiconductor layout pattern as described in claim 7, wherein, in a cross-sectional view, the first layer contact plug (V1) is located above the first metal conductor, and there is no contact plug directly below the first metal conductor.

9. The semiconductor layout pattern as described in claim 6, wherein the first metal wire and the second metal wire are parallel to each other, the first metal wire and the second metal wire are adjacent to each other, and an extension direction of the first metal wire is parallel to an extension direction of the axis of symmetry.

10. The semiconductor layout pattern as described in claim 1, further comprising a plurality of dummy fin structures located on the substrate, and some of the dummy fin structures located between the fin structures, wherein the width and height of the dummy fin structures are smaller than the width and height of the fin structures.

11. A method for fabricating a semiconductor layout pattern, comprising: providing a substrate; forming a plurality of ternary content addressable memory (TCAM) cells on the substrate, wherein the layout of at least two TCAM cells is mirror-symmetrical about each other along an axis of symmetry; wherein each TCAM cell includes a plurality of transistors, the substrate includes a plurality of fin structures arranged in a Y direction and a plurality of gate structures arranged in an X direction, wherein some of the gate structures span the fin structures and constitute the plurality of transistors of the TCAM cell; and wherein the plurality of gate structures includes a first gate structure connected to a search line and a second gate structure not connected to the search line, wherein the first gate structure and the second gate structure are arranged parallel to each other, and the first gate structure does not overlap with the axis of symmetry, while the second gate structure overlaps with the axis of symmetry.

12. The method for fabricating a semiconductor layout pattern as described in claim 11, wherein an extension direction of the axis of symmetry is parallel to an extension direction of each of the fin structures, and the extension direction of the axis of symmetry is perpendicular to an extension direction of each of the gate structures.

13. A method for fabricating a semiconductor layout pattern as described in claim 11, wherein each TCAM unit includes two six-transistor layout patterns and a comparison logic circuit, wherein each six-transistor layout pattern includes: a first pull-up transistor (PU1) and a first pull-down transistor (PD1) forming a first inverter (INV1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2) forming a second inverter (INV2), and a first transmission gate transistor (PG1) and a second transmission gate transistor (PG2) connecting the first inverter and the second inverter; the comparison logic circuit includes a first transistor T1 and a second transistor T2 connected in series, and a third transistor T3 and a fourth transistor T4 connected in series, wherein the gate structure included in the second transistor T2 is connected to the gate structure of the second pull-down transistor (PD2).

14. The method for fabricating a semiconductor layout pattern as described in claim 13, wherein the first gate structure spans a portion of the fin structure and constitutes the first transistor T1, and the second gate structure does not span the fin structure.

15. The method for fabricating a semiconductor layout pattern as described in claim 13, wherein the plurality of gate structures further includes a third gate structure that spans the fin structure and constitutes the second transistor T2, wherein the third gate structure and the second gate structure are aligned with each other in the X direction.

16. The method for fabricating a semiconductor layout pattern as described in claim 11, further comprising forming a first metal layer (M1) including a plurality of metal wires, wherein a first metal wire included in the first metal layer (M1) overlaps with the axis of symmetry, and a second metal wire included in the first metal layer (M1) is electrically connected to the first gate structure via a zero-layer contact plug (V0), wherein, in a cross-sectional view, the zero-layer contact plug (V0) is located below the second metal wire.

17. The method for fabricating a semiconductor layout pattern as described in claim 16, wherein the first metal wire is electrically connected to a second metal layer (M2) via a first contact plug (V1) and connected to a voltage source (Vss).

18. A method for fabricating a semiconductor layout pattern as described in claim 17, wherein, in a cross-sectional view, the first layer of contact plug (V1) is located above the first metal wire, and there is no contact plug directly below the first metal wire.

19. A method for fabricating a semiconductor layout pattern as described in claim 16, wherein the first metal wire and the second metal wire are parallel to each other, the first metal wire and the second metal wire are adjacent to each other, and an extension direction of the first metal wire is parallel to an extension direction of the axis of symmetry.

20. The method for fabricating a semiconductor layout pattern as described in claim 11, further comprising forming a plurality of dummy fin structures on the substrate, and some of the dummy fin structures being located between the fin structures, wherein the width and height of the dummy fin structures are smaller than the width and height of the fin structures.

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