Multi-chip module with synchronous clocking paths

Abstract

A multi-chip module includes an interposer including first and second interposer layers each including a first plurality of contacts and a second plurality of contacts. An embedded die includes a first phase-locked loop (PLL) circuit and arranged in the interposer. A first die includes a first die layer with a third plurality of contacts connected to the first plurality of contacts of the second interposer layer and a second die layer including at least one of a first clock buffer and a first circuit. A second die includes a first die layer with a fourth plurality of contacts connected to the second plurality of contacts of the second interposer layer and a second die layer including at least one of a second clock buffer and a second circuit. A reference clock is connected to the first PLL circuit through the first interposer layer and the second interposer layer.

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