Wafer stack structure and fabricating method of the same

Abstract

and increasing sequentially in Arabic numerals. All of the Nth device wafers are stacked from the bottom to the top to form the wafer stack structure, with the wafer of a larger N positioned below the wafer of a smaller N. Each Nth device wafer includes an Nth front surface and an Nth back surface. An Nth metal interconnection of the Nth device wafer is embedded within an Nth dielectric layer of the Nth device wafer, and the Nth metal interconnection and the Nth dielectric layer cover and contact the Nth front surface of the Nth device wafer. When N =

Description

Technical Field

[0001] The present invention relates to a wafer stacking structure and a manufacturing method thereof, and in particular to a wafer stacking structure using silicon as a carrier wafer and a manufacturing method thereof. Prior Art

[0002] Wafer stacking is a key packaging technology in the semiconductor industry. By vertically stacking multiple wafers or chips, it achieves high-density integration and reduces package size. As chip sizes continue to shrink, traditional planar packaging techniques are unable to meet the demands for high-performance computing and high-capacity storage. Therefore, wafer stacking has become a key approach to address these challenges. By stacking chips with different functions and utilizing vertical interconnects, this packaging method can significantly increase processing power and storage capacity while reducing space requirements. It is particularly suitable for applications such as high-performance computing, memory, mobile phones, and high-frequency communications. For example, in 3D IC packaging, 3D NAND, and high-bandwidth memory (HBM), wafer stacking can significantly improve integration and performance, enabling storage devices and processors to achieve more functions within the same space. Furthermore, with the continuous advancement of packaging technology, controlling power consumption and heat dissipation has become a new challenge. The industry has proposed various solutions to these issues. Overall, wafer stacking not only meets the current demand for miniaturization and high performance, but also opens up new possibilities for the development of future semiconductor products. Summary of the Invention

[0003] In view of this, the present invention provides a wafer stacking structure and a manufacturing process thereof, which can reduce the package volume and increase the yield.

[0004] According to one embodiment of the present invention, a wafer stack structure includes a plurality of device wafers, each of the aforementioned device wafers being defined as an Nth device wafer, where N=1, 2...M, M≥3, and N is a positive integer starting from 1 and increasing in Arabic numeral order. All Nth device wafers are stacked from bottom to top to form a wafer stack structure, with the Nth device wafer with a larger N being below the Nth device wafer with a smaller N. When N=M, the Mth device wafer is the bottommost wafer in the wafer stack structure, and when N=1, the 1st device wafer is the topmost wafer in the wafer stack structure. The Nth device wafer includes an Nth front side and an Nth back side, an Nth metal connection is embedded in an Nth dielectric layer, and the Nth metal connection and the Nth dielectric layer cover and contact the Nth front side of the Nth device wafer, wherein when N=1, 2. When M-1, the edges of all N-th device wafers are cut flush with each other to form a plane, and the edge of the M-th dielectric layer of the M-th device wafer protrudes from the plane.

[0005] According to another embodiment of the present invention, a process for manufacturing a wafer stack structure includes providing a silicon carrier wafer having a top surface and a bottom surface, and providing a plurality of device wafers, each of the aforementioned device wafers being defined as an Nth device wafer, where N=1, 2...M, M≥3, and N is a positive integer starting from 1 and increasing in Arabic numeral order, wherein the Nth device wafer includes an Nth front surface and an Nth back surface, an Nth metal connection is embedded in an Nth dielectric layer, and the Nth metal connection and the Nth dielectric layer cover and contact the Nth front surface of the Nth device wafer, a plurality of Nth silicon vias are embedded from the Nth front surface of the Nth device wafer into the Nth device wafer, then, forming a first silicon oxide layer covering and contacting the top surface of the silicon carrier wafer, and when N=1, forming a second silicon oxide layer covering and contacting the first metal connection and the first dielectric layer on the first device wafer, and then After forming the first silicon oxide layer and the second silicon oxide layer, when N=1, a first bonding process is performed to bond the second silicon oxide layer on the first device wafer and the first silicon oxide layer on the silicon carrier wafer. When N=2...M, a second bonding process is repeated until the Mth device wafer is bonded. The second bonding process includes bonding the Nth metal connection and the Nth dielectric layer on the Nth device wafer to an N-1th device wafer. After the second bonding process, the bottom surface of the silicon carrier wafer is thinned and the edge of the silicon carrier wafer is trimmed. Finally, the thinned silicon carrier wafer is immersed in an etching solution to completely remove the silicon carrier wafer.

[0006] According to another embodiment of the present invention, a process for forming a wafer stack structure includes forming a wafer stack structure, the wafer stack structure including a plurality of device wafers, each of the device wafers being defined as an Nth device wafer, where N=1, 2...M, M≥3, and N is a positive integer starting from 1 and increasing in Arabic numeral order, all Nth device wafers being stacked from bottom to top to form a wafer stack structure, with the Nth device wafer having a larger N being below the Nth device wafer having a smaller N. When N=M, the Mth device wafer is the bottommost wafer in the wafer stack structure, and when N=1, the 1st device wafer is the topmost wafer in the wafer stack structure. The Nth device wafer includes an Nth front side and an Nth back side, an Nth metal connection is embedded in an Nth dielectric layer, and the Nth metal connection and the Nth dielectric layer cover and contact the Nth front side of the Nth device wafer, wherein when N=1, 2. When M-1, the edges of all N-th device wafers are cut flush with each other to form a plane, and the edge of the M-th dielectric layer of the M-th device wafer protrudes from the plane.

[0007] To make the above-mentioned objectives, features, and advantages of the present invention more readily apparent, preferred embodiments are described below in detail with reference to the accompanying drawings. However, the following preferred embodiments and drawings are provided for reference and illustration only and are not intended to limit the present invention. Simple diagram description

[0008] FIG1 to FIG9 illustrate a process of manufacturing a wafer stacking structure according to a first embodiment of the present invention. FIG. 10 to FIG. 13 illustrate a process of manufacturing a wafer stacking structure according to a second embodiment of the present invention. Implementation Method

[0009] FIG1 to FIG9 illustrate a process of manufacturing a wafer stacking structure according to a first embodiment of the present invention.

[0010] As shown in FIG. 1 , a silicon carrier wafer 1 is provided. The silicon carrier wafer 1 includes a top surface 1a and a bottom surface 1b, with the top surface 1a and the bottom surface 1b facing each other. The material of the silicon carrier wafer 1 includes single crystal silicon, polycrystalline silicon, amorphous silicon, or a silicon-on-insulator wafer. The material of the silicon carrier wafer 1 is opaque, and the Young's modulus of the silicon carrier wafer 1 is greater than that of glass. According to one embodiment of the present invention, the Young's modulus of the silicon carrier wafer 1 is between 130 and 190 GPa, but is not limited thereto.

[0011] In addition, a plurality of device wafers are provided, each device wafer being defined as an Nth device wafer 100. The material of the Nth device wafer 100 includes a semiconductor material or an insulating material. The semiconductor material includes, but is not limited to, silicon, germanium, gallium arsenide, silicon germanium, indium phosphide, gallium nitride, or silicon carbide. The insulating material includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or tetraethoxysilane. In addition, N=1. 2...M, M≥3. According to a preferred embodiment of the present invention, M≥6, and N is a positive integer starting from 1 and increasing in order according to Arabic numerals, wherein the Nth device wafer 100 includes an Nth front side 100a and an Nth back side 100b, the Nth front side 100a and the Nth back side 100b facing each other, an Nth metal connection 101 is embedded in an Nth dielectric layer 102, and the Nth metal connection 101 and the Nth dielectric layer 102 cover and contact the Nth front side 100a of the Nth device wafer 100, a plurality of Nth through silicon vias 103 are embedded from the Nth front side 100a of the Nth device wafer 100 into the Nth device wafer 100, and the Nth metal connection 101 is fabricated by etching the Nth dielectric layer 102 to form a groove, which is then filled with metal. The Nth through-silicon vias 103 are fabricated by etching the Nth front surface 100a of the Nth device wafer 100 to form recesses, which are then filled with metal. The metal used for the Nth through-silicon vias 103 and the Nth metal connection 101 includes copper, aluminum, or other conductive materials. The Nth dielectric layer 102 is made of silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane, or a low-k material. Components such as transistors, capacitors, inductors, or dynamic random access memory (DRAM) may be disposed on the Nth front surface 100a of the Nth device wafer 100. In one embodiment, the Nth device wafer 100 includes a plurality of DRAM chips or a plurality of logic chips.

[0012] As shown in FIG. 2 , when N=1, the Nth device wafer becomes the first device wafer 10 in FIG. The first device wafer 10 includes a first front side 10 a and a first back side 10 b . A first metal connection 11 is embedded in a first dielectric layer 12 , and the first metal connection 11 and the first dielectric layer 12 cover and contact the first front side 10 a of the first device wafer 10 . A plurality of first through-silicon vias 13 are embedded from the first front side 10 a of the first device wafer 10 into the first device wafer 10 .

[0013] Continuing with Figure 2, a first silicon oxide layer OX1 is formed to cover and contact the top surface 1a of the silicon carrier wafer 1. The first silicon oxide layer OX1 can be formed using either a heated oxidation process or a deposition process. If the heated oxidation process is used, the first silicon oxide layer OX1 will completely encapsulate the entire silicon carrier wafer 1. Furthermore, a second silicon oxide layer OX2 is formed to cover and contact the first metal connection 11 and the first dielectric layer 12 on the first device wafer 10. The second silicon oxide layer OX2 can be formed using either a deposition process or a heated oxidation process. According to one embodiment, the thickness of the first silicon oxide layer OX1 is between 10 and 19,000 angstroms, and the thickness of the second silicon oxide layer OX2 is between 10 and 19,000 angstroms. Both the first silicon oxide layer OX1 and the second silicon oxide layer OX2 comprise silicon dioxide.

[0014] As shown in FIG3 , a first bonding process B1 is performed to bond the second silicon oxide layer OX2 on the first device wafer 10 to the first silicon oxide layer OX1 on the silicon carrier wafer 1 . The first bonding process B1 utilizes silicon dioxide wafer bonding. At this point, the front surface 10 a of the first device wafer 10 faces the top surface 1 a of the silicon carrier wafer 1 .

[0015] As shown in FIG4 , after trimming the edge of the first device wafer 10 , the first back side 10 b of the first device wafer 10 is thinned to expose each first TSV 13 on the first device wafer 10 . After trimming, the diameter of the first device wafer 10 is reduced, and the thickness of the first device wafer 10 is reduced. The first device wafer 10 can be thinned using chemical mechanical polishing (CMP), and trimmed using edge grinding. In the first embodiment, both thinning and trimming can be performed using CMP. A plurality of first conductive lines 14 and a first insulating layer 15 are then formed covering the first back side 10 b of the first device wafer 10 , with each first conductive line 14 contacting each first TSV 13 on the first device wafer 10 . The first conductive line 14 includes copper, aluminum, or other conductive materials. The first insulating layer 15 includes silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane, or a low-k material. The first conductive line 14 includes a single-layer conductive pad. Depending on different needs, the first conductive line 14 can also include multiple conductive pads and conductive plugs stacked together.

[0016] As shown in Figures 5 to 7, when N = 2…M, the value of N is increased in numerical order, and the second bonding process B2 is repeated until the Mth device wafer is bonded. For example, if M = 4, the second device wafer, the third device wafer, and the fourth device wafer are stacked on the first device wafer from bottom to top.

[0017] Specifically, when N=2...M-1, the second bonding process B2 includes bonding an N-th metal connection and an N-th dielectric layer on an N-th device wafer to an N-1-th device wafer. The second bonding process B2 uses a hybrid bonding process. However, before bonding the N-th metal connection and the N-th dielectric layer on the N-th device wafer to the N-1-th device wafer, the edges of the N-1-th device wafer and the N-1-th dielectric layer are trimmed. Then, the N-1-th backside of the N-1-th device wafer is thinned to expose each N-1-th silicon via on the N-1-th device wafer. Then, a plurality of N-1-th conductive lines and an N-1-th insulating layer are formed to cover the N-1-th backside of the N-1-th device wafer, wherein each N-1-th conductive line contacts each N-1-th silicon via on the N-1-th device wafer, and the N-th metal connection and the N-1-th dielectric layer on the N-th device wafer are bonded to the N-1-th conductive line and the N-1-th insulating layer, respectively. In this embodiment, the Nth conductive line includes copper, aluminum, or other conductive materials, and the Nth insulating layer includes silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane, or a low dielectric constant material.

[0018] Specifically, as shown in FIG. 5 , when N=2, the Nth device wafer is the second device wafer 20 . The second device wafer 20 includes a second front side 20 a and a second back side 20 b . In the second bonding process B2 , the second metal wires 21 on the second device wafer 20 are bonded to the first conductive wires 14 on the first device wafer 10 . Each second metal wire 21 is in contact with its corresponding first conductive wire 14 , and the second dielectric layer 22 on the second device wafer 20 is bonded to the first insulating layer 15 on the first device wafer 10 . As shown in FIG. 6 , after the edges of the second device wafer 20 and the second dielectric layer 22 are trimmed, the second backside 20 b of the second device wafer 20 is thinned to expose the second TSVs 23 on the second device wafer 20. A plurality of second conductive lines 24 and a second insulating layer 25 are then formed to cover the second backside 20 b of the second device wafer 20. Each second conductive line 24 contacts a second TSV 23 on the second device wafer 20. Furthermore, when trimming the edges of the second device wafer 20 and the second dielectric layer 22, they are aligned with the trimmed edges of the first device wafer 10 and the first dielectric layer 12. Therefore, the trimmed edges of the second device wafer 20, the second dielectric layer 22, the first device wafer 10, and the first dielectric layer 12 form a plane P. As shown in FIG. 7 , the Nth device wafer is stacked in the same manner as the second device wafer 20 until N=M-1, at which point the edges of the first device wafer 10 to the M-1th device wafer and the edges of the first dielectric layer 12 to the M-1th dielectric layer are all aligned with plane P. Next, when N=M, the Mth device wafer 200 is stacked. The Mth device wafer 200 includes an Mth front side 200a and an Mth back side 200b. It is noteworthy that after bonding the Mth metal connection 201 and the Mth dielectric layer 202 on the Mth device wafer 200 to the M-1th device wafer, the edges of the Mth device wafer 200 and the Mth dielectric layer 202 are not trimmed, and the Mth back side 200b of the Mth device wafer 200 is not thinned. Therefore, the edges of the Mth dielectric layer 202 and the Mth device wafer 200 protrude above plane P, and the Mth through-silicon via 203 is not exposed from the back side 200b of the Mth device wafer 200. This forms a wafer stack structure W1.

[0019] As shown in FIG8 , after the wafer stack structure W1 is flipped upside down, the silicon carrier wafer 1 is now positioned at the top layer and the M-th device wafer 200 is positioned at the bottom layer. Subsequently, the bottom surface 1b of the silicon carrier wafer 1 is thinned and the edge of the silicon carrier wafer 1 is trimmed to form a third silicon oxide layer OX3 covering the edges of the first device wafer 10 to the M-1 device wafer, the edges of the first dielectric layer 12 to the M-th dielectric layer 202, and the edge of the silicon carrier wafer 1. The silicon carrier wafer 1 can be thinned using chemical mechanical polishing. If glass is used as the carrier wafer, since it needs to undergo chemical mechanical polishing, the Young's modulus of glass is lower than that of silicon and it will break during the chemical mechanical polishing process. Therefore, glass cannot be used as the carrier wafer in the first embodiment. As shown in Figures 8 and 9, the thinned silicon carrier wafer 1 is immersed in an etching solution S to completely remove the silicon carrier wafer 1, exposing the first silicon oxide layer OX1. The etching solution S comprises an alkaline solution with a pH greater than 13. According to one embodiment, the etching solution S comprises tetramethylammonium hydroxide (TMAH). The first silicon oxide layer OX1 and the second silicon oxide layer OX2 are then patterned to expose the first metal connection 11 on the first device wafer 10. At this point, the wafer stack W2 is complete and can be sent to subsequent wafer packaging and testing processes. The wafer stack W2 can then be cut into multiple chip stacks.

[0020] Please refer to FIG. 1 and FIG. 9 simultaneously. A wafer stacking structure W2 includes a plurality of Nth device wafers 100, where N=1. 2...M, M ≥ 3, N is a positive integer starting from 1 and increasing in order according to Arabic numerals, all Nth device wafers 100 are stacked from bottom to top to form a wafer stack structure W2, the Nth device wafer with a larger N is below the Nth device wafer with a smaller N, when N=M, the Mth device wafer 200 is the bottom wafer in the wafer stack structure W2, when N=1, the first device wafer 10 is the top wafer in the wafer stack structure W2, the Nth device wafer 100 includes an Nth front side 100a and an Nth back side 100b, an Nth metal connection 101 is embedded in an Nth dielectric layer 102, and the Nth metal connection 101 and the Nth dielectric layer 102 cover and contact the Nth front side 100a of the Nth device wafer 100, wherein when N=1, 2. When M-1, the edges of all the Nth device wafers 100 are aligned with each other to form a plane P, and the edge of the Mth dielectric layer 202 of the Mth device wafer 200 protrudes from the plane P.

[0021] Furthermore, a first silicon oxide layer OX1 and a second silicon oxide layer OX2 cover the first metal connection 11 and the first dielectric layer 12 on the first device wafer 10, wherein the first metal connection 11 is exposed by the first silicon oxide layer OX1 and the second silicon oxide layer OX2. A first silicon oxide layer OX1 and a second silicon oxide layer OX2 are stacked together to form a silicon oxide block. Several separate silicon oxide blocks each cover and contact each first metal connection 11. A third silicon oxide layer OX3 covers and contacts the plane P and the edge of the Mth dielectric layer 202 of the Mth device wafer 200. Furthermore, each Nth device wafer 100 may include a plurality of DRAM chips or a plurality of logic chips. The types of chips on each Nth device wafer 100 may be different. For example, the first device wafer 10 may include a plurality of DRAM chips, while the second device wafer 20 may include a plurality of logic chips.

[0022] Figures 10 through 13 illustrate a process for fabricating a wafer stack structure according to a second embodiment of the present invention. Components with the same functions and positions will use the same component numbers as in the first embodiment. The difference between the second embodiment and the first embodiment lies in that the carrier wafer in the second embodiment is not a silicon carrier wafer. In the second embodiment, the silicon carrier wafer is not directly removed using an etching solution. Instead, the adhesive is removed to separate the carrier wafer from the first device wafer. The stacking method for the first to Mth device wafers in the second embodiment is the same as in the first embodiment. For detailed information on the stacking process for the first to Mth device wafers, please refer to the first embodiment.

[0023] As shown in FIG. 10 , a carrier wafer 2 is provided. The carrier wafer 2 includes a top surface 2a and a bottom surface 2b, with the top surface 2a and bottom surface 2b facing each other. The carrier wafer 2 is made of a material such as glass, metal, resin, or ceramic. A first device wafer 10 is then provided, and a first bonding process B1 is performed to bond the first device wafer 10 to the carrier wafer 2. Specifically, an adhesive A is formed to cover the top surface 2a of the carrier wafer 2. A first dielectric layer 12 is then brought into contact with the adhesive A, and the adhesive A is then heated and cured to bond the first device wafer 10 to the carrier wafer 2. The adhesive A includes a polymer adhesive, such as, but not limited to, epoxy resin, polyimide, or acrylic resin.

[0024] As shown in FIG. 11 , a second bonding process B2 is performed. When N=2…M, the value of N is increased in numerical order, and the second bonding process B2 is repeated until the Mth device wafer 200 is bonded. The second device wafer 20 through the M-1th device wafer are all subjected to edge trimming and thinning, formation of a plurality of second conductive lines 24 through the M-1th conductive line, and formation of a second insulating layer 25 through the M-1th insulating layer, as in the first embodiment. Similarly, the Mth device wafer 200 is not subjected to edge trimming and thinning.

[0025] As shown in FIG12 , the carrier wafer 2 is debonded. Debonding methods include, but are not limited to, chemical debonding, thermal release debonding, laser debonding, or mechanical debonding. The primary goal of debonding is to remove adhesive A or reduce the viscosity of adhesive A, thereby separating the carrier wafer 2 from the first device wafer 10. While the carrier wafer 2 itself remains intact, the silicon carrier wafer 1 in the first embodiment is debonded by the etching solution S. As shown in FIG13 , the first dielectric layer 12 is then planarized to expose the first metal interconnects 11, and any residual adhesive A on the first dielectric layer 12 is removed. At this point, the wafer stack structure W3 is complete.

[0026] The present invention utilizes hybrid bonding between multiple device wafers, utilizing direct electrical contact between metal wires and through-silicon vias (TSVs) to connect the upper and lower device wafers. Compared to wire bonding, the present invention enables a smaller wafer stack. Furthermore, if the silicon carrier wafer is removed using an etching solution as in the first embodiment, damage to the dies on the device wafer during carrier wafer removal can be avoided, and the step of handling residual adhesive can be eliminated. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0027] 1: Silicon carrier wafer 1a: Above 1b: Bottom 2: Carrier wafer 2a: Above 2b: Bottom 10: 1st device wafer 10a: 1st front 10b: 1st back 11: 1st metal connection 12: 1st dielectric layer 13: First silicon via 14: 1st conductive line 15: First insulation layer 20: Second device wafer 20a: 2nd front 20b: 2nd back 21: Second metal connection 22: Second dielectric layer 23: Second silicon perforation 24: Second conductive line 25: Second insulation layer 100: Nth device wafer 100a: Nth front 100b: Nth back 101: Nth metal connection 102: Nth dielectric layer 103:Nth silicon through-hole 200: Mth device wafer 200a: Front of M 200b: Mth back 201: Mth metal connection 202: Mth dielectric layer A: Adhesive B1: First bonding process B2: Second bonding process OX1: first silicon oxide layer OX2: Second silicon oxide layer OX3: third silicon oxide layer P: plane S: etching solution W1: Wafer stacking structure W2: Wafer stacking structure W3: Wafer stacking structure

Claims

1. A wafer stack structure, comprising: a plurality of device wafers, each of the device wafers being defined as an Nth device wafer, wherein N=1, 2...M, M≥3, and N is a positive integer starting from 1 and increasing in order according to Arabic numerals, all of the Nth device wafers being stacked from bottom to top to form a wafer stack structure, wherein the Nth device wafer with a larger N is below the Nth device wafer with a smaller N, when N=M, the Mth device wafer is the bottommost wafer in the wafer stack structure, and when N=1, the 1st device wafer is the topmost wafer in the wafer stack structure, the Nth device wafer including an Nth front side and an Nth back side, an Nth metal connection embedded in an Nth dielectric layer, and the Nth metal connection and the Nth dielectric layer covering and contacting the Nth front side of the Nth device wafer; wherein when N=1, 2..M-1, all edges of the Nth device wafer are aligned with each other to form a plane, and the edge of the Mth dielectric layer of the Mth device wafer protrudes from the plane; and a first silicon oxide layer and a second silicon oxide layer cover the first metal connection and the first dielectric layer on the first device wafer, wherein the first metal connection is exposed by the first silicon oxide layer and the second silicon oxide layer.

2. The wafer stack structure of claim 1, further comprising a third silicon oxide layer covering and contacting the plane and an edge of the Mth dielectric layer of the Mth device wafer.

3. The wafer stack structure of claim 1, wherein the Nth device wafer comprises a plurality of DRAM chips or a plurality of logic chips.

4. A process for forming a wafer stack structure, comprising: providing a silicon carrier wafer comprising an upper surface and a lower surface; providing a plurality of device wafers, each of the device wafers being defined as an Nth device wafer, where N=1, 2...M, M≥3, and N is a positive integer starting from 1 and increasing in Arabic numeral order, wherein the Nth device wafer comprises an Nth front side and an Nth back side, an Nth metal connection embedded in an Nth dielectric layer, and the Nth metal connection and the Nth dielectric layer cover and contact the Nth front side of the Nth device wafer, and a plurality of Nth through silicon vias are embedded from the Nth front side of the Nth device wafer into the Nth device wafer; forming a first silicon oxide layer covering and contacting the upper surface of the silicon carrier wafer; and when N=1, forming a second silicon oxide layer covering and contacting the first metal connection and the first dielectric layer on the first device wafer; After forming the first silicon oxide layer and the second silicon oxide layer, when N=1, a first bonding process is performed to bond the second silicon oxide layer on the first device wafer and the first silicon oxide layer on the silicon carrier wafer; when N=2…M, a second bonding process is repeated to complete the bonding of the Mth device wafer, and the second bonding process includes: bonding the Nth metal connection and the Nth dielectric layer on the Nth device wafer to an N-1th device wafer; after the second bonding process, thinning the bottom surface of the silicon carrier wafer and trimming the edge of the silicon carrier wafer; and immersing the thinned silicon carrier wafer in an etching solution to completely remove the silicon carrier wafer.

5. The process for manufacturing the wafer stack structure as described in claim 4 further comprises: after removing the silicon carrier wafer, patterning the first silicon oxide layer and the second silicon oxide layer to expose the first metal connection on the first device wafer.

6. The process for manufacturing the wafer stacking structure as described in claim 4 further comprises: after the first bonding process, trimming the edge of the first device wafer and then thinning the first back side of the first device wafer to expose the first silicon vias on the first device wafer; and forming a plurality of first conductive lines and a first insulating layer covering the first back side of the first device wafer, wherein each of the first conductive lines contacts each of the first silicon vias on the first device wafer.

7. A process for manufacturing a wafer stacking structure as described in claim 6, wherein the second bonding process further comprises: bonding the second metal connection on the second device wafer to each of the first conductive lines on the first device wafer; and trimming the edge of the second device wafer and then thinning the second back side of the second device wafer to expose the second silicon vias on the second device wafer.

8. A process for manufacturing a wafer stacking structure as described in claim 6, wherein when N=2...M-1, the second bonding process further comprises: before bonding the Nth metal connection and the Nth dielectric layer on the Nth device wafer to the N-1th device wafer, thinning the N-1th back side of the N-1th device wafer after trimming the edge of the N-1th device wafer to expose the N-1th silicon vias on the N-1th device wafer; forming a plurality of N-1th conductive lines and an N-1th insulating layer covering the N-1th back side of the N-1th device wafer, wherein each of the N-1th conductive lines contacts each of the N-1th silicon vias on the N-1th device wafer; wherein the Nth metal connection and the Nth dielectric layer on the N device wafer bond the N-1th conductive lines and the N-1th insulating layer.

9. A process for forming a wafer stack structure as described in claim 4, wherein when N=M, after bonding the Mth metal connection and the Mth dielectric layer on the Mth device wafer to the M-1th device wafer, the edge of the Mth device wafer is not trimmed and the Mth back side of the Mth device wafer is not thinned.

10. The process for manufacturing a wafer stacked structure according to claim 4, wherein the etching solution comprises a solution having a pH value greater than 13.

11. The process for manufacturing a wafer stack structure as claimed in claim 4, wherein the Nth device wafer comprises a plurality of DRAM chips or a plurality of logic chips.

12. The process for manufacturing a wafer stack structure as claimed in claim 4, wherein the silicon carrier wafer is opaque.

13. The process for manufacturing the wafer stack structure as described in claim 4 further includes forming a third silicon oxide layer to cover the edge of the Nth device wafer and the edge of the Nth dielectric layer before immersing the thinned silicon carrier wafer in the etching solution when N=1, 2...M.

14. A process for manufacturing a wafer stack structure, comprising: forming a wafer stack structure, the wafer stack structure comprising: a plurality of device wafers, each of the device wafers being defined as an Nth device wafer, wherein N=1, 2...M, M≥3, and N is a positive integer starting from 1 and increasing in order according to Arabic numerals, all the Nth device wafers being stacked from bottom to top to form the wafer stack structure, the Nth device wafer with a larger N being below the Nth device wafer with a smaller N, when N=M, the Mth device wafer being the bottommost wafer in the wafer stack structure, and when N=1, the 1st device wafer being the topmost wafer in the wafer stack structure, the Nth device wafer comprising an Nth front side and an Nth back side, an Nth metal connection being embedded in an Nth dielectric layer, and the Nth metal connection and the Nth dielectric layer covering and contacting the Nth front side of the Nth device wafer; wherein when N=1, 2..M-1, all edges of the Nth device wafer are aligned with each other to form a plane, and the edge of the Mth dielectric layer of the Mth device wafer protrudes from the plane; and a first silicon oxide layer is formed to cover the first metal connection and the first dielectric layer on the first device wafer, wherein the first metal connection is exposed by the first silicon oxide layer.

15. The process for manufacturing the wafer stack structure as described in claim 14 further comprises: forming a third silicon oxide layer covering and contacting the plane and the edge of the Mth dielectric layer of the Mth device wafer.

16. The process for manufacturing a wafer stack structure as claimed in claim 14, wherein the Nth device wafer comprises a plurality of DRAM chips or a plurality of logic chips.

Images