Memory device configured for detecting a connection failure between signal paths

Abstract

A memory device includes a base chip and a core chip that are stacked through a signal path. The base chip and the core chip drive the signal path after the start of a scan operation and detect a connection fail of the signal path based on a logic level at which an internal node that is connected to the signal path is driven. The base chip adjusts timing at which the logic level of the internal node is latched.

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