Electronic device

Abstract

An electronic device including a substrate and a conductive structure is provided. The conductive structure includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer is disposed on the substrate. The second conductive layer includes a concave structure and a first side portion, wherein the concave structure includes a bottom portion, a second side portion and a third side portion. The bottom portion, the second side portion and the third side portion define a concave surface. The concave structure directly contacts the first conductive layer, and the first side portion is adjacent to the second side portion. The third conductive layer directly contacts the first side portion. A vertical projection of the concave surface of the concave structure on the substrate does not overlap a vertical projection of the third conductive layer on the substrate.

Description

Technical Field

[0001] This invention relates to an electronic device. Prior Technology

[0002] Electronic devices typically require numerous conductive structures to electrically connect different conductive components or layers. These components or layers may be unable to be electrically connected due to the insulating layers sandwiched between them. Furthermore, when these components or layers are far apart or require electrical connections through deep vias, the manufacturing process becomes significantly more complex. Summary of the Invention

[0003] This invention provides an electronic device with a high yield rate.

[0004] According to an embodiment of the present invention, an electronic device is provided, including a substrate and a conductive structure. The conductive structure includes a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer is disposed on the substrate. The second conductive layer includes a recessed structure and a first side portion, wherein the recessed structure includes a bottom, a second side portion, and a third side portion. The second side portion and the third side portion are disposed on the bottom. The bottom, the second side portion, and the third side portion define a concave surface. The recessed structure directly contacts the first conductive layer, and the first side portion is adjacent to the second side portion. The third conductive layer directly contacts the first side portion. The orthographic projection of the concave surface of the recessed structure onto the substrate does not overlap with the orthographic projection of the third conductive layer onto the substrate.

[0005] Based on the above, the electronic device provided by the embodiments of the present invention provides a third conductive layer without increasing manufacturing costs, and uses the third conductive layer to ensure the electrical connection between the first conductive layer and the second conductive layer, thereby greatly improving the yield of the electronic device.

[0006] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0007] Figure 1 shows a schematic cross-sectional view of an electronic device according to a comparative example. Figure 2A shows a partial cross-sectional schematic diagram of an electronic device according to a first embodiment of the present invention. Figure 2B shows an enlarged schematic diagram of the concave structure of an electronic device according to some embodiments of the present invention. Figure 3 shows a partial cross-sectional schematic diagram of an electronic device according to a second embodiment of the present invention. Figure 4 shows a partial cross-sectional schematic diagram of an electronic device according to a third embodiment of the present invention. Figure 5 shows a partial cross-sectional schematic diagram of an electronic device according to a fourth embodiment of the present invention. Figure 6 shows a partial cross-sectional schematic diagram of an electronic device according to a fifth embodiment of the present invention. Figure 7 shows a partial cross-sectional schematic diagram of an electronic device according to a sixth embodiment of the present invention. Figure 8 shows a partial cross-sectional schematic diagram of an electronic device according to a seventh embodiment of the present invention. Figure 9 shows a partial cross-sectional schematic diagram of an electronic device according to an eighth embodiment of the present invention. Implementation

[0008] Comparative example:

[0009] Referring to Figure 1, which shows a schematic cross-sectional view of an electronic device according to a comparative example.

[0010] The electronic device 1 has an active area AA and a non-active area NAA.

[0011] Electronic device 1 includes a substrate 100. Within the active region AA, electronic device 1 further includes a first insulating layer BF, a thin-film transistor (TFT), a second insulating layer PL, a conductive layer M31, a first buffer layer BP1, a conductive layer ITO1, a second buffer layer BP2, and a conductive layer ITO21 sequentially disposed on the substrate 100. The conductive layer ITO21 is electrically connected to the TFT via a through-hole penetrating the second insulating layer PL, the first buffer layer BP1, and the second buffer layer BP2. The TFT includes a semiconductor layer POLY, a gate M1, and a source / drain M2. A gate insulating layer GI is disposed between the semiconductor layer POLY and the gate M1, and an interlayer insulating layer ILD is disposed between the semiconductor layer POLY and the source / drain M2.

[0012] In this comparative example, electronic device 1 may be a display panel. The conductive layer ITO21 in the active area AA may be a pixel electrode, and the conductive layer M31 may be used for touch sensing, but is not limited thereto.

[0013] In the comparative example shown in FIG1, the electronic device 1 further includes a shielding layer SM disposed between the first insulating layer BF and the substrate 100 and corresponding to the thin-film transistor element TFT within the active region AA. The shielding layer SM is used to block light penetrating the substrate 100 from the thin-film transistor element TFT to prevent the semiconductor layer POLY of the thin-film transistor element TFT from being irradiated by light.

[0014] The electronic device 1, within the non-active region NAA, further includes a conductive layer HM, a first insulating layer BF, a gate insulating layer GI, an interlayer insulating layer ILD, a second insulating layer PL, a conductive layer M32, a first buffer layer BP1, a second buffer layer BP2, and a conductive layer ITO22, sequentially disposed on the substrate 100. The first insulating layer BF has a first through-hole H1, and the second insulating layer PL has a second through-hole H2. The conductive layer ITO22 is disposed on the second buffer layer BP2.

[0015] In the comparative example shown in Figure 1, because a portion of the first insulating layer BF on the conductive layer HM was removed during the patterning process of the interlayer insulating layer ILD, the top surface of the conductive layer HM was exposed. Furthermore, during the patterning processes of the conductive layers M31 and M32, a portion of the conductive layer HM was removed, and the second buffer layer BP2 was filled at the location where a portion of the conductive layer HM had been removed. Ultimately, the conductive layer ITO22 and the conductive layer HM could not be electrically connected because the second buffer layer BP2 was sandwiched between them, as shown in Figure 1.

[0016] First embodiment:

[0017] Referring also to Figures 1, 2A, and 2B, Figure 2A shows a partial cross-sectional schematic diagram of an electronic device according to a first embodiment of the present invention, and Figure 2B shows an enlarged schematic diagram of the concave structure in Figure 2A.

[0018] The electronic device 2 of this first embodiment includes an active region AA and a non-active region NAA. It should be noted that although FIG2A only shows the non-active region NAA of the electronic device 2 and does not show the structure of the electronic device 2 in the active region AA, it should be understood that the active region AA of the electronic device 2 has the same structure as the active region AA of the electronic device 1 shown in FIG1. ​​The arrangement relationship between the multiple components is shown in FIG1, so it will not be described in detail here.

[0019] The electronic device 2 includes, within the non-active region NAA, a conductive layer (first conductive layer) HM, a first insulating layer BF, a gate insulating layer GI, an interlayer insulating layer ILD, a second insulating layer PL, conductive layers M32 and M33, a buffer layer BP, and a conductive layer (second conductive layer) ITO22, sequentially disposed on the substrate 100. The first insulating layer BF has a first via H1, and the second insulating layer PL has a second via H2. Conversely, within the active region AA of the electronic device 2, at least one thin-film transistor (TFT) element is disposed between the first insulating layer BF and the second insulating layer PL. The conductive layer HM is disposed on the same layer as the shielding layer SM of the active region AA.

[0020] It should be particularly noted that in the electronic device 2 of this first embodiment, when the conductive layer M32 is provided, a conductive layer (third conductive layer) M33 is simultaneously provided on the sidewall of the first through hole H1 and the sidewall of the second through hole H2, wherein the conductive layer M33 directly contacts the sidewall of the second through hole H2. The conductive layer M33 and the conductive layer M31 used for touch sensing in the active area AA can be provided in the same process without increasing manufacturing costs. Furthermore, the conductive layer ITO22 is provided on the conductive layer M33. Compared with the comparative example shown in FIG1, in the electronic device 2 of this first embodiment, even if part of the conductive layer HM is removed in the process of patterning the conductive layer M31 and the conductive layer M32, by providing the conductive layer M33 and removing the buffer layer BP in the first through hole H1 and the second through hole H2, it is still possible to ensure that the conductive layer ITO22 can be electrically connected to the conductive layer HM. It should be noted that by designing the width of the opening of the buffer layer BP above the second through hole H2 to be greater than the inner diameter of the conductive layer M33 in the first through hole H1, the buffer layer BP in both the first and second through holes H1 can be completely removed. In other words, by providing a patterned conductive layer M33 in the first and second through holes H1 and H2, the opening width of the buffer layer BP above the second through hole H2 can be correctly designed, ensuring that the buffer layer BP in both the first and second through holes H1 can be completely removed, thereby ensuring the electrical connection between the conductive layer ITO22 and the conductive layer HM.

[0021] Figure 2A shows a conductive structure including a conductive layer HM, a conductive layer ITO22, and a conductive layer M33. The conductive layer HM is disposed on a substrate 100. The conductive layer ITO22 includes a concave structure ITO22C and a side portion ITO22S. The concave structure ITO22C includes a bottom C1, a side portion C2, and a side portion C3. Side portions C2 and C3 are disposed on the bottom C1, and the bottom C1, side portions C2, and side portions C3 define a concave surface CS. Side portions C2 and C3 of the concave structure ITO22C directly contact the conductive layer HM, and side portion ITO22S is adjacent to side portion C2. The conductive layer M33 directly contacts side portion ITO22S and the conductive layer HM. The orthographic projection of the concave surface CS of the concave structure ITO22C onto the substrate 100 does not overlap with the orthographic projection of the conductive layer M33 onto the substrate 100, as shown in Figures 2A and 2B.

[0022] The aforementioned conductive structure ensures electrical connection between the conductive layer ITO22 and the conductive layer HM. In some embodiments, this electrical connection configuration can be used to heat the active region AA of the electronic device 2. The heating signal can be input through the conductive layer ITO22 and transmitted to the active region AA of the electronic device 2 through the conductive layer HM for heating. It should be noted that this conductive structure does not involve the source / drain M2 of the active region AA; therefore, the heating signal will not interfere with the operation of the thin-film transistor (TFT) element.

[0023] It should also be noted that since the conductive layer HM and the shielding layer SM of the active region AA are disposed in the same layer, the via containing the conductive layer ITO22 has a large depth (approximately 4 micrometers). Such a large depth is not conducive to achieving the electrical connection configuration between the conductive layer ITO22 and the conductive layer HM. By providing the conductive layer M33, the electrical connection between the conductive layer ITO22 and the conductive layer HM can be ensured, significantly improving the yield of the electronic device 2.

[0024] In some embodiments, the conductive layer HM and the shielding layer SM are made of the same material, including a low-reflectivity conductive material, such as molybdenum, but are not limited thereto. On the other hand, in some embodiments, the conductive layer M33 and the conductive layer M31 for touch sensing can be formed in the same process, so the conductive layer M33 can have the same low-reflectivity conductive material as the conductive layer M31, such as molybdenum, but are not limited thereto.

[0025] To fully illustrate the various embodiments of the present invention, other embodiments will be described below. It must be noted that the following embodiments use the same element reference numerals and some content as those in the foregoing embodiments, with the same reference numerals representing the same or similar elements, and descriptions of identical technical content omitted. For explanations of the omitted parts, please refer to the foregoing embodiments; these will not be repeated in the following embodiments.

[0026] Second embodiment:

[0027] Referring also to Figures 1, 3, and 2B, Figure 3 shows a partial cross-sectional schematic diagram of an electronic device according to a second embodiment of the present invention, and Figure 2B shows an enlarged schematic diagram of the concave structure in Figure 3.

[0028] The electronic device 3 of this second embodiment has an active area AA and a non-active area NAA. It should be noted that although FIG3 only shows the non-active area NAA of the electronic device 3 and does not show the structure of the electronic device 3 in the active area AA, it should be understood that the active area AA of the electronic device 3 has the same structure as the active area AA of the electronic device 1 shown in FIG1. ​​The arrangement relationship between the multiple components is shown in FIG1, so it will not be described in detail here.

[0029] The electronic device 3 includes, within the non-active region NAA, a conductive layer HM, a first insulating layer BF, a gate insulating layer GI, an interlayer insulating layer ILD, a second insulating layer PL, conductive layers M32 and M33, a buffer layer BP, and a conductive layer ITO22 sequentially disposed on a substrate 100, wherein the first insulating layer BF has a first through hole H1, and the second insulating layer PL has a second through hole H2.

[0030] Figure 3 shows a conductive structure including a conductive layer HM, a conductive layer ITO22, and a conductive layer M33. The conductive layer HM is disposed on a substrate 100. The conductive layer ITO22 includes a concave structure ITO22C and a side portion ITO22S. The concave structure ITO22C includes a bottom C1, a side portion C2, and a side portion C3. Side portions C2 and C3 are disposed on the bottom C1, and the bottom C1, side portions C2, and side portions C3 define a concave surface CS. The concave structure ITO22C directly contacts the conductive layer HM, and the side portion ITO22S is adjacent to the side portion C3. The conductive layer M33 directly contacts the side portion ITO22S. The orthographic projection of the concave surface CS of the concave structure ITO22C onto the substrate 100 does not overlap with the orthographic projection of the conductive layer M33 onto the substrate 100, as shown in Figures 3 and 2B.

[0031] It should be particularly noted that the electronic device 3 of this second embodiment differs from the electronic device 2 of the first embodiment in that the top surface of the conductive layer HM is not exposed by the first insulating layer BF during the fabrication process of the patterned interlayer insulating layer ILD. Therefore, the conductive layer HM will not be etched during the fabrication processes of the patterned conductive layers M31 and M32. The conductive layer ITO22 can directly contact and electrically connect to the conductive layer HM through the bottom C1 of the concave structure ITO22C. It should be noted that by designing the width of the opening of the buffer layer BP above the second via H2 to be greater than the inner diameter of the conductive layer M33 above the conductive layer HM, the buffer layer BP in the first via H1 and the second via H2 can be completely removed. In other words, by setting the patterned conductive layer M33, the opening width of the buffer layer BP above the second via H2 can be correctly designed, ensuring that the buffer layer BP in the first via H1 and the second via H2 can be completely removed, thereby ensuring the electrical connection between the conductive layer ITO22 and the conductive layer HM.

[0032] The aforementioned conductive structure ensures electrical connection between conductive layer ITO22 and conductive layer HM. In some embodiments, this electrical connection configuration can be used to heat the active region AA of the electronic device 3. The heating signal can be input through conductive layer ITO22 and transmitted to the active region AA of the electronic device 3 through conductive layer HM for heating. It should be noted that this conductive structure does not involve the source / drain M2 of the active region AA; therefore, the heating signal will not interfere with the operation of the thin-film transistor (TFT) element.

[0033] Third embodiment:

[0034] Referring also to Figures 1, 4, and 2B, Figure 4 shows a partial cross-sectional schematic diagram of an electronic device according to a third embodiment of the present invention, and Figure 2B shows an enlarged schematic diagram of the concave structure in Figure 4.

[0035] The electronic device 4 in this embodiment differs from the electronic device 2 shown in FIG2A in that, in the electronic device 2, the orthographic projection of the conductive layer M33 onto the conductive layer HM is a closed ring; while in the electronic device 4, the orthographic projection of the conductive layer M33 onto the conductive layer HM is a non-closed arc.

[0036] In this third embodiment, by providing a patterned conductive layer M33 in the first through hole H1 and the second through hole H2, the opening width of the buffer layer BP above the second through hole H2 can be correctly designed, ensuring that there is no buffer layer BP residue on the conductive layer M33 in the first through hole H1 and the second through hole H2, thereby ensuring the electrical connection between the conductive layer ITO22 and the conductive layer HM.

[0037] Fourth embodiment:

[0038] Referring also to Figures 1, 5, and 2B, Figure 5 shows a partial cross-sectional schematic diagram of an electronic device according to a fourth embodiment of the present invention, and Figure 2B shows an enlarged schematic diagram of the concave structure in Figure 5.

[0039] The electronic device 5 in this embodiment differs from the electronic device 3 shown in FIG3 in that, in the electronic device 3, the orthographic projection of the conductive layer M33 onto the conductive layer HM is a closed ring; while in the electronic device 5, the orthographic projection of the conductive layer M33 onto the conductive layer HM is a non-closed arc.

[0040] In this fourth embodiment, by providing a patterned conductive layer M33 in the first through hole H1 and the second through hole H2, the opening width of the buffer layer BP above the second through hole H2 can be correctly designed, ensuring that there is no buffer layer BP residue on the conductive layer M33 in the first through hole H1 and the second through hole H2, thereby ensuring the electrical connection between the conductive layer ITO22 and the conductive layer HM.

[0041] Fifth embodiment:

[0042] Referring also to Figures 1, 6, and 2B, Figure 6 shows a partial cross-sectional schematic diagram of an electronic device according to a fifth embodiment of the present invention, and Figure 2B shows an enlarged schematic diagram of the concave structure in Figure 6.

[0043] The electronic device 6 in this embodiment differs from the electronic device 2 shown in FIG2A in that, in the electronic device 2, the orthographic projection of the conductive layer M33 on the conductive layer HM is a closed ring; while in the electronic device 6, the orthographic projection of the conductive layer M33 on the conductive layer HM is a non-closed arc.

[0044] In this fifth embodiment, by providing a patterned conductive layer M33 in the first through hole H1 and the second through hole H2, the opening width of the buffer layer BP above the second through hole H2 can be correctly designed, ensuring that there is no buffer layer BP residue on the conductive layer M33 in the first through hole H1 and the second through hole H2, thereby ensuring the electrical connection between the conductive layer ITO22 and the conductive layer HM.

[0045] Sixth embodiment:

[0046] Referring also to Figures 1, 7, and 2B, Figure 7 shows a partial cross-sectional schematic diagram of an electronic device according to a sixth embodiment of the present invention, and Figure 2B shows an enlarged schematic diagram of the concave structure in Figure 7.

[0047] The electronic device 7 in this embodiment differs from the electronic device 3 shown in FIG3 in that, in the electronic device 3, the orthographic projection of the conductive layer M33 onto the conductive layer HM is a closed ring; while in the electronic device 7, the orthographic projection of the conductive layer M33 onto the conductive layer HM is a non-closed arc.

[0048] In this sixth embodiment, by providing a patterned conductive layer M33 in the first through hole H1 and the second through hole H2, the opening width of the buffer layer BP above the second through hole H2 can be correctly designed, ensuring that there is no buffer layer BP residue on the conductive layer M33 in the first through hole H1 and the second through hole H2, thereby ensuring the electrical connection between the conductive layer ITO22 and the conductive layer HM.

[0049] Seventh embodiment:

[0050] Referring also to Figures 1, 8, and 2B, Figure 8 shows a partial cross-sectional schematic diagram of an electronic device according to a seventh embodiment of the present invention, and Figure 2B shows an enlarged schematic diagram of the concave structure in Figure 8.

[0051] The electronic device 8 in this embodiment differs from the electronic device 2 shown in FIG2A in that, in the electronic device 2, the conductive layer M33 is disposed on the sidewall of the first through hole H1 and the sidewall of the second through hole H2; in the electronic device 8, the conductive layer M33 is disposed on the sidewall of the first through hole H1, but not on the sidewall of the second through hole H2.

[0052] In this seventh embodiment, by providing a patterned conductive layer M33 in the first through hole H1 and designing the width of the opening of the buffer layer BP above the first through hole H1 to be greater than the inner diameter of the conductive layer M33 in the first through hole H1, the electrical connection between the conductive layer ITO22 and the conductive layer HM can be ensured.

[0053] Eighth embodiment:

[0054] Referring also to Figures 1, 9, and 2B, Figure 9 shows a partial cross-sectional schematic diagram of an electronic device according to an eighth embodiment of the present invention, and Figure 2B shows an enlarged schematic diagram of the concave structure in Figure 9.

[0055] The electronic device 9 in this embodiment differs from the electronic device 3 shown in FIG3 in that, in the electronic device 3, the conductive layer M33 is disposed on the sidewall of the second through hole H2; while in the electronic device 9, the conductive layer M33 is disposed on the sidewall of the first through hole H1, but not on the sidewall of the second through hole H2.

[0056] In this eighth embodiment, by providing a patterned conductive layer M33 in the first through hole H1 and designing the width of the opening of the buffer layer BP above the first through hole H1 to be greater than the inner diameter of the conductive layer M33 in the first through hole H1, the electrical connection between the conductive layer ITO22 and the conductive layer HM can be ensured.

[0057] In summary, the electronic device provided by the embodiments of the present invention further provides a third conductive layer compared with the electronic device of the prior art. The third conductive layer ensures the electrical connection between the first conductive layer and the second conductive layer without increasing the manufacturing cost, and significantly improves the yield of the electronic device.

[0058] 1, 2, 3, 4, 5, 6, 7, 8, 9: Electronic devices 100:Substrate AA: Active Zone BP: Buffer layer BP1: First Buffer Layer BP2: Second Buffer Layer BF: First insulating layer C1: Bottom C2: Side C3: Side CS: Concave surface GI: Gate insulation layer HM: Conductive layer H1: First through hole H2: Second through hole ITO1: Conductive layer ITO21: Conductive layer ITO22: Conductive layer ITO22C: Concave Structure ITO22S: Side ILD: Interlayer Insulation Layer M1: Gate M2: Source / Drain M31: Conductive layer M32: Conductive layer M33: Conductive layer NAA: Non-active zone PL: Second insulating layer POLY: Semiconductor layer SM: Masking layer TFT: Thin Film Transistor

Claims

1. An electronic device comprising a substrate and a conductive structure, the conductive structure comprising: A first conductive layer is disposed on the substrate; A second conductive layer includes a concave structure and a first side portion, wherein the concave structure includes a bottom, a second side portion, and a third side portion, the second side portion and the third side portion being disposed on the bottom, the bottom, the second side portion, and the third side portion defining a concave surface, the concave structure directly contacting the first conductive layer, and the first side portion adjacent to the second side portion; and a third conductive layer directly contacting the first side portion, wherein the orthographic projection of the concave surface of the concave structure onto the substrate does not overlap the orthographic projection of the third conductive layer onto the substrate.

2. The electronic device as claimed in claim 1, wherein the third conductive layer is in direct contact with the first conductive layer.

3. The electronic device according to claim 1 further includes a first insulating layer and a second insulating layer, wherein the first insulating layer is disposed between the substrate and the second insulating layer and partially covers the first conductive layer, the first insulating layer has a first through-hole, the second insulating layer has a second through-hole, and the second conductive layer is disposed on the sidewall of the first through-hole and on the sidewall of the second through-hole.

4. The electronic device as claimed in claim 3 further includes a thin-film transistor element disposed between the first insulating layer and the second insulating layer.

5. The electronic device as claimed in claim 4 further includes a shielding layer corresponding to the thin-film transistor element and disposed in the same layer as the first conductive layer.

6. The electronic device as claimed in claim 3, wherein the third conductive layer is disposed on the sidewall of the first through-hole.

7. The electronic device as claimed in claim 3, wherein the third conductive layer is disposed on the sidewall of the second via.

8. The electronic device as claimed in claim 7, wherein the third conductive layer directly contacts the sidewall of the second via.

9. The electronic device of claim 1, wherein the conductive structure is used to heat an active region of the electronic device.

10. The electronic device of claim 1, wherein the bottom of the recessed structure directly contacts the first conductive layer.

11. The electronic device of claim 1, wherein the second side or the third side of the recessed structure directly contacts the first conductive layer.

12. The electronic device of claim 1, wherein the first conductive layer comprises a low-reflectivity conductive material.

13. The electronic device of claim 12, wherein the first conductive layer comprises molybdenum.

14. The electronic device of claim 1, wherein the third conductive layer comprises a low-reflectivity conductive material.

15. The electronic device of claim 14, wherein the third conductive layer comprises molybdenum.

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