Method of via formation and electrical connection structure
TW202636999APending Publication Date: 2026-09-01TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information
- Application Number
- TW114129754
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-06-06
- Filing Date
- 2025-08-05
- Publication Date
- 2026-09-01
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Figure TWG2TA001074244_001 
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Figure TWG2TA001074244_003
Abstract
A resist layer is formed over the dielectric layer. A pattern of via openings is imprinted in the resist layer, for example using nano imprint lithography. After the imprinting, the pattern of via openings imprinted in the resist layer is transferred to the dielectric layer by anisotropic etching to form via openings in the dielectric layer. The anisotropic etching has low etching selectivity between the resist layer and the dielectric layer. The via openings in the dielectric layer are filled with an electrically conductive material to form vias in the dielectric layer. A center line of at least one retargeting via of the vias is not parallel with a center line of at least one other via of the vias.
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