Chip stacking structure, packaging structure, electronic devices

Abstract

A wafer stacking structure, a package structure, and an electronic device are disclosed. The wafer stacking structure includes: in a first direction, a second wafer located on an even-numbered layer is offset relative to a first wafer located on an odd-numbered layer, exposing a plurality of first signal pads on the first wafer on the odd-numbered layer, the plurality of first signal pads being arranged along a second direction; in a second direction, the second wafer located on an even-numbered layer is offset relative to the first wafer located on an odd-numbered layer, exposing a plurality of first common pads on the first wafer on the odd-numbered layer, the plurality of first signal pads being arranged along the first direction, the first direction being perpendicular to the second direction; and a plurality of second common pads on the second wafer are arranged along the first direction, with leads between the first common pads and the second common pads being perpendicular to the first direction. This wafer stacking structure exhibits good performance.

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