Memory test system and test method thereof

Abstract

A memory test system and a test method thereof are provided. The memory test system includes a memory array, a voltage control device, a test device and a determine device. The voltage control device is configured to change states of a gate terminal pad, a drain terminal pad, a source terminal pad and a bulk terminal pad during a test operation. The test device is configured to provide a plurality of output signals based on changes in state of the gate terminal pad, the sink terminal pad, the source terminal pad, and the body terminal pad. The determine device determines whether a breakdown phenomenon occurs in the memory array and a location where the breakdown phenomenon occurs according to the output signals.

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