Wafer processing method

Abstract

This invention provides a wafer processing method, comprising the following steps: providing a wafer including a plurality of chips, and defining a plurality of blank areas near edges of each chip; performing N times of photolithography processes to form N layers of pattern profiles on a surface of each chip, wherein each of the photolithography processes except for a final photolithography process forms a set of ruler patterns on one of the plurality of blank areas, and each of the photolithography processes except for a first photolithography process forms a marking pattern on each set of ruler patterns that has been formed, wherein N is an integer not less than

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