Lane-wise operated single instruction, multiple data (SIMD) coprocessor

Abstract

A processing system according to the present disclosure includes a first single instruction multiple data (SIMD) coprocessor. The first SIMD coprocessor includes a plurality of SIMD registers. Each of the plurality of SIMD registers includes a plurality of SIMD lanes in data communication with a memory. The first SIMD coprocessor is configured to receive an instruction included in a first instruction set architecture. The first SIMD coprocessor is further configured to execute the instruction independent of a cross-lane operation occurring between the plurality of SIMD lanes.

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