System and method for controlling access to physical address space

Abstract

A system for controlling access to a physical address (PA) space includes a plurality of processing circuits executing a plurality of virtual machines (VMs), a plurality of system resources addressable within the PA space, a plurality of memory management units (MMUs), and a plurality of memory protection units (MPUs). A given region of the PA space is dedicated to addressing the plurality of VMs. A given MMU translates a virtual address indicated in an access request from a requesting processing circuit into a requested PA that is accessible by the requesting processing circuit according to a configurable setting of the given MMU. A given MPU coupled to a target system resource allocated with the requested PA grants or denies the access request according to a sideband signal that is included in a page table entry utilized by the plurality of MMU for virtual-to-physical address translation.

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