Technique for managing snoop filter entries
TW202638257APending Publication Date: 2026-09-16ARM LTD
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Patent Information
- Application Number
- TW115104126
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-07
- Filing Date
- 2026-02-03
- Publication Date
- 2026-09-16
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Figure TWG2TA001077147_001 
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Abstract
An apparatus is provided for receiving requests from a plurality of processing elements, where multiple of the plurality of processing elements have associated cache storage. The apparatus comprises a snoop unit configured to implement a cache coherency protocol when a request received by the apparatus identifies a cacheable address within memory. The snoop unit has snoop filter storage comprising a plurality of snoop filter entries, and snoop control circuitry configured to control allocation of the snoop filter entries. The snoop control circuitry is configured, for a given address, to allocate a selected snoop filter entry to be used to maintain information associated with the given address. The snoop control circuitry is configured, absent detection of a given condition in association with the given address, to employ a default configuration for the selected snoop filter entry where the information associated with the given address comprises coherence information used to determine which of the associated cache storages for the multiple processing elements need to be subjected to a snoop operation in response to a request specifying that given address. However, the snoop control circuitry is configured, when the given condition is detected in association with the given address, to employ a modified configuration for the selected snoop filter entry where at least a part of the information associated with the given address comprises an indication of a data value for that given address.
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