Triggered data arrangement method and memory device

TW202638259APending Publication Date: 2026-09-16SILICON MOTION INC
View PDF 0 Cites 0 Cited by

Patent Information

Application Number
TW114109250
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Filing Date
2025-03-12
Publication Date
2026-09-16

Smart Images

  • Figure TWG2TA001075883_001
    Figure TWG2TA001075883_001
  • Figure TWG2TA001075883_002
    Figure TWG2TA001075883_002
  • Figure TWG2TA001075883_003
    Figure TWG2TA001075883_003
Patent Text Reader

Abstract

The present disclosure provides a triggered data arrangement method and a memory device. The memory device includes a memory controller and a memory module. The memory module includes multiple blocks. The triggered data arrangement method includes: in response to the electronic device detecting a first trigger event, triggering, by the electronic device, the memory controller executing an aggressive garbage collection operation, wherein the aggressive garbage collection operation is used to maximize a number of spare block of multiple first blocks of a first type among the blocks; and in response to a second trigger event, stopping, by the memory controller, the aggressive garbage collection operation, wherein the aggressive garbage collection operation includes uninterrupted garbage collection operation before the second trigger event occurs.
Need to check novelty before this filing date? Find Prior Art