Frequency adjustment device and frequency adjustment method

Abstract

A frequency adjustment device operating based on a power supply and an operation frequency is provided in the present disclosure. The frequency adjustment device comprises a clock supply circuit, a clock gating component and a control circuit. The clock supply circuit is configured to output one of a plurality of clock signals as a supply clock signal. The clock gating component is configured to gate the supply clock signal to generate an output clock signal. The control circuit is configured to: when the voltage change slope of the power supply is less than a first critical slope, reduce the frequency of the output clock signal; when the voltage change slope of the power supply is greater than zero, increase the frequency of the output clock signal; and when the voltage change slope is maintained in a stable slope interval, control the clock supply circuit to select a first clock signal of the plurality of clock signals as the supply clock signal, and adjust the frequency of the output clock signal the same as the frequency of the first clock signal. The frequency of the first clock signal is the same as the operation frequency.

Description

[Technical Field]

[0001] This disclosure relates to frequency adjustment technology, and in particular to a frequency adjustment device and method for adjusting the frequency of a clock signal based on the slope of the voltage change of the power supply. [Previous Technology]

[0002] The processor of a System-On-a-Chip (SoC) may experience a momentary voltage drop in its supply voltage due to the execution of a heavy-load program, which can lead to insufficient timing margin and cause electronic circuit failure. Therefore, in some technologies, when a voltage drop in the supply voltage is detected, the clock frequency is rapidly reduced (i.e., frequency division) to reduce the power consumption of the circuit and allow the supply voltage to return to its original value.

[0003] However, the above-described operating mode may cause the circuit to trigger frequency division when it is unnecessary (e.g., when the voltage briefly approaches a critical value), thereby resulting in a decrease in operating capability. Therefore, how to more accurately determine the timing of frequency division of the clock signal is one of the issues in this field. [Summary of the Invention]

[0004] This disclosure provides a frequency adjustment device for operating according to a power supply and an operating frequency. The frequency adjustment device includes a clock supply circuit, a clock gating element, and a control circuit. The clock supply circuit outputs one of a plurality of clock signals as a supply clock signal. The clock gating element gating the supply clock signal to generate an output clock signal. The control circuit is used to: decrease the frequency of the output clock signal when the voltage change slope of the power supply is less than a first critical slope, wherein the first critical slope is less than zero; increase the frequency of the output clock signal when the voltage change slope is greater than zero; and control the clock supply circuit to select a first clock signal from the plurality of clock signals as the supply clock signal and adjust the frequency of the output clock signal to the frequency of the first clock signal when the voltage change slope remains within a stable slope range for a specified period of time. The frequency of the first clock signal is equal to the operating frequency.

[0005] This disclosure provides a frequency adjustment method applicable to a frequency adjustment device operating according to a power supply and an operating frequency. The frequency adjustment method includes: outputting one of a plurality of clock signals from a clock supply circuit as a supply clock signal; gates the supply clock signal using a clock gate element to generate an output clock signal; reducing the frequency of the output clock signal by a control circuit in response to a voltage change slope of the power supply being less than a first critical slope, wherein the first critical slope is less than zero; increasing the frequency of the output clock signal by the control circuit in response to a voltage change slope being greater than zero; and selecting a first clock signal from the plurality of clock signals as the supply clock signal by the clock supply circuit in response to a voltage change slope remaining within a stable slope range for a specified time period, and adjusting the frequency of the output clock signal to the frequency of the first clock signal by the control circuit. The frequency of the first clock signal is equal to the operating frequency.

[0006] Through the frequency adjustment device and frequency adjustment method disclosed herein, the frequency of the output clock signal can be adjusted according to the slope of the voltage change of the power supply, thereby improving the situation of reduced operating capability caused by over-triggered frequency division.

Implementation Method

[0007] For illustrative purposes, numerous specific details are set forth below to provide a thorough understanding of the embodiments of this disclosure. However, it will be apparent that one or more embodiments may be implemented without these specific details. In other instances, conventional structures and apparatuses are shown only schematically for the sake of simplicity. The embodiments of this disclosure will be described below in conjunction with the accompanying drawings. In the drawings, the same reference numerals denote the same or similar elements or method flows.

[0008] In this disclosure, when an element is referred to as a “connection,” it may mean an “electrical connection” or a “signal connection,” and when an element is referred to as a “coupled connection,” it may mean an “electrical coupling” or a “signal coupling.” “Connection” or “coupled connection” may also be used to indicate the operation or interaction between two or more elements. Unless otherwise specified in the text, “a” and “the” may refer to one or more in general. It will be further understood that the terms “comprising,” “including,” “having,” and similar terms as used herein specify the features, regions, integers, steps, operations, elements, and / or components described herein, but do not exclude one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof described or additionally.

[0009] Figure 1 is a functional block diagram of a frequency adjustment device 100 according to some embodiments of the present disclosure. In some embodiments, the frequency adjustment device 100 includes a clock supply circuit 110, a clock gate element 120, a voltage detection circuit 130, and a control circuit 140 for operating at an operating frequency according to a power supply SP.

[0010] The clock supply circuit 110 is coupled to the clock gate element 120 and the control circuit 140, and is used to receive a selection signal SS from the control circuit 140, and output a corresponding clock supply signal CLK_S to the clock gate element 120 according to the selection signal SS. In some embodiments, the clock supply circuit 110 includes clock sources 111A, 111B and a clock switching circuit 112.

[0011] Clock sources 111A and 111B are coupled to clock switching circuit 112 and are used to generate clock signals CLK_A and CLK_B to clock switching circuit 112, respectively. In some embodiments, the frequency of one of the clock signals CLK_A and CLK_B is equal to the operating frequency of frequency adjustment device 100, and the frequency of the other is less than the operating frequency of frequency adjustment device 100.

[0012] The clock switching circuit 112 is coupled to clock sources 111A and 111B, clock gate element 120, and control circuit 140. It receives a selection signal SS from control circuit 140 and outputs one of the clock signals CLK_A and CLK_B received from clock sources 111A and 111B as a supply clock signal CLK_S to clock gate element 120 according to the selection signal SS. In some embodiments, the clock switching circuit 112 can be implemented by a combination of multiple switching circuits, wherein these switching circuits are respectively connected to clock sources 111A and 111B to control one of clock sources 111A and 111B to form a short circuit with the clock switching circuit 112, and the others to form an open circuit with the clock switching circuit 112, thereby realizing the switching of the clock signal.

[0013] The clock gate element 120 is coupled to the clock supply circuit 110 and the control circuit 140 to gate the clock signal CLK_S according to the clock parameter CP received from the control circuit 140, so as to generate the output clock signal CLK_O.

[0014] Regarding the method by which the clock gate control element 120 generates the corresponding output clock signal CLK_O according to the clock parameter CP, please refer to Figure 2. Figure 2 is a timing diagram illustrating the supply clock signal CLK_S and the output clock signal CLK_O under multiple clock parameters CP, according to some embodiments of this disclosure.

[0015] In some embodiments, the clock parameter CP is a digital signal containing multiple bits. Taking the embodiment of Figure 2 as an example, the clock parameter CP is a digital signal containing 8 bits, wherein each bit has a logic low state (e.g., logic 0) or a logic high state (e.g., logic 1). Therefore, the clock parameter CP can be represented by sequences such as "(11111111)" and "(10101010)" as shown in Figure 2.

[0016] In some embodiments, the frequency of the output clock signal CLK_O is positively correlated with the number of bits in the clock parameter CP that are in a logic high state. Taking the embodiment in Figure 2 as an example, the supply clock signal CLK_S has a period TS. When the clock parameter CP is the sequence "(11111111)", the output clock signal CLK_O will have the same period TO1 as the period TS, so the frequency of the output clock signal CLK_O is the same as the frequency of the supply clock signal CLK_S; when the clock parameter CP is the sequence "(10101010)", the period TO2 of the output clock signal CLK_O is twice the period TS, so the frequency of the output clock signal CLK_O will be the same as the frequency of the supply clock signal CLK_S. The frequency of CLK_S is half of the frequency of the clock signal CLK_O. When the clock parameter CP is the sequence "(10001000)", the period TO2 of the output clock signal CLK_O is four times the period TS, so the frequency of the output clock signal CLK_O will be one-quarter of the frequency of the supply clock signal CLK_S. When the clock parameter CP is the sequence "(10000000)", the period TO2 of the output clock signal CLK_O is eight times the period TS, so the frequency of the output clock signal CLK_O will be one-eighth of the frequency of the supply clock signal CLK_S.

[0017] By adjusting the bits of the clock parameter CP described above, the clock gate element 120 can generate an output clock signal CLK_O with a corresponding frequency according to the clock parameter CP. It should be noted that although Figure 2 shows that the rise of the output clock signal CLK_O corresponds to a bit in the clock parameter CP with a logic high state (i.e., logic 1), this disclosure is not limited thereto. In some embodiments not shown, the rise of the output clock signal CLK_O corresponds to a bit in the clock parameter CP with a logic low state (i.e., logic 0), therefore the frequency of the output clock signal CLK_O is directly related to the number of bits in the clock parameter CP with a logic low state.

[0018] Please refer to Figure 1 again. The voltage detection circuit 130 is coupled to the control circuit 140 to detect the voltage change slope SL and voltage value VT of the power supply SP, and transmits the detected voltage change slope SL and voltage value VT to the control circuit 140.

[0019] The control circuit 140 is coupled to the clock supply circuit 110, the clock gate element 120, and the voltage detection circuit 130. It is used to generate a corresponding clock selection signal SS and clock parameter CP according to the voltage change slope SL and voltage value VT of the power supply SP, so as to control the frequency of the output clock signal CLK_O output by the clock gate element 120 in real time, thereby enabling the supply voltage to quickly recover to its original value after experiencing a voltage drop.

[0020] Specifically, please refer to Figure 3. Figure 3 is a timing diagram illustrating the voltage value VT and voltage change slope SL of the power supply SP according to some embodiments of this disclosure.

[0021] Before time point T1, the system operates in a normal state, so the voltage value VT will be maintained at (e.g., the processor's) operating voltage value VO. The control circuit 140 will control the clock supply circuit 110 to select a first clock signal (e.g., the clock signal CLK_A in Figure 1) with the same frequency as the operating frequency from among multiple clock signals by transmitting the selection signal SS as the supply clock signal CLK_S. And by adjusting the clock parameter CP to not block the supply clock signal CLK_S (e.g., setting the sequence of the clock parameter CP to (11111111)), the output clock signal CLK_O will be equivalent to the first clock signal.

[0022] At time point T1, due to reasons such as the processor executing an overloaded program, the voltage value VT begins to drop. In other words, starting from time point T1, the slope SL of the voltage change of the power supply SP becomes less than zero.

[0023] Between time point T1 and time point T2, the voltage change slope SL of the power supply SP gradually decreases, and at time point T2 it decreases to less than the first critical slope S1. At time point T2, the control circuit 140 adjusts the clock parameter CP to gradually reduce the frequency of the output clock signal CLK_O. In some embodiments, the first critical slope S1 is less than zero.

[0024] In some embodiments, in addition to determining whether to adjust the clock parameter CP based on the voltage change slope SL, the control circuit 140 may also determine whether to adjust the clock parameter CP based on whether the voltage value VT is less than a specific critical voltage value. In other words, in some embodiments, when the voltage change slope SL of the power supply SP drops to less than the first critical slope S1 and / or the voltage value VT is less than the first critical voltage value Vth1, the control circuit 140 will adjust the clock parameter CP to gradually reduce the frequency of the output clock signal CLK_O.

[0025] As the frequency of the output clock signal CLK_O gradually decreases, the power consumption of the circuit gradually decreases, and the voltage drop of the voltage value VT also gradually slows down. At time point T3, the voltage value VT drops to the voltage value V1 and begins to rise. As the voltage value VT begins to rise, the control circuit 140 adjusts the clock parameter CP to gradually increase the frequency of the output clock signal CLK_O back to its original operating frequency. In other words, when the voltage change slope SL changes from less than zero to greater than zero, the control circuit 140 adjusts the clock parameter CP to increase the frequency of the output clock signal CLK_O.

[0026] At time point T4, the voltage change slope SL is greater than zero and the voltage value VT rises to the second critical voltage value Vth2. At this time, the control circuit 140 will control the clock supply circuit 110 to select the second clock signal (e.g., the clock signal CLK_B in Figure 1) with a frequency lower than the operating frequency from among multiple clock signals by adjusting the selection signal SS, and adjust the clock parameter CP to increase the frequency of the output clock signal CLK_O.

[0027] In some embodiments, the reference for the control circuit 140 to determine whether to switch the clock signal selected by the clock supply circuit 110 can be, in addition to whether the voltage value VT reaches the second critical voltage value Vth2 as described above, the determination can also be based on the magnitude of the voltage change slope SL. For example, in some embodiments, when the voltage change slope SL is greater than zero and greater than the second critical slope S2, the control circuit 140 controls the clock supply circuit 110 to select a second clock signal with a frequency lower than the operating frequency as the supply clock signal CLK_S, and adjusts the clock parameter CP to increase the frequency of the output clock signal CLK_O.

[0028] At time point T5, the voltage value VT reaches a stable voltage value Vstb that is close to the operating voltage value VO. At this time, the control circuit 140 controls the clock supply circuit 110 to select a first clock signal with the same frequency as the operating frequency as the supply clock signal CLK_S, and adjusts the clock parameter CP so that the output clock signal CLK_O gradually approaches the original operating frequency.

[0029] Finally, at time point T6, the voltage value VT is maintained at a near stable voltage value Vstb, and the voltage change slope SL is maintained in a stable slope range (e.g., ±1%) for a specified period of time (e.g., the cycle of ten clock signals). At this time, the control circuit 140 controls the clock supply circuit 110 to keep selecting the first clock signal as the supply clock signal CLK_S, and adjusts the clock parameter CP to not block the supply clock signal CLK_S, thereby making the output clock signal CLK_O equal to the first clock signal (i.e., equal to the original operating frequency).

[0030] In some embodiments not shown, the clock supply circuit 110 shown in Figure 1 may include more than two clock sources (e.g., clock sources 111A, 111B and a third clock source). In this case, the clock supply circuit 110 selects one of the three clock signals as the supply clock signal CLK_S according to the clock selection signal SS. Furthermore, the control circuit 140 is further configured to control the clock supply circuit 110 to select the third clock signal provided by the third clock source as the supply clock signal CLK_S when the voltage change slope SL is greater than zero and the voltage value VT of the supply power supply SP is greater than a third critical voltage value (e.g., a voltage value between the second critical voltage value Vth2 and the stable voltage value Vstb), and adjust the clock parameter CP to increase the frequency of the output clock signal CLK_O. By setting more clock sources in the clock supply circuit 110, the frequency adjustment device 100 can realize the function of switching between more frequency levels.

[0031] Figure 4 is a flowchart illustrating a frequency adjustment method 400 according to some embodiments of this disclosure. The frequency adjustment method 400 is applicable to a frequency adjustment device (e.g., the frequency adjustment device 100 in Figure 1) that operates according to a power supply and an operating frequency. In some embodiments, the frequency adjustment method 400 includes steps S410, S420, S430, S440, S440_D, S450, S450_D, S460, S460_D, S470, and S470_D.

[0032] In step S410, a first clock signal is output as a supply clock signal by a clock supply circuit (e.g., clock supply circuit 110 in Figure 1), wherein the frequency of the first clock signal is equal to the operating frequency of the frequency adjustment device. Next, step S420 is executed.

[0033] In step S420, a clock signal is supplied by a clock gate element (e.g., clock gate element 120 in Figure 1) according to clock parameters to generate an output clock signal. Then, step S430 is executed.

[0034] In step S430, the voltage value and voltage change slope of the power supply are detected by a voltage detection circuit (e.g., voltage detection circuit 130 in Figure 1). Then, step S440_D is executed.

[0035] In step S440_D, the control circuit (e.g., control circuit 140 in Figure 1) determines whether the voltage change slope is less than the first critical slope (e.g., the first critical slope S1 in Figure 3). When the control circuit determines that the voltage change slope is less than the first critical slope, step S440 is executed; when the control circuit determines that the voltage change slope is not less than (and equal to or greater than) the first critical slope, step S430 is executed again.

[0036] In step S440, the clock parameters transmitted to the clock gate element are adjusted by the control circuit to reduce the frequency of the output clock signal. Next, step S450_D is executed.

[0037] In step S450_D, the control circuit determines whether the voltage change slope is greater than zero (i.e., whether the voltage value has started to rise). When the control circuit determines that the voltage change slope is greater than zero, step S450 is executed; when the control circuit determines that the voltage change slope is not greater than zero (i.e., equal to or less than zero), step S440 is executed again.

[0038] In step S450, the clock parameters transmitted to the clock gate element are adjusted by the control circuit to increase the frequency of the output clock signal. Next, step S460_D is executed.

[0039] In step S460_D, the control circuit determines whether the voltage value of the power supply is greater than a critical voltage value (for example, the second critical voltage value Vth2 in Figure 3). When the control circuit determines that the voltage value is greater than the critical voltage value, step S460 is executed; when the control circuit determines that the voltage value is not greater than (and equal to or less than) the critical voltage value, step S450 is executed again.

[0040] In step S460, the clock supply circuit selects a second clock signal as the supply clock signal, and the control circuit adjusts the clock parameters to increase the frequency of the output clock signal, wherein the frequency of the second clock signal is less than the operating frequency of the frequency adjustment device. Next, step S470_D is executed.

[0041] In step S470_D, the control circuit determines whether the voltage value of the power supply is maintained at a stable voltage value (e.g., the stable voltage value Vstb in Figure 3). When the control circuit determines that the voltage value is maintained at a stable voltage value, step S470 is executed; when the control circuit determines that the voltage value has not been maintained at a stable voltage value, step S460 is executed again.

[0042] In step S470, the first clock signal is selected again as the supply clock signal by the clock supply circuit, and the clock parameters are adjusted by the control circuit so as not to block the first clock signal (i.e. the supply clock signal), but only to make the frequency of the output clock signal equal to the operating frequency of the frequency adjustment device.

[0043] It should be noted that the number and order of steps in the frequency adjustment method 400 of this disclosure are merely examples and are not intended to limit this disclosure. The number and order of other steps are all within the scope of this disclosure. In some embodiments, the frequency adjustment method 400 further includes the step of determining whether the voltage value is less than the first critical voltage value Vth1 as described above. In some embodiments, the frequency adjustment method 400 further includes the step of determining whether the voltage change slope is greater than the second critical slope S2.

[0044] Through the frequency adjustment device 100 and frequency adjustment method 400 disclosed herein, the frequency of the clock signal used can be adjusted in real time when the voltage change slope of the power supply reaches a specified critical value. In addition to improving the ability to solve voltage drop problems by performing frequency division earlier, it can also improve the problem of reduced operating performance caused by frequent frequency division when the voltage value of the power supply is close to the critical value in general frequency adjustment devices.

[0045] The above are merely preferred embodiments of this disclosure. Various modifications and equivalent changes can be made to the structure of this disclosure without departing from its scope or spirit. In summary, all modifications and equivalent changes made to this disclosure within the scope of the following claims are within the scope of this disclosure. [Simplified Explanation of the Diagram]

[0046] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described as follows: Figure 1 is a functional block diagram of a frequency adjustment device according to some embodiments of this disclosure; Figure 2 is a timing diagram of a supply clock signal and an output clock signal under multiple clock parameters according to some embodiments of this disclosure; Figure 3 is a timing diagram of the voltage value and voltage change slope of the supply power supply according to some embodiments of this disclosure; and Figure 4 is a flowchart of a frequency adjustment method according to some embodiments of this disclosure. [Biomaterial Storage]

[0048] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A frequency adjustment device for operating according to a power supply and an operating frequency, the frequency adjustment device comprising: a clock supply circuit for outputting one of a plurality of clock signals as a supply clock signal; a clock gate element for gated the supply clock signal to generate an output clock signal; a voltage detection circuit for detecting a voltage change slope and a voltage value of the power supply; and a control circuit for: reducing a frequency of the output clock signal when the voltage change slope of the power supply is less than a first critical slope, wherein the first critical slope is less than zero; increasing the frequency of the output clock signal when the voltage change slope is greater than zero; and controlling the clock supply circuit to select a first clock signal from the plurality of clock signals as the supply clock signal and adjusting the frequency of the output clock signal to the frequency of the first clock signal when the voltage change slope is maintained within a stable slope range for a specified time period, wherein the frequency of the first clock signal is equal to the operating frequency.

2. The frequency adjustment device as claimed in claim 1, wherein the control circuit is further configured to: when the voltage value of the power supply is less than a first threshold voltage value, control the clock supply circuit to select the first clock signal among the plurality of clock signals as the supply clock signal, and reduce the frequency of the output clock signal.

3. The frequency adjustment device as claimed in claim 1, wherein the control circuit is further configured to: when the voltage value of the power supply rises to a value greater than a second threshold voltage value, control the clock supply circuit to select a second clock signal from the plurality of clock signals as the supply clock signal, and increase the frequency of the output clock signal, wherein a frequency of the second clock signal is less than the operating frequency.

4. The frequency adjustment device as claimed in claim 3, wherein the control circuit is further configured to: when the voltage value of the power supply is equal to a stable voltage value for the specified time period, control the clock supply circuit to select the first clock signal as the supply clock signal, and adjust the frequency of the output clock signal to the frequency of the first clock signal.

5. The frequency adjustment device as claimed in claim 4, wherein the clock supply circuit comprises: a first clock source for generating the first clock signal; a second clock source for generating the second clock signal; and a clock switching circuit coupled to the first clock source, the second clock source and the control circuit, for receiving a clock selection signal from the control circuit and selecting one of the first clock signal and the second clock signal as the supplied clock signal according to the clock selection signal.

6. The frequency adjustment device as claimed in claim 5, wherein the clock supply circuit further comprises: a third clock source coupled to the clock switching circuit and used to generate a third clock signal, wherein a frequency of the third clock signal is greater than the frequency of the second clock signal and less than the operating frequency, wherein the clock switching circuit is used to select one of the first clock signal, the second clock signal and the third clock signal as the supply clock signal according to the clock selection signal, and wherein the control circuit is further used to control the clock supply circuit to select the third clock signal as the supply clock signal and increase the frequency of the output clock signal when the voltage value of the power supply rises to a value greater than a third threshold voltage value, wherein the third threshold voltage value is greater than the second threshold voltage value and less than the stable voltage value.

7. The frequency adjustment device as claimed in claim 1, wherein the control circuit is further configured to: when the voltage change slope rises to a level greater than a second critical slope, control the clock supply circuit to select a second clock signal from the plurality of clock signals as the supply clock signal, wherein a frequency of the second clock signal is less than the operating frequency.

8. The frequency adjustment device as claimed in claim 1, wherein the clock gate element is used to gate the supplied clock signal according to a clock parameter generated by the control circuit, wherein the clock parameter is a digital signal comprising a plurality of bits, each of the plurality of bits being in a logic high state or a logic low state, and the frequency of the output clock signal is positively correlated with the number of the plurality of bits being in the logic high state.

9. A frequency adjustment method applicable to a frequency adjustment device operating according to a power supply and an operating frequency, the frequency adjustment method comprising: outputting one of a plurality of clock signals as a supply clock signal via a clock supply circuit; gate the supply clock signal via a clock gate element to generate an output clock signal; detecting a voltage change slope and a voltage value of the power supply via a voltage detection circuit; and reducing a frequency of the output clock signal via a control circuit in response to the voltage change slope of the power supply being less than a first critical slope, wherein the first critical slope is less than zero. In response to the voltage change slope being greater than zero, the frequency of the output clock signal is increased by the control circuit; and in response to the voltage change slope being maintained within a stable slope range for a specified period of time, the clock supply circuit selects a first clock signal from the plurality of clock signals as the supply clock signal, and the frequency of the output clock signal is adjusted by the control circuit to a frequency of the first clock signal, wherein the frequency of the first clock signal is equal to the operating frequency.

10. The frequency adjustment method as claimed in claim 9 further comprises: in response to the voltage value of the power supply rising to a value greater than a second threshold voltage value, selecting a second clock signal from the plurality of clock signals as the supply clock signal by the clock supply circuit, and increasing the frequency of the output clock signal by the control circuit, wherein a frequency of the second clock signal is less than the operating frequency.

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