System and method for providing high-frequency Anti-tamper protection in communication interface

Abstract

Systems, methods, and apparatuses include a first counter to count a number of clock pulses received by the communication interface within a predetermined time window, a second counter pre-loaded with a predetermined count value indicating a threshold number of clock pulses expected to be received within the predetermined time window, and a comparator to compare a count value of the second counter to the threshold number of clock pulses. Control circuitry may enable the first counter when a chip select signal is asserted, disable the first counter when the chip select signal is de-asserted, start the second counter when a clock pulse is received, stop the second counter when a predetermined number of clock pulses have been received, and trigger a tamper signal if the count value of the second counter is greater than the threshold number of clock pulses.

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