Pixel circuit and method for reducing leakage current

TW202638386AActive Publication Date: 2026-09-16RAYDIUM SEMICON
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Patent Information

Application Number
TW114108290
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Filing Date
2025-03-06
Publication Date
2026-09-16
Estimated Expiration
2045-03-05

AI Technical Summary

Technical Problem

Conventional micro-LED pixel circuits face issues with leakage currents, particularly reverse PN junction leakage current, which affect the performance of ultra-high resolution displays.

Method used

A 5T1C architecture is introduced, where the body electrode of the third transistor is coupled to a reference voltage instead of the operating voltage, reducing reverse junction leakage current, and a voltage divider structure is used with two capacitors to enhance grayscale distinction.

Benefits of technology

The solution effectively reduces leakage currents, enabling better current balance and improved grayscale distinction in ultra-high resolution displays, suitable for wafer-based manufacturing processes.

✦ Generated by Eureka AI based on patent content.

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Patent Text Reader

Abstract

A pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitor. The second transistor is coupled between a first power supply voltage and the first terminal of the first transistor. The control terminal of the second transistor is coupled to a first node. The third transistor is coupled between a first reference voltage and the first node. The fourth transistor is coupled between a data voltage and a second node. The fifth transistor is coupled between the second node and a second reference voltage. The first capacitor is coupled between the second node and the first node. The body electrode of the third transistor is coupled to the first reference voltage.
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Description

[Technical Field]

[0001] This invention relates to a light-emitting diode (LED) pixel circuit, and in particular to an LED pixel circuit that reduces the reverse PN junction leakage current after the transistor is turned off. [Previous Technology]

[0002] Please refer to Figure 1, which shows a schematic diagram of a conventional micro-light-emitting diode (LED) pixel circuit. As shown in Figure 1, the conventional LED pixel circuit P10 adopts a 2T1C (two transistors and one capacitor) architecture. The second transistor PM2 of the LED pixel circuit 1 is turned on column by column through the scan line to write the voltage of the data line into the pixel and store it in the capacitor PC1. The first transistor PM1 generates current of different magnitudes to drive the LED. Afterwards, when the second transistor PM2 is turned off, the amount of electricity stored in the capacitor PC1 can still maintain the voltage difference between the gate and source terminals of the first transistor PM1, so that the first transistor PM1 continues to generate current, thereby reducing power consumption.

[0003] With the development of technology, users' requirements for pixel quality are increasing. Depositing various thin-film transistors (TFTs) on substrates using conventional processes can no longer provide smaller and better resolutions. In this field, products with ultra-high resolution (e.g., AR glasses) will instead use wafer-based processes.

[0004] However, wafer fabrication processes may encounter leakage current problems. For example, when the second transistor PM2 of the micro-LED pixel circuit P10 shown in Figure 1 is turned off, two leakage current paths may be generated. Specifically, referring to Figure 2, one is when the second transistor PM2 operates in the subcritical region (not completely turned off), there may be a bias voltage between the source and drain terminals of the second transistor PM2, forming a subcritical leakage current ISUB (as shown in PL1 in Figure 2); the other is when the second transistor PM2 is turned off, the reverse bias voltage of the PN junction between its drain and body terminals will be too large, forming a reverse PN junction leakage current IDR (as shown in PL2 in Figure 2). [Summary of the Invention]

[0005] Therefore, the present invention proposes a light-emitting diode pixel circuit that reduces the reverse PN junction leakage current after the transistor is turned off, thereby effectively solving the above-mentioned problems encountered in the prior art.

[0006] A preferred embodiment of the present invention provides a light-emitting diode (LED) pixel circuit. In this embodiment, the LED pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitor. The control terminal of the first transistor is controlled by a first control signal. The second transistor is coupled between a first power supply voltage and a first terminal of the first transistor, and the control terminal of the second transistor is coupled to a first node. The third transistor is coupled between a first reference voltage and the first node, and the control terminal of the third transistor is controlled by the first control signal. The fourth transistor is coupled between a data voltage and a second node, and the control terminal of the fourth transistor is controlled by a second control signal. The fifth transistor is coupled between the second node and a second reference voltage, and the control terminal of the fifth transistor is controlled by the first control signal. The first capacitor is coupled between the second node and the first node. The body electrode of the third transistor is coupled to the first reference voltage.

[0007] In one embodiment, the light-emitting diode pixel circuit further includes a second capacitor coupled between the operating voltage and the first node.

[0008] In one embodiment, the body electrodes of the first transistor, the second transistor, the fourth transistor and the fifth transistor are coupled to the operating voltage.

[0009] In one embodiment, the bulk of the third transistor is a wafer substrate.

[0010] In one embodiment, the second end of the first transistor is coupled to a second power supply voltage via a micro-light-emitting diode.

[0011] In one embodiment, the first reference voltage and the second reference voltage are between the first power supply voltage and the second power supply voltage, and the first reference voltage is greater than the second reference voltage.

[0012] In one embodiment, during the data writing stage, the second, third and fourth transistors are turned on and the first and fifth transistors are turned off, the first node has a first reference voltage and the second node has a data voltage.

[0013] In one embodiment, during the light emission stage, the first transistor, the second transistor and the fifth transistor are turned on and the third transistor and the fourth transistor are turned off, the second node has a second reference voltage and the first node has a voltage of at least a portion of the first reference voltage plus the second reference voltage minus the data voltage.

[0014] In one embodiment, the first reference voltage is selected based on the average range of the micro-light-emitting diode current controlled by the second transistor.

[0015] In one embodiment, the second reference voltage is selected from 0.5 to 1.5 times the data voltage.

[0016] A preferred embodiment of the present invention provides a method for reducing leakage current in a light-emitting diode (LED) pixel circuit. In this embodiment, the method includes: providing a second transistor configured to control the current of a micro LED according to a data voltage, the control terminal of the second transistor being coupled to a first node; providing a third transistor coupled between a first reference voltage and the first node, wherein the body of the third transistor is coupled to the first reference voltage; and providing a first capacitor coupled between a second node and the first node; wherein during a data writing phase, the first node has a first reference voltage and the second node has a data voltage; during a light-emitting phase, the second node has a second reference voltage and the first node has a voltage equal to at least a portion of the first reference voltage plus the second reference voltage minus the data voltage.

[0017] In one embodiment, the body electrode of the second transistor is coupled to the operating voltage.

[0018] In one embodiment, the bulk of the third transistor is a wafer substrate.

[0019] In one embodiment, the method further includes: setting a first transistor, a first end of the first transistor being coupled to a second power supply voltage via a micro-light-emitting diode, and a second end of the first transistor being coupled to a second transistor.

[0020] In one embodiment, the first reference voltage and the second reference voltage are between the first power supply voltage and the second power supply voltage, and the first reference voltage is greater than the second reference voltage.

[0021] In one embodiment, the first reference voltage is selected based on the average range of the micro-light-emitting diode current controlled by the second transistor.

[0022] In one embodiment, the second reference voltage is selected from 0.5 to 1.5 times the data voltage.

[0023] Compared to prior art, the light-emitting diode (LED) pixel circuit and method proposed in this invention can be applied to ultra-high resolution display panels, and can be designed using CMOS process technology to adapt to extremely small pixel areas, thereby achieving leakage current balance and effectively solving the problem that traditional micro LED pixel circuits using a 2T1C (two transistors and one capacitor) architecture are easily affected by transistor leakage current, resulting in uneven driving current. In this invention, the body electrode of the third transistor, which is coupled between the first reference voltage and the first node, is coupled to the first reference voltage instead of the operating voltage, which can reduce the reverse junction leakage current formed by excessive reverse bias voltage between the body electrode of the third transistor and other junctions.

Implementation Method

[0024] Any reference to elements referred to herein by names such as "first," "second," etc., does not generally limit the number or order of these elements. Rather, these names are used herein as a convenient way to distinguish two or more elements or instances of elements. Therefore, it should be understood that the names "first," "second," etc., in the claim do not necessarily correspond to the same names in the written description. Furthermore, it should be understood that references to first and second elements do not imply that only two elements can be used or that the first element must precede the second element. The terms "comprising," "including," "having," "containing," etc., as used herein are open-ended, meaning that they include but are not limited to.

[0025] The term "connection" is used herein to refer to a direct or indirect link between two structures. For example, in one example of an indirect connection, one structure may be connected to another structure via a band.

[0026] In this invention, the terms "exemplary" and "for example" are used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" or "for example" is not necessarily to be construed as preferred or advantageous over other aspects of the invention. The terms "about" and "approximately" as used herein with respect to specified values ​​or characteristics are intended to mean within a certain value (e.g., 10%) of the specified value or characteristic.

[0027] A preferred embodiment of the present invention is a light-emitting diode (LED) pixel circuit. In this embodiment, the LED pixel circuit adopts a 5T1C (five transistors and one capacitor) architecture for use in an ultra-high resolution display panel, and can be manufactured using a wafer-based process. An exemplary definition of a wafer-based process is that the transistors are formed on a wafer substrate; in other words, the body of the transistor is a wafer substrate, but this is not a limitation.

[0028] Please refer to Figure 3, which shows a schematic diagram of the light-emitting diode pixel circuit 10 in this embodiment.

[0029] As shown in Figure 3, the light-emitting diode pixel circuit 10 in this embodiment includes a first transistor (M1), a second transistor (M2), a third transistor (M3), a fourth transistor (M4), a fifth transistor (M5), and a first capacitor (C1). The control terminal of the first transistor (M1) is controlled by a first control signal (EM[N]). The second transistor (M2) is coupled between a first power supply voltage (ELVDD) and a first terminal of the first transistor (M1), and the control terminal of the second transistor (M2) is coupled to a first node (A). The third transistor (M3) is coupled between a first reference voltage (V1) and the first node (A), and the control terminal of the third transistor (M3) is controlled by the first control signal (EM[N]). The fourth transistor (M4) is coupled between a data voltage (VDATA) and a second node (B), and the control terminal of the fourth transistor (M4) is controlled by a second control signal (S[N]). The fifth transistor (M5) is coupled between the second node (B) and the second reference voltage (V2), and the control terminal of the fifth transistor (M5) is controlled by the first control signal (EM[N]). The first capacitor (C1) is coupled between the second node (B) and the first node (A). The body electrode of the third transistor (M3) is coupled to the first reference voltage (V1), and the body electrodes of the first transistor (M1), the second transistor (M2), the fourth transistor (M4), and the fifth transistor (M5) are coupled to the operating voltage (VDD). The second terminal of the first transistor (M1) is coupled to the second power supply voltage (ELVSS) via a micro-light-emitting diode (uLED).

[0030] Please refer to Figure 4-5 for an explanation of the operation of the light-emitting diode pixel circuit 10 (i.e., data writing and light emission).

[0031] As shown in Figure 4, during the data writing stage, the second transistor (M2), the third transistor (M3), and the fourth transistor (M4) are turned on, while the first transistor (M1) and the fifth transistor (M5) are turned off. The first node (A) has a first reference voltage (V1), and the second node (B) has a data voltage (V DATA). Specifically, the first control signal (EM[N]) controls the third transistor (M3) to turn on and the first transistor (M1) and the fifth transistor (M5) to turn off. Due to the turn-on of the third transistor (M3), the voltage of the first node (A) (i.e., the control terminal of the second transistor (M2)) is the second reference voltage (V2), and the second transistor (M2) is turned on. The second control signal (S[N]) turns on the fourth transistor (M4). During the writing stage shown in Figure 4, the data voltage (V DATA) of the data line is written into the second node (B) of the light-emitting diode pixel circuit 10 and stored in the first capacitor (C1).

[0032] It should be noted that the first transistor (M1), the second transistor (M2), the third transistor (M3), the fourth transistor (M4), and the fifth transistor (M5) of the present invention are not limited in type (e.g., P-type or N-type). Therefore, the first control signal (EM[N]) or the second control signal (S[N]) corresponding to the first transistor (M1), the second transistor (M2), the third transistor (M3), the fourth transistor (M4), and the fifth transistor (M5) can be selected for control according to the type of the first transistor (M1), the second transistor (M2), the third transistor (M3), the fourth transistor (M4), and the fifth transistor (M5). For example, when the third transistor (M3) is the same type of transistor as the first transistor (M1) and the fifth transistor (M5), the first control signal (EM[N]) that controls the third transistor (M3) to turn on and the first transistor (M1) and the fifth transistor (M5) to turn off can be set through logic operations such as reverse gate, so as to achieve the purpose of controlling the third transistor (M3), the first transistor (M1) and the fifth transistor (M5).

[0033] As shown in Figure 5, during the light-emitting stage, the first transistor (M1), the second transistor (M2), and the fifth transistor (M5) are turned on, while the third transistor (M3) and the fourth transistor (M4) are turned off. The second node (B) has a second reference voltage (V2), and the first node (A) has a voltage equal to at least a portion of the first reference voltage (V1) plus the second reference voltage (V2) minus the data voltage (V DATA). Specifically, the second node (B) will be written with the second reference voltage (V2) due to the conduction of the fifth transistor (M5). At this time, the voltage of the first node (A) will be the first reference voltage (V1) plus the second reference voltage (V2) minus the data voltage (V DATA), expressed as follows: The second transistor (M2) is controlled by the voltage of the first node (A) to make the current of the micro-LED (uLED) as follows:

[0034] In one embodiment, the first reference voltage (V1) and the second reference voltage (V2) are between the first power supply voltage (ELVDD) and the second power supply voltage (ELVSS), and the first reference voltage (V1) is greater than the second reference voltage (V2). In one embodiment, the first reference voltage (V1) is selected based on the average range of the micro-light-emitting diode (uLED) current controlled by the second transistor (M2). In one embodiment, the second reference voltage (V2) is selected from 0.5 to 1.5 times the data voltage (VDATA).

[0035] In summary, by coupling the body of the third transistor (M3) coupled between the first reference voltage (V1) and the first node (A) to the first reference voltage (V1) instead of the operating voltage (VDD), the reverse junction leakage current formed by excessive reverse bias between the body of the third transistor (M3) and other junctions can be reduced.

[0036] In one embodiment, the light-emitting diode (LED) pixel circuit 20 further includes a second capacitor coupled between the operating voltage (VDD) and the first node (A). Specifically, please refer to FIG6, which illustrates the LED pixel circuit 20 including the second capacitor (C2). Through the voltage division between the first capacitor (C1) and the second capacitor (C2), the range of the data voltage (VDATA) can be increased, making the grayscale distinction of the LED pixel circuit 20 more distinct.

[0037] For example, the operation of the light-emitting diode pixel circuit 20 (i.e., data writing and light emission) is illustrated in Figures 7-8.

[0038] As shown in Figure 7, during the data writing stage, the second transistor (M2), the third transistor (M3), and the fourth transistor (M4) are turned on, while the first transistor (M1) and the fifth transistor (M5) are turned off. The first node (A) has a first reference voltage (V1), and the second node (B) has a data voltage (V DATA). Specifically, the first control signal (EM[N]) controls the third transistor (M3) to turn on and the first transistor (M1) and the fifth transistor (M5) to turn off. Due to the turn-on of the third transistor (M3), the voltage of the first node (A) (i.e., the control terminal of the second transistor (M2)) is the second reference voltage (V2), and the second transistor (M2) is turned on. The second control signal (S[N]) turns on the fourth transistor (M4). During the writing stage shown in Figure 7, the data voltage (V DATA) of the data line is written into the second node (B) of the light-emitting diode pixel circuit 20 and stored in the first capacitor (C1).

[0039] As shown in Figure 8, during the light-emitting stage, the first transistor (M1), the second transistor (M2), and the fifth transistor (M5) are turned on, while the third transistor (M3) and the fourth transistor (M4) are turned off. The second node (B) has a second reference voltage (V2), and the first node (A) has a voltage equal to at least a portion of the first reference voltage (V1) plus the second reference voltage (V2) minus the data voltage (VDATA). Specifically, the second node (B) will be written with the second reference voltage (V2) due to the conduction of the fifth transistor (M5). At this time, the voltage of the first node (A) will be the first reference voltage (V1) plus the second reference voltage (V2) minus the data voltage (VDATA) through the voltage division result of the first capacitor (C1) and the second capacitor (C2), and the formula is as follows: The second transistor (M2) is controlled by the voltage of the first node (A), so that the current of the micro-light-emitting diode (uLED) is as follows:

[0040] Compared to the prior art, in the LED pixel circuit 20, the body of the third transistor (M3), which is coupled between the first reference voltage (V1) and the first node (A), is coupled to the first reference voltage (V1) instead of the operating voltage (VDD). This reduces the reverse junction leakage current caused by excessive reverse bias between the body of the third transistor (M3) and other junctions. Furthermore, the LED pixel circuit 20 has a first capacitor (C1) and a second capacitor (C2) forming a voltage divider structure, which can increase the range of data voltage (VDATA) and make the grayscale distinction of the LED pixel circuit 20 more distinct.

[0041] A preferred embodiment of the present invention provides a method for reducing leakage current in a light-emitting diode (LED) pixel circuit. In this embodiment, the method for reducing leakage current in the LED pixel circuit can be applied to an ultra-high resolution display panel and can be manufactured using a wafer fabrication process.

[0042] Please refer to Figure 9, which is a flowchart of a method for reducing leakage current in a light-emitting diode pixel circuit.

[0043] As shown in Figure 9, the method for reducing the leakage current of a light-emitting diode (LED) pixel circuit includes: (step S1) setting a second transistor configured to control the micro LED current according to the data voltage, wherein the control terminal of the second transistor is coupled to a first node; (step S2) setting a third transistor coupled between a first reference voltage and the first node, wherein the body electrode of the third transistor is coupled to the first reference voltage; and (step S3) setting a first capacitor coupled between a second node and the first node; wherein during the data writing stage, the first node has a first reference voltage and the second node has a data voltage; during the light-emitting stage, the second node has a second reference voltage and the first node has a voltage equal to at least a portion of the first reference voltage plus the second reference voltage minus the data voltage. It should be noted that steps S1-S3 are merely example flows and do not limit the implementation sequence of the method for reducing the leakage current of an LED pixel circuit. Those skilled in the art can adjust steps S1-S3 according to design conditions to implement the method for reducing the leakage current of an LED pixel circuit according to the present invention.

[0044] In one embodiment, the method further includes: setting a first transistor, a first end of the first transistor being coupled to a second power supply voltage via a micro-light-emitting diode, and a second end of the first transistor being coupled to a second transistor.

[0045] The method for reducing leakage current in the light-emitting diode pixel circuit of the present invention can be used in a 4T1C (four transistors and one capacitor) architecture, a 4T2C (four transistors and two capacitors) architecture, a 5T1C (five transistors and one capacitor) architecture, or a 5T2C (five transistors and two capacitors) architecture for application in ultra-high resolution display panels. Furthermore, because the body electrode of the third transistor is coupled to the first reference voltage, the leakage current when the third transistor is turned off is significantly reduced. This feature is even more pronounced when applied to wafer fabrication processes.

[0046] The prior description of the invention is provided to enable those skilled in the art to make or practice the invention. Various modifications to the invention will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations or embodiments can be combined with or implemented individually without departing from the spirit or scope of the invention. Therefore, the invention is not intended to be limited to the examples described herein, but is accorded the widest scope consistent with the principles and novel features of the invention herein. [Simplified Explanation of the Diagram]

[0047] The accompanying drawings presented in this invention are intended to help describe various embodiments of the invention. However, to simplify the drawings and / or highlight what the drawings are intended to present, known structures and / or elements in the drawings may be drawn in a simple schematic manner or presented in an omitted manner. On the other hand, the number of elements in the drawings may be singular or plural. The accompanying drawings presented in this invention are only for illustrating these embodiments and not for limiting them.

[0048] Figure 1 shows a schematic diagram of a conventional micro-light-emitting diode pixel circuit.

[0049] Figure 2 shows a schematic diagram of the leakage current path of a traditional micro-light-emitting diode pixel circuit.

[0050] Figure 3 shows a circuit diagram of a light-emitting diode pixel circuit in one embodiment of the present invention.

[0051] Figure 4 illustrates a schematic diagram of the light-emitting diode pixel circuit operating in the data writing stage in one embodiment of the present invention.

[0052] Figure 5 illustrates a schematic diagram of the light-emitting diode pixel circuit operating in the light-emitting stage in one embodiment of the present invention.

[0053] Figure 6 shows a circuit diagram of a light-emitting diode pixel circuit in one embodiment of the present invention.

[0054] Figure 7 illustrates a schematic diagram of the light-emitting diode pixel circuit operating in the data writing stage in one embodiment of the present invention.

[0055] Figure 8 illustrates a schematic diagram of the light-emitting diode pixel circuit operating in the light-emitting stage in one embodiment of the present invention.

[0056] Figure 9 illustrates an embodiment of the present invention, while Figure 8 is a flowchart of a method for reducing leakage current in a light-emitting diode pixel circuit.

Claims

1. A light-emitting diode pixel circuit, comprising: A first transistor, the control terminal of which is controlled by a first control signal; A second transistor is coupled between a first power supply voltage and a first terminal of the first transistor, and the control terminal of the second transistor is coupled to a first node; a third transistor is coupled between a first reference voltage and the first node, and the control terminal of the third transistor is controlled by the first control signal; a fourth transistor is coupled between a data voltage and a second node, and the control terminal of the fourth transistor is controlled by a second control signal; a fifth transistor is coupled between the second node and a second reference voltage, and the control terminal of the fifth transistor is controlled by the first control signal. and a first capacitor coupled between the second node and the first node; wherein the body electrode of the third transistor is coupled to the first reference voltage.

2. The light-emitting diode pixel circuit as described in claim 1, further comprising: A second capacitor is coupled between an operating voltage and the first node.

3. The light-emitting diode pixel circuit as described in claim 1, wherein the body electrodes of the first transistor, the second transistor, the fourth transistor, and the fifth transistor are coupled to an operating voltage.

4. The light-emitting diode pixel circuit as described in claim 1, wherein the body of the third transistor is a wafer substrate.

5. The light-emitting diode pixel circuit as claimed in claim 1, wherein a second terminal of the first transistor is coupled to a second power supply voltage via a micro-light-emitting diode.

6. The light-emitting diode pixel circuit as described in claim 5, wherein the first reference voltage and the second reference voltage are between the first power supply voltage and the second power supply voltage, and the first reference voltage is greater than the second reference voltage.

7. The light-emitting diode pixel circuit as claimed in claim 1, wherein during a data writing phase, the second transistor, the third transistor, and the fourth transistor are turned on and the first transistor and the fifth transistor are turned off, the first node has the first reference voltage, and the second node has the data voltage.

8. The light-emitting diode pixel circuit as claimed in claim 1, wherein during a light-emitting phase, the first transistor, the second transistor, and the fifth transistor are turned on and the third transistor and the fourth transistor are turned off, the second node has the second reference voltage, and the first node has a voltage consisting of the first reference voltage plus at least a portion of the second reference voltage minus the data voltage.

9. The light-emitting diode pixel circuit as claimed in claim 1, wherein the first reference voltage is selected based on the average range of one of the micro light-emitting diode currents controlled by the second transistor.

10. The light-emitting diode pixel circuit as claimed in claim 1, wherein the second reference voltage is selected from 0.5 to 1.5 times the data voltage.

11. A method for reducing leakage current in a light-emitting diode (LED) pixel circuit, comprising: providing a second transistor configured to control a micro LED current according to a data voltage, the control terminal of the second transistor being coupled to a first node; providing a third transistor coupled between a first reference voltage and the first node, wherein the body of the third transistor is coupled to the first reference voltage; and providing a first capacitor coupled between a second node and the first node; wherein during a data writing phase, the first node has the first reference voltage and the second node has the data voltage; during a light-emitting phase, the second node has a second reference voltage and the first node has a voltage consisting of the first reference voltage plus at least a portion of the second reference voltage minus the data voltage.

12. The method as described in claim 11, wherein the body electrode of the second transistor is coupled to an operating voltage.

13. The method as described in claim 11, wherein the bulk of the third transistor is a wafer substrate.

14. The method of claim 11 further comprises: providing a first transistor, a first terminal of the first transistor being coupled to a second power supply voltage via a micro-light-emitting diode, and a second terminal of the first transistor being coupled to the second transistor.

15. The method as described in claim 14, wherein the first reference voltage and the second reference voltage are between a first power supply voltage and the second power supply voltage, and the first reference voltage is greater than the second reference voltage.

16. The method as described in claim 11, wherein the first reference voltage is selected based on an average range of the micro-light-emitting diode current controlled by the second transistor.

17. The method as described in claim 11, wherein the second reference voltage is selected from 0.5 to 1.5 times the data voltage.