Memory device and memory cell

Abstract

A memory device may include a memory cell array including a plurality of memory cells, and a controller connected to the memory cell array. A first memory cell among the plurality of memory cells includes a first inverter including a first PMOS transistor, and a first NMOS transistor connected between the first PMOS transistor and a ground, a second inverter including a second NMOS transistor, and a second PMOS transistor connected between the second NMOS transistor and a power supply voltage, a write buffer that generates first data, based on a first enable signal output from the first inverter and a second enable signal output from the second inverter, and a latch circuit that stores the first data. In a write operation on the first memory cell, the controller is configured to apply a first column selection signal to a source-drain electrode of the first PMOS transistor.

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