Receiving device and data jitter suppression method thereof

Abstract

The invention provides a receiving device and a data jitter suppression method thereof. The receiving device can be applied to a three-dimensional NAND flash memory with high capacity and high performance. The receiving device includes an input buffer and an analog feedforward equalizer (AFFE). The input buffer receives an original data signal from an external chip to generate a gained data signal. An input terminal of the AFFE is coupled to an output terminal of the input buffer to receive the gained data signal. The AFFE adjusts the inverter strength of the gained data signal to suppress data dependent jitter.

Description

[Technical Field]

[0001] This invention relates to a memory device, and more particularly to a receiving device and a method for suppressing data jitter therein. [Previous Technology]

[0002] The bulk circuitry of high-capacity and high-performance 3D NAND flash memory is continuously evolving. To overcome the challenges of size reduction, the NAND flash memory industry has transitioned from planar architecture to 3D architecture. The storage capacity of 3D vertical NAND flash memory has been increasing over the past decade to meet the needs of various industries, including mobile and data centers. The increase in the number of stacked word-line (WL) layers has played a key role in achieving higher storage capacity or bit density. This paradigm shift allows for increased storage density through the vertical stacking of storage cells, rather than solely relying on cell miniaturization. Charge-trap technology uses continuous silicon nitride layers as storage nodes (SNs). Compared to floating gate technology, charge-trap technology is widely used in 3D NAND flash memory arrays due to its simpler manufacturing process and higher vertical scaling capabilities.

[0003] Interface circuits in memory volume circuits can transmit data between internal circuits and external chips. Generally, due to the limited driving strength of Complementary Metal-Oxide-Semiconductor (CMOS) circuits, high-speed data DQ may experience data-dependent jitter (DDJ). Data-dependent jitter reduces eye width, thereby affecting the data valid window. How to suppress high-speed data DQ jitter to maintain the data valid window has become one of the many technical issues in the field of 3D NAND flash memory. [Summary of the Invention]

[0004] The present invention provides a receiving device and a data jitter suppression method thereof to suppress data dependent jitter (DDJ) of high-speed data signals.

[0005] In one embodiment of the present invention, the receiving device includes an input buffer and an analog feedforward equalizer (AFFE). The input buffer receives the raw data signal from an external chip to generate a gained data signal. The input of the analog feedforward equalizer is coupled to the output of the input buffer to receive the gained data signal. The analog feedforward equalizer adjusts the inverter strength of the gained data signal to suppress data correlation jitter.

[0006] In one embodiment of the present invention, the above-described data jitter suppression method includes: receiving a raw data signal from an external chip by an input buffer of a receiving device to generate a gained data signal; and adjusting the inverter strength of the gained data signal by an analog feedforward equalizer of the receiving device to suppress data-related jitter.

[0007] Based on the above, the receiving device described in the embodiments of the present invention is configured with an analog feedforward equalizer to compensate for edge latency in different modes. The inverter strength of the analog feedforward equalizer can be set / adjusted based on the actual application. For example, when the frequency of the original data signal is high, the user can increase the inverter strength of the analog feedforward equalizer. Conversely, when the frequency of the original data signal is low, the user can decrease the inverter strength of the analog feedforward equalizer. Therefore, the receiving device can suppress data correlation jitter in the gained data signal.

[0008] In order to make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are given in conjunction with the accompanying drawings.

Implementation Method

[0009] The term "coupled (or connected)" as used throughout the entire specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout the entire specification (including the claims) are used to name elements or distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of elements, nor to limit the order of elements. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0010] FIG1 is a circuit block diagram of a non-volatile memory volumetric circuit 100 according to an embodiment of the present invention. The non-volatile memory volumetric circuit 100 includes a memory cell array 110 and a control circuit 120. The control circuit 120 is coupled to the memory cell array 110. The memory cell array 110 shown in FIG1 can be one of many embodiments of the memory cell array 110 shown in FIG2, and the control circuit 120 shown in FIG2 can be one of many embodiments of the control circuit 120 shown in FIG1. ​​Depending on the design, in some embodiments, the control circuit 120 can be implemented as a hardware circuit. In other embodiments, the control circuit 120 can be implemented as a combination of hardware, firmware, and software (i.e., programs).

[0011] In hardware form, the control circuit 120 described above can be implemented as logic circuitry on an integrated circuit. For example, the functions of the control circuit 120 can be implemented in various logic blocks, modules, and circuits within one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), and / or other processing units. The functions of the control circuit 120 can be implemented as hardware circuitry, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages ​​(e.g., Verilog HDL or VHDL) or other suitable programming languages.

[0012] In software and / or firmware form, the functions of the control circuit 120 described above can be implemented as programming codes. For example, the control circuit 120 can be implemented using general programming languages ​​(such as C, C++, or assembly languages) or other suitable programming languages. The programming code can be recorded / stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or storage devices. An electronic device (e.g., a CPU, hardware controller, microcontroller, hardware processor, or microprocessor) can read and execute the programming code from the non-transitory machine-readable storage medium to implement the functions of the control circuit 120.

[0013] Figure 1 shows the equivalent circuit of a three-dimensional (3D) inverse gate NAND flash memory integrated circuit. The memory cell array 110 has multiple memory cells (e.g., memory cell M'). The multiple memory cells in the memory cell array 110 shown in Figure 1 are arranged in a 3D manner in the XYZ coordinate system. However, this does not mean that the circuit of the memory cell array 110 is limited to a 3D manner. In one example, the memory cell array 110 can be divided into four sub-blocks Sub0, Sub1, Sub2, and Sub3. The control circuit 120 can independently control the operation of each sub-block (e.g., sub-block Sub0).

[0014] Each memory cell string shown in Figure 1 (e.g., memory cell string 101, 102, or 103) includes multiple memory cells (e.g., memory cells M') connected in series along the Z direction. The memory cell array 110 includes multiple word lines (WL), such as the word lines WL1, ..., WLi, WLi+1, ..., WLn-1, WLn, ..., WLm shown in Figure 1. One word line (e.g., word line WLn) may correspond to one layer in the XY plane. Each of the word lines WL1 to WLm is coupled to multiple memory cells in a corresponding row of these memory cells. Multiple memory cells in each memory cell string (e.g., memory cell string 101) correspond to one word line (e.g., word line WLi+1). Memory cell M can be configured as a string select transistor coupled to a string select line (SSL, such as string select lines SSL0, SSL1, SSL2, and SSL3), and another memory cell can be configured as a ground select transistor coupled to a ground select line (GSL). The string select transistor and the ground select transistor are located on opposite sides of each memory cell string (e.g., memory cell string 101). In this example, multiple memory cell strings (e.g., memory cell strings 101, 102, etc.) coupled to the same string select line (e.g., string select line SSL0) on the same plane (e.g., the plane defined by the X and Z directions) can be defined as a subblock (e.g., subblock Sub0).

[0015] Each of the multiple bit lines (BLs) is coupled to multiple memory cells in a corresponding column of these memory cells. That is, each memory cell string (e.g., memory cell string 101, 102, or 103) is connected to the corresponding bit line (e.g., bit line BL1, BLn, or BLm) via a corresponding string select transistor on a string select line (e.g., string select line SSL0). Memory cell strings (e.g., memory cell string 101) in the same column of different sub-blocks (e.g., sub-blocks Sub0, Sub1, etc.) along the Y direction are connected to the corresponding bit line (e.g., bit line BL1). The string select line (e.g., string select line SSL0) can be a conductive line or conductive layer formed above the topmost word line layer (e.g., word line WL1). Each memory cell string (e.g., memory cell string 101, 102, or 103) can be connected to the same common source line (CSL) via a corresponding ground select transistor on the ground select line GSL. The ground select line GSL can be a conductive line or conductive layer formed below the bottommost character line layer (e.g., character line WLm). The common source line CSL can be a conductive layer formed above the substrate of the non-volatile memory volumetric circuit 100. The serial select lines (e.g., serial select lines SSL0~SSL3) in the memory cell array 110 can be on the same conductive layer, but divided into independent lines. Each independent line (serial select line) can independently control the operation of the corresponding sub-block (e.g., sub-blocks Sub0, Sub1, etc.) in the memory cell array 110.

[0016] In one example, in a single-level cell (SLC) configuration, multiple memory cells (including memory cell M') coupled to the same word line or word line layer (e.g., word line WLn) in a sub-region (e.g., sub-block Sub0) can be defined as a page. In another example, in a triple-level cell (TLC) configuration, multiple memory cells (including memory cell M') coupled to the same word line or word line layer (e.g., word line WLn) in a sub-region (e.g., sub-block Sub0) can be defined as three pages. In the TLC configuration, these three pages include a high page, a middle page, and a low page. Memory cells M' located on the same word line (e.g., word line WLn) are subjected to the same voltage. Each word line (e.g., word line WLn) can be connected to a driving circuit, such as an X-decoder (or scan driver).

[0017] In one example, one or more dummy lines or layers (not shown) may be provided between the string select lines (e.g., string select lines SSL0~SSL3) and the character line layer (e.g., character line WL1), and between the ground select line GSL and the bottommost character line layer (e.g., character line WLm). In another example, one or more dummy lines or layers (not shown) may be provided in the middle portion of each memory cell string (e.g., memory cell string 101, 102, or 103). The non-volatile memory volume circuit 100 also includes control circuitry 120 for implementing corresponding operations on the memory cell array 110.

[0018] FIG2 is a circuit block diagram of a non-volatile memory volume circuit 100 according to an embodiment of the present invention. The non-volatile memory volume circuit 100 shown in FIG2 can be referred to the relevant description in FIG1. ​​An external chip 11 sends commands to the non-volatile memory volume circuit 100 and receives and sends data to the non-volatile memory volume circuit 100. Based on the control of the external chip 11 (e.g., a memory controller), the non-volatile memory volume circuit 100 shown in FIG2 provides data access functions to the external chip 11. In the embodiment shown in FIG2, the control circuit 120 includes an interface circuit 121, a command decoder 122, an address decoder 123, word line operation logic 124, bit line operation logic 125, a word line decoding circuit 126, a bit line decoding circuit 127, and a page buffer 128.

[0019] Command decoder 122 receives commands (e.g., programming commands, read mode commands, write mode commands, etc.) from external chip 11 via interface circuit 121. Upon receiving a command, command decoder 122 decodes the command to perform the corresponding operation. For example, command decoder 122 transmits the array address to address decoder 123 based on the command decoding result. Based on the control of command decoder 122, word line operation logic 124 notifies word line decoding circuit 126 of the word line to be selected (WL) and the word line to be deselected. Address decoder 123 decodes the array address and transmits the address decoding result to word line decoding circuit 126 and bit line decoding circuit 127. Based on the control of address decoder 123 and word line operation logic 124, word line decoding circuit 126 selects the corresponding word line of memory cell array 110.

[0020] Based on the control of the command decoder 122, the bit-line operation logic 125 notifies the bit-line decoding circuit 127 of the bit-line to be selected (BL) and the bit-line to be deselected. Based on the control of the address decoder 123 and the bit-line operation logic 125, the bit-line decoding circuit 127 transmits and receives data to and from the external chip 11 through the interface circuit 121. The bit-line decoding circuit 127 selects the corresponding bit-line of the memory cell array 110 based on the control of the bit-line operation logic 125. The page buffer 128 includes a sense amplifier to sense the signal of the bit-line to generate corresponding data.

[0021] FIG3 is a circuit block diagram of a receiving device 400 according to an embodiment. Depending on the application, the receiving device 400 can be arranged in any functional circuit of any integrated circuit. For example, the receiving device 400 can be arranged within the interface circuit 121 of the non-volatile memory volumetric circuit 100 shown in FIG2. The receiving device 400 receives a raw data signal Din4 from an external chip (e.g., external chip 11 shown in FIG2) to generate a logic-processed data signal Dout4 for subsequent circuitry 40. The receiving device 400 shown in FIG3 includes an input buffer 410 and logic circuitry 420. The input buffer 410 receives the raw data signal Din4 from the external chip to generate a gain-enhanced data signal D41. The input of the logic circuitry 420 is coupled to the output of the input buffer 410 to receive the gain-enhanced data signal D41. The logic circuitry 420 generates the logic-processed data signal Dout4 based on the gain-enhanced data signal D41 for subsequent circuitry 40.

[0022] Figure 4 is a waveform diagram of the data signal of the receiving device 400 according to one embodiment. Generally, due to the limited driving strength of complementary metal-oxide-semiconductor (CMOS) circuits, the logic-processed data signal Dout4 may experience data-dependent jitter (DDJ). Data-dependent jitter reduces eye width, thereby affecting the data valid window.

[0023] FIG5 is a circuit block diagram of a receiving device 600 according to an embodiment of the present invention. Based on practical design and application, the receiving device 600 shown in FIG5 can be arranged in any functional circuit of any integrated circuit. For example, the receiving device 600 can be arranged in the interface circuit 121 of the non-volatile memory volumetric circuit 100 shown in FIG2, or in other circuits. The receiving device 600 receives the raw data signal Din6 from an external chip (e.g., external chip 11 shown in FIG2) to generate a logic-processed data signal Dout6 to the subsequent circuit 60. The receiving device 600 shown in FIG5 includes an input buffer 610, an analog feedforward equalizer (AFFE) 620, and logic circuit 630. The input of the analog feedforward equalizer 620 is coupled to the output of the input buffer 610 to receive the gain-enhanced data signal D61. The input of logic circuit 630 is coupled to the output of analog feedforward equalizer 620 to receive the delayed-adjusted data signal D62. A typical feedforward equalizer (FFE) focuses on voltage domain equalization and requires a clock signal. An analog feedforward equalizer focuses on time domain equalization and does not require a clock signal.

[0024] FIG6 is a schematic flowchart of a data jitter suppression method for a receiving device according to an embodiment of the present invention. Referring to FIG5 and FIG6, in step S710, the input buffer 610 receives the raw data signal Din6 from an external chip to generate a gained data signal D61. In step S720, the analog feedforward equalizer 620 adjusts the inverter strength of the gained data signal D61 to suppress the data dependent jitter (DDJ) of the gained data signal D61, thereby generating a delayed adjusted data signal D62. The logic circuit 630 generates a logic-processed data signal Dout6 based on the delayed adjusted data signal D62, and provides the logic-processed data signal Dout6 to the subsequent circuit 60.

[0025] Figure 7 is a waveform diagram of the data signal of the receiving device 600 according to one embodiment. The receiving device 600 is configured with an analog feedforward equalizer 620 to compensate for edge latency in different modes. The inverter strength of the analog feedforward equalizer 620 can be set / adjusted based on the actual application. For example, when the frequency of the original data signal Din6 is high, the user can increase the inverter strength of the analog feedforward equalizer 620. Conversely, when the frequency of the original data signal Din6 is low, the user can decrease the inverter strength of the analog feedforward equalizer 620. Therefore, the receiving device 600 can suppress data-related jitter in the logic-processed data signal Dout6.

[0026] FIG8 is a circuit block diagram of an analog feedforward equalizer 620 according to an embodiment of the present invention. The analog feedforward equalizer 620 shown in FIG8 can be one of many embodiments of the analog feedforward equalizer 620 shown in FIG5. The original data signal Din6, the gained data signal D61, the delayed adjustment data signal D62, the input buffer 610, the analog feedforward equalizer 620, and the logic circuit 630 shown in FIG8 can be referred to the relevant description in FIG5, and therefore will not be repeated here. In the embodiment shown in FIG8, the analog feedforward equalizer 620 includes an inverter 621. The input and output terminals of the inverter 621 are both coupled to the same transmission path between the output terminal of the input buffer 610 and the input terminal of the logic circuit 630, as shown in FIG8. The signal output by the output terminal of the inverter 621 is the inverted signal of the gained data signal D61. It should be noted that the driving force of the output terminal of the inverter 621 is weaker than that of the output terminal of the input buffer 610. Therefore, the output terminal of the inverter 621 will not change the logic state of the output terminal of the input buffer 610, but it can suppress the data correlation jitter of the gain data signal D61.

[0027] FIG9 is a circuit block diagram of an inverter 621 according to an embodiment of the present invention. The inverter 621 shown in FIG9 can be one of many embodiments of the inverter 621 shown in FIG8. The inverter 621 shown in FIG9 can be referred to the relevant description in FIG8, and therefore will not be repeated here. In the embodiment shown in FIG9, the inverter 621 includes an inverter circuit INV101. The input terminal of the inverter circuit INV101 is coupled to the input terminal of the inverter 621 to receive the gain data signal D61. The output terminal of the inverter circuit INV101 is coupled to the output terminal of the inverter 621. The driving force of the output terminal of the inverter circuit INV101 is weaker than the driving force of the output terminal of the input buffer 610. Therefore, the output terminal of the inverter circuit INV101 does not change the logic state of the output terminal of the input buffer 610, but can suppress the data correlation jitter of the gain data signal D61.

[0028] This embodiment does not limit the specific implementation of the inverter circuit INV101. For example, FIG10 is a circuit block diagram of the inverter circuit INV101 according to an embodiment of the present invention. The inverter circuit INV101 shown in FIG10 can be one of many implementation examples of the inverter circuit INV101 shown in FIG9. The inverter circuit INV101 shown in FIG10 can be referred to the relevant description in FIG9, so it will not be described again here. In the embodiment shown in FIG10, the inverter circuit INV101 includes an inverter 1110, a power supply current adjustment circuit 1120, and a power supply current adjustment circuit 1130. The input terminal of the inverter 1110 is coupled to the input terminal of the inverter circuit INV101 to receive the gain data signal D61. The output terminal of the inverter 1110 is coupled to the output terminal of the inverter circuit INV101. The driving force of the output terminal of the inverter 1110 is weaker than the driving force of the output terminal of the input buffer 610.

[0029] The power supply current adjustment circuit 1120 is coupled to the power supply terminal of the inverter 1110 to provide an adjusted power supply current IP111. The symbol "VCCQ" in Figure 10 represents the power supply voltage. The power supply current adjustment circuit 1130 is coupled to the reference terminal of the inverter 1110 to draw the adjusted power supply current IP111. The power supply current adjustment circuits 1120 and 1130 are controlled by bias voltages VB111 and VB112. Based on the setting / adjustment of bias voltages VB111 and VB112, the power supply current adjustment circuits 1120 and 1130 can adjust the power supply current IP111, thereby adjusting the inverter strength of the inverter 1110. For example, when the frequency of the gain data signal D61 is high, the power supply current adjustment circuits 1120 and 1130 adaptively reduce the power supply current IP111 (the inverter strength of the inverter 1110 is increased). When the frequency of the gain data signal D61 is low, the power supply current adjustment circuits 1120 and 1130 adaptively increase the power supply current IP111 (the inverter strength of inverter 1110 is reduced).

[0030] FIG11 is a circuit block diagram of an inverter circuit INV101 according to another embodiment of the present invention. The inverter circuit INV101 shown in FIG11 can be one of many embodiments of the inverter circuit INV101 shown in FIG9. The inverter circuit INV101 shown in FIG11 can be referred to the relevant description in FIG9, and therefore will not be repeated here. In the embodiment shown in FIG11, the inverter circuit INV101 includes an inverter 1210, a power supply current adjustment circuit 1220, and a power supply current adjustment circuit 1230. The input terminal of the inverter 1210 is coupled to the input terminal of the inverter circuit INV101 to receive the gain data signal D61. The output terminal of the inverter 1210 is coupled to the output terminal of the inverter circuit INV101. The driving force of the output terminal of the inverter 1210 is weaker than the driving force of the output terminal of the input buffer 610.

[0031] A power supply current adjustment circuit 1220 is coupled to the power supply terminal of the inverter 1210 to provide an adjusted power supply current IP121. A power supply current adjustment circuit 1230 is coupled to the reference terminal of the inverter 1210 to draw the adjusted power supply current IP121. Power supply current adjustment circuits 1220 and 1230 are controlled by enable signals EN121_1, ..., EN121_n and EN122_1, ..., EN122_n. Based on the settings of enable signals EN121_1 to EN121_n and EN122_1 to EN122_n, power supply current adjustment circuits 1220 and 1230 can adjust the power supply current IP121, thereby adjusting the inverter strength of the inverter 1210.

[0032] In the embodiment shown in FIG11, the power supply current adjustment circuit 1220 includes n transistors MN12_1, ..., MN12_n, while the power supply current adjustment circuit 1230 includes n transistors MP12_1, ..., MP12_n. The sources of transistors MP12_1 to MP12_n receive the power supply voltage VCCQ. The drains of transistors MP12_1 to MP12_n are coupled to the power supply terminal of inverter 1210. The reference terminal of inverter 1210 is coupled to the drains of transistors MN12_1 to MN12_n. The sources of transistors MN12_1 to MN12_n receive a reference voltage (e.g., ground voltage or other fixed voltage). Enable signals EN121_1 to EN121_n can turn on (or off) some or all of transistors MP12_1 to MP12_n, while enable signals EN122_1 to EN122_n can turn on (or off) some or all of transistors MN12_1 to MN12_n. Therefore, based on the settings of enable signals EN121_1 to EN121_n and EN122_1 to EN122_n, power supply current adjustment circuits 1220 and 1230 can adjust the power supply current IP121, thereby adjusting the inverter strength of inverter 1210.

[0033] FIG12 is a circuit block diagram of an inverter 621 according to another embodiment of the present invention. The inverter 621 shown in FIG12 can be one of many embodiments of the inverter 621 shown in FIG8. The inverter 621 shown in FIG12 can be referred to the relevant description in FIG8, and therefore will not be repeated here. In the embodiment shown in FIG12, the inverter 621 includes a buffer BUF131 and an inverter circuit INV131. The input terminal of the buffer BUF131 is coupled to the input terminal of the inverter 621 to receive the gain data signal D61. The input terminal of the inverter circuit INV131 is coupled to the output terminal of the buffer BUF131. The output terminal of the inverter circuit INV131 is coupled to the output terminal of the inverter 621. The driving force of the output terminal of the inverter circuit INV131 is weaker than the driving force of the output terminal of the input buffer 610. Therefore, the output of the inverter circuit INV131 does not change the logic state of the output of the input buffer 610, but it can suppress the data correlation jitter of the gain data signal D61.

[0034] This embodiment does not limit the specific implementation of the buffer BUF131 and the inverting circuit INV131. For example, the inverting circuit INV131 shown in FIG12 can be deduced by referring to the relevant description of the inverting circuit INV111 shown in FIG10.

[0035] Figure 13 is a circuit block diagram of a buffer BUF 131 according to an embodiment of the present invention. The buffer BUF 131 shown in Figure 13 can be one of many embodiments of the buffer BUF 131 shown in Figure 12. In the embodiment shown in Figure 13, the buffer BUF 131 includes an inverter circuit INV 141 and an inverter circuit INV 142. The input terminal of the inverter circuit INV 141 is coupled to the input terminal of the buffer BUF 131 to receive the gain data signal D61. The input terminal of the inverter circuit INV 142 is coupled to the output terminal of the inverter circuit INV 141. The output terminal of the inverter circuit INV 142 is coupled to the output terminal of the buffer BUF 131, that is, coupled to the input terminal of the inverter circuit INV 131. This embodiment does not limit the specific implementation of the inverter circuits INV 141 and INV 142. For example, either the inverter circuits INV141 and INV142 shown in Figure 13 can be deduced by referring to the relevant description of the inverter circuit INV111 shown in Figure 10.

[0036] Figure 14 is a circuit block diagram of buffer BUF 131 according to another embodiment of the present invention. Buffer BUF 131 shown in Figure 14 can be one of many embodiments of buffer BUF 131 shown in Figure 12. In the embodiment shown in Figure 14, buffer BUF 131 includes resistor R141, inverting circuit INV 141, and inverting circuit INV 142. The inverting circuits INV 131, INV 141, and INV 142 shown in Figure 14 can be deduced from the relevant description in Figure 13, and therefore will not be repeated here. When bandwidth is insufficient, resistor R141 can be added to buffer BUF 131. In the embodiment shown in Figure 14, the first end of resistor R141 is coupled to the input terminal of inverting circuit INV 142. The second end of resistor R141 is coupled to the output terminal of inverting circuit INV 142.

[0037] FIG15 is a circuit block diagram of an analog feedforward equalizer 620 according to another embodiment of the present invention. The analog feedforward equalizer 620 shown in FIG15 can be one of many embodiments of the analog feedforward equalizer 620 shown in FIG5. The original data signal Din6, the gained data signal D61, the delayed-adjusted data signal D62, the input buffer 610, the analog feedforward equalizer 620, and the logic circuit 630 shown in FIG15 can be referred to the relevant description in FIG5, and therefore will not be repeated here. In the embodiment shown in FIG15, the analog feedforward equalizer 620 includes a logic circuit 622 and an inverter 623. The input terminal of the logic circuit 622 is coupled to the output terminal of the input buffer 610 to receive the gained data signal D61. The output terminal of the logic circuit 622 provides the delayed-adjusted data signal D62 to the logic circuit 630. The input and output terminals of the inverter 623 are both coupled to the same transmission path between the output terminal of logic circuit 622 and the input terminal of logic circuit 630, as shown in Figure 15. The signal output by the inverter 623 is the inverted signal of the delayed-adjusted data signal D61. It should be noted that the driving force of the output terminal of the inverter 623 is weaker than that of the output terminal of logic circuit 622. Therefore, the output terminal of the inverter 623 does not change the logic state of the output terminal of logic circuit 622, but it can suppress the data correlation jitter of the gain data signal D61.

[0038] This embodiment does not limit the specific implementation of the inverter 623. For example, the inverter 623 shown in FIG15 can be deduced by analogy with the relevant description of the inverter 621 shown in FIG9. That is, the inverter 623 includes an inverter circuit (the driving force of the output terminal of this inverter circuit is weaker than the driving force of the output terminal of the logic circuit 622), wherein the input terminal of this inverter circuit is coupled to the input terminal of the inverter 623, and the output terminal of this inverter circuit is coupled to the output terminal of the inverter 623. As another example, the inverter 623 shown in FIG15 can be deduced by analogy with the relevant description of the inverter 621 shown in FIG12.

[0039] FIG16 is a circuit block diagram of an analog feedforward equalizer 620 according to another embodiment of the present invention. The analog feedforward equalizer 620 shown in FIG16 can be one of many embodiments of the analog feedforward equalizer 620 shown in FIG5. The original data signal Din6, the gained data signal D61, the delayed-adjusted data signal D62, the input buffer 610, the analog feedforward equalizer 620, and the logic circuit 630 shown in FIG16 can be referred to the relevant description in FIG5, and therefore will not be repeated here. In the embodiment shown in FIG16, the analog feedforward equalizer 620 includes a logic circuit 624 and an inverter 625. The input terminal of the logic circuit 624 is coupled to the output terminal of the input buffer 610 to receive the gained data signal D61. The output terminal of the logic circuit 622 provides the delayed-adjusted data signal D62 to the logic circuit 630.

[0040] The input terminal of the inverter 625 is coupled to the input terminal of the logic circuit 624. The output terminal of the inverter 625 is coupled to the output terminal of the logic circuit 624. The signal output by the output terminal of the inverter 623 is the inverted signal of the delayed-adjusted data signal D61. It should be noted that the driving force of the output terminal of the inverter 625 is weaker than the driving force of the output terminal of the logic circuit 624. Therefore, the output terminal of the inverter 625 does not change the logic state of the output terminal of the logic circuit 624, but it can suppress the data correlation jitter of the gain data signal D61.

[0041] This embodiment does not limit the specific implementation of the inverter 625. For example, the inverter 625 shown in FIG16 can be deduced by analogy with the relevant description of the inverter 621 shown in FIG9. That is, the inverter 625 includes an inverter circuit (the driving force of the output terminal of this inverter circuit is weaker than the driving force of the output terminal of the logic circuit 624), wherein the input terminal of this inverter circuit is coupled to the input terminal of the inverter 625, and the output terminal of this inverter circuit is coupled to the output terminal of the inverter 625. As another example, the inverter 625 shown in FIG16 can be deduced by analogy with the relevant description of the inverter 621 shown in FIG12.

[0042] In summary, the receiving device 600 is equipped with an analog feedforward equalizer 620 to compensate for edge latency in different modes. The inverter strength of the analog feedforward equalizer 620 can be set / adjusted based on the actual application. For example, when the frequency of the original data signal Din6 is high, the user can increase the inverter strength of the analog feedforward equalizer 620. Conversely, when the frequency of the original data signal Din6 is low, the user can decrease the inverter strength of the analog feedforward equalizer 620. Therefore, the receiving device 600 can suppress data correlation jitter in the amplified data signal D61.

[0043] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0044] Figure 1 is a circuit block diagram of a non-volatile memory volumetric circuit according to an embodiment of the present invention. Figure 2 is a circuit block diagram of a non-volatile memory volumetric circuit according to an embodiment of the present invention. Figure 3 is a circuit block diagram of a receiving device according to an embodiment. Figure 4 is a waveform diagram of a data signal of a receiving device according to an embodiment. Figure 5 is a circuit block diagram of a receiving device according to an embodiment of the present invention. Figure 6 is a flowchart of a data jitter suppression method of a receiving device according to an embodiment of the present invention. Figure 7 is a waveform diagram of a data signal of a receiving device according to an embodiment. Figure 8 is a circuit block diagram of an analog feedforward equalizer according to an embodiment of the present invention. Figure 9 is a circuit block diagram of an inverting device according to an embodiment of the present invention. Figure 10 is a circuit block diagram of an inverting circuit according to an embodiment of the present invention. Figure 11 is a circuit block diagram of an inverting circuit according to another embodiment of the present invention. Figure 12 is a circuit block diagram of an inverting device according to another embodiment of the present invention. Figure 13 is a circuit block diagram of a buffer according to one embodiment of the present invention. Figure 14 is a circuit block diagram of a buffer according to another embodiment of the present invention. Figure 15 is a circuit block diagram of an analog feedforward equalizer according to another embodiment of the present invention. Figure 16 is a circuit block diagram of an analog feedforward equalizer according to yet another embodiment of the present invention.

Claims

1. A receiving device, comprising: An input buffer receives a raw data signal from an external chip to generate a gained data signal; an analog feedforward equalizer, wherein an input of the analog feedforward equalizer is coupled to an output of the input buffer to receive the gained data signal, and the analog feedforward equalizer adjusts the inverter strength of the gained data signal to suppress data correlation jitter; and a first logic circuit, wherein an input of the first logic circuit is coupled to an output of the analog feedforward equalizer to receive a delayed adjusted data signal, and the first logic circuit provides a logic-processed data signal to a subsequent circuit of the receiving device, wherein the analog feedforward equalizer includes: An inverting device, wherein an input terminal and an output terminal of the inverting device are both coupled to the same transmission path between the output terminal of the input buffer and the input terminal of the first logic circuit, the signal output by the output terminal of the inverting device is an inverted signal of the gain data signal, and the driving force of the output terminal of the inverting device is weaker than the driving force of the output terminal of the input buffer.

2. The receiving apparatus as claimed in claim 1, wherein the inverting device comprises: An inverting circuit, wherein an input terminal of the inverting circuit is coupled to the input terminal of the inverting device, an output terminal of the inverting circuit is coupled to the output terminal of the inverting device, and the driving force of the output terminal of the inverting circuit is weaker than the driving force of the output terminal of the input buffer.

3. The receiving device as claimed in claim 2, wherein the inverting circuit comprises: An inverter, wherein an input terminal of the inverter is coupled to the input terminal of the inverting circuit, an output terminal of the inverter is coupled to the output terminal of the inverting circuit, and the driving force of the output terminal of the inverter is weaker than the driving force of the output terminal of the input buffer; a first power supply current adjustment circuit is coupled to a power supply terminal of the inverter to provide a first adjusted power supply current; And a second power supply current adjustment circuit, coupled to a reference terminal of the inverter to draw a second adjusted power supply current.

4. The receiving apparatus as claimed in claim 1, wherein the inverting device comprises: A buffer, wherein one input of the buffer is coupled to the input of the inverting device; And a first inverting circuit, wherein an input terminal of the first inverting circuit is coupled to an output terminal of the buffer, an output terminal of the first inverting circuit is coupled to the output terminal of the inverting device, and the driving force of the output terminal of the first inverting circuit is weaker than the driving force of the output terminal of the input buffer.

5. The receiving device as claimed in claim 4, wherein the buffer comprises: A second inverter circuit, wherein an input terminal of the second inverter circuit is coupled to the input terminal of the buffer; And a third inverting circuit, wherein an input terminal of the third inverting circuit is coupled to an output terminal of the second inverting circuit, and an output terminal of the third inverting circuit is coupled to the output terminal of the buffer.

6. The receiving device as claimed in claim 5, wherein the buffer further comprises: A resistor, wherein a first end of the resistor is coupled to the input terminal of the third inverting circuit, and a second end of the resistor is coupled to the output terminal of the third inverting circuit.

7. A receiving device, comprising: An input buffer receives a raw data signal from an external chip to generate a gained data signal; an analog feedforward equalizer, wherein an input of the analog feedforward equalizer is coupled to an output of the input buffer to receive the gained data signal, and the analog feedforward equalizer adjusts the inverter strength of the gained data signal to suppress data correlation jitter; and a first logic circuit, wherein an input of the first logic circuit is coupled to an output of the analog feedforward equalizer to receive a delayed adjusted data signal, and the first logic circuit provides a logic-processed data signal to a subsequent circuit of the receiving device, wherein the analog feedforward equalizer includes: A second logic circuit, wherein an input of the second logic circuit is coupled to the output of the input buffer to receive the gain-adjusted data signal, and an output of the second logic circuit provides the delay-adjusted data signal to the first logic circuit; and an inverter, wherein an input and an output of the inverter are both coupled to the same transmission path between the output of the second logic circuit and the input of the first logic circuit, the signal output by the output of the inverter is an inverted signal of the delay-adjusted data signal, and the driving force of the output of the inverter is weaker than the driving force of the output of the second logic circuit.

8. The receiving apparatus as claimed in claim 7, wherein the inverting device comprises: An inverting circuit, wherein an input terminal of the inverting circuit is coupled to the input terminal of the inverting device, an output terminal of the inverting circuit is coupled to the output terminal of the inverting device, and the driving force of the output terminal of the inverting circuit is weaker than the driving force of the output terminal of the second logic circuit.

9. A receiving device, comprising: An input buffer receives a raw data signal from an external chip to generate a gained data signal; an analog feedforward equalizer, wherein an input of the analog feedforward equalizer is coupled to an output of the input buffer to receive the gained data signal, and the analog feedforward equalizer adjusts the inverter strength of the gained data signal to suppress data correlation jitter; and a first logic circuit, wherein an input of the first logic circuit is coupled to an output of the analog feedforward equalizer to receive a delayed adjusted data signal, and the first logic circuit provides a logic-processed data signal to a subsequent circuit of the receiving device, wherein the analog feedforward equalizer includes: A second logic circuit, wherein an input of the second logic circuit is coupled to the output of the input buffer to receive the gain-adjusted data signal, and an output of the second logic circuit provides the delay-adjusted data signal to the first logic circuit; and an inverter, wherein an input of the inverter is coupled to the input of the second logic circuit, an output of the inverter is coupled to the output of the second logic circuit, and the driving force of the output of the inverter is weaker than the driving force of the output of the second logic circuit.

10. The receiving apparatus as claimed in claim 9, wherein the inverting device comprises: An inverting circuit, wherein an input terminal of the inverting circuit is coupled to the input terminal of the inverting device, an output terminal of the inverting circuit is coupled to the output terminal of the inverting device, and the driving force of the output terminal of the inverting circuit is weaker than the driving force of the output terminal of the second logic circuit.

11. A method for suppressing data jitter in a receiving device, comprising: The receiving device receives a raw data signal from an external chip via an input buffer to generate a gain-up data signal; An analog feedforward equalizer of the receiving device adjusts the strength of an inverter in the gained data signal to suppress data correlation jitter, wherein an input of the analog feedforward equalizer is coupled to an output of the input buffer to receive the gained data signal; and a first logic circuit of the receiving device provides a logic-processed data signal to a subsequent circuit of the receiving device, wherein an input of the first logic circuit is coupled to an output of the analog feedforward equalizer to receive a delay-adjusted data signal, wherein the analog feedforward equalizer includes an inverter, an input and an output of the inverter are both coupled to the same transmission path between the output of the input buffer and the input of the first logic circuit, the signal output by the output of the inverter is an inverted signal of the gained data signal, and the driving force of the output of the inverter is weaker than the driving force of the output of the input buffer.

12. The data jitter suppression method as claimed in claim 11, wherein the inverting device includes an inverting circuit, an input terminal of the inverting circuit is coupled to the input terminal of the inverting device, an output terminal of the inverting circuit is coupled to the output terminal of the inverting device, and the driving force of the output terminal of the inverting circuit is weaker than the driving force of the output terminal of the input buffer.

13. The data jitter suppression method as claimed in claim 11, wherein the inverting device includes a buffer and an inverting circuit, an input terminal of the buffer is coupled to the input terminal of the inverting device, an input terminal of the inverting circuit is coupled to an output terminal of the buffer, an output terminal of the inverting circuit is coupled to the output terminal of the inverting device, and the driving force of the output terminal of the inverting circuit is weaker than the driving force of the output terminal of the input buffer.

14. A method for suppressing data jitter in a receiving device, comprising: The receiving device receives a raw data signal from an external chip via an input buffer to generate a gain-up data signal; An inverter strength of the gained data signal is adjusted by an analog feedforward equalizer of the receiving device to suppress data correlation jitter, wherein an input of the analog feedforward equalizer is coupled to an output of the input buffer to receive the gained data signal; A first logic circuit of the receiving device provides a logic-processed data signal to a subsequent circuit of the receiving device, wherein an input of the first logic circuit is coupled to an output of the analog feedforward equalizer to receive a delayed-adjusted data signal; and an output of a second logic circuit of the analog feedforward equalizer provides the delayed-adjusted data signal to the first logic circuit, wherein an input of the second logic circuit is coupled to the output of the input buffer to receive the gained data signal, an input and an output of an inverting device of the analog feedforward equalizer are both coupled to the same transmission path between the output of the second logic circuit and the input of the first logic circuit, the signal output by the output of the inverting device is an inverted signal of the delayed-adjusted data signal, and the driving force of the output of the inverting device is weaker than the driving force of the output of the second logic circuit.

15. A method for suppressing data jitter in a receiving device, comprising: The receiving device receives a raw data signal from an external chip via an input buffer to generate a gain-up data signal; An inverter strength of the gained data signal is adjusted by an analog feedforward equalizer of the receiving device to suppress data correlation jitter, wherein an input of the analog feedforward equalizer is coupled to an output of the input buffer to receive the gained data signal; A first logic circuit of the receiving device provides a logic-processed data signal to a subsequent circuit of the receiving device, wherein an input of the first logic circuit is coupled to an output of the analog feedforward equalizer to receive a delayed data signal; and an output of a second logic circuit of the analog feedforward equalizer provides the delayed data signal to the first logic circuit, wherein an input of the second logic circuit is coupled to the output of the input buffer to receive the gained data signal, an input of an inverting device of the analog feedforward equalizer is coupled to the input of the second logic circuit, an output of the inverting device is coupled to the output of the second logic circuit, and the driving force of the output of the inverting device is weaker than the driving force of the output of the second logic circuit.

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