Clock transmission device and operation method thereof

Abstract

The invention provides a clock transmission device and an operation method thereof. The clock transmission device may be applied to a three-dimensional NAND flash memory with high capacity and high performance. The clock transmission device includes a clock transmission circuit and a jitter suppression circuit. The clock transmission circuit generates an output clock based on an input clock. The jitter suppression circuit supplies a power current to the clock transmission circuit based on a power voltage. The jitter suppression circuit adaptively adjusts the power current in response to a power supply noise of the power voltage to suppress the power noise induced jitter of the output clock.

Description

[Technical Field]

[0001] This invention relates to a memory device, and more particularly to a clock transmission device and its operating method. [Previous Technology]

[0002] The bulk circuitry of high-capacity and high-performance 3D NAND flash memory is continuously evolving. To overcome the challenges of size reduction, the NAND flash memory industry has transitioned from planar architecture to 3D architecture. The storage capacity of 3D vertical NAND flash memory has been increasing over the past decade to meet the needs of various industries, including mobile and data centers. The increase in the number of stacked word-line (WL) layers has played a key role in achieving higher storage capacity or bit density. This paradigm shift allows for increased storage density through the vertical stacking of storage cells, rather than solely relying on cell miniaturization. Charge-trap technology uses continuous silicon nitride layers as storage nodes (SNs). Compared to floating gate technology, charge-trap technology is widely used in 3D NAND flash memory arrays due to its simpler manufacturing process and higher vertical scaling capabilities.

[0003] Interface circuits in memory volume circuits can transmit data between internal and external circuits. However, power supply noise will cause jitter on the data DQ path and the strobe clock DQS path. If the data DQ and the strobe clock DQS are matched, the power supply noise jitter on the DQ and DQS paths is the same, so the strobe clock DQS can strobe the eye diagram center of the data DQ. Based on this, the data valid window is maintained.

[0004] The Open NAND Flash Interface (ONFI) version 5.1 specification provides unparalleled DQ and DQS options, allowing the data DQ and strobe clock DQS to no longer track each other. Because the strobe clock DQS path (e.g., clock tree distribution) is relatively long, it is more susceptible to power noise-induced jitter (PNIJ). How to eliminate power noise-induced jitter in the strobe clock DQS to maintain the data validity window under significant power noise has become one of the many technical challenges in the 3D NAND flash memory field. [Summary of the Invention]

[0005] The present invention provides a clock transmission device and its operation method to suppress power noise induced jitter (PNIJ) of the output clock.

[0006] In one embodiment of the present invention, the clock transmission device described above includes a clock transmission circuit and a jitter suppression circuit. The clock transmission circuit generates at least one output clock based on an input clock. The jitter suppression circuit supplies power current to the clock transmission circuit based on a power supply voltage. The jitter suppression circuit adaptively adjusts the power supply current in response to power supply noise of the power supply voltage to suppress jitter caused by power supply noise in the at least one output clock.

[0007] In one embodiment of the present invention, the above-described operation method includes: a clock transmission circuit of a clock transmission device generating at least one output clock based on an input clock; a jitter suppression circuit of a clock transmission device supplying a power supply current to the clock transmission circuit based on a power supply voltage; and the jitter suppression circuit adaptively adjusting the power supply current in response to power supply noise of the power supply voltage to suppress jitter caused by power supply noise of the at least one output clock.

[0008] Based on the above, the jitter suppression circuit described in the embodiments of the present invention can detect power supply noise components of the power supply voltage and dynamically adjust the power supply current of the clock transmission circuit based on the power supply noise components. For example, when power supply noise causes the power supply voltage to rise, the jitter suppression circuit adaptively adjusts the power supply current of the clock transmission circuit. When power supply noise causes the power supply voltage to fall, the jitter suppression circuit adaptively increases the power supply current of the clock transmission circuit. Therefore, the jitter suppression circuit can adaptively suppress jitter caused by power supply noise in the output clock of the clock transmission circuit in response to power supply noise in the power supply voltage.

[0009] In order to make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are given in conjunction with the accompanying drawings.

Implementation Method

[0010] The term "coupled (or connected)" as used throughout the entire specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout the entire specification (including the claims) are used to name elements or distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of elements, nor to limit the order of elements. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0011] FIG1 is a circuit block diagram of a non-volatile memory volumetric circuit 100 according to an embodiment of the present invention. The non-volatile memory volumetric circuit 100 includes a memory cell array 110 and a control circuit 120. The control circuit 120 is coupled to the memory cell array 110. The memory cell array 110 shown in FIG1 can be one of many embodiments of the memory cell array 110 shown in FIG2, and the control circuit 120 shown in FIG2 can be one of many embodiments of the control circuit 120 shown in FIG1. ​​Depending on the design, in some embodiments, the control circuit 120 can be implemented as a hardware circuit. In other embodiments, the control circuit 120 can be implemented as a combination of hardware, firmware, and software (i.e., programs).

[0012] In hardware form, the control circuit 120 described above can be implemented as logic circuitry on an integrated circuit. For example, the functions of the control circuit 120 can be implemented in various logic blocks, modules, and circuits within one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), and / or other processing units. The functions of the control circuit 120 can be implemented as hardware circuitry, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages ​​(e.g., Verilog HDL or VHDL) or other suitable programming languages.

[0013] In software and / or firmware form, the functions of the control circuit 120 described above can be implemented as programming codes. For example, the control circuit 120 can be implemented using general programming languages ​​(such as C, C++, or assembly languages) or other suitable programming languages. The programming code can be recorded / stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or storage devices. An electronic device (e.g., a CPU, hardware controller, microcontroller, hardware processor, or microprocessor) can read and execute the programming code from the non-transitory machine-readable storage medium to implement the functions of the control circuit 120.

[0014] Figure 1 shows the equivalent circuit of a three-dimensional (3D) inverse gate NAND flash memory integrated circuit. The memory cell array 110 has multiple memory cells (e.g., memory cell M'). The multiple memory cells in the memory cell array 110 shown in Figure 1 are arranged in a 3D manner in the XYZ coordinate system. However, this does not mean that the circuit of the memory cell array 110 is limited to a 3D manner. In one example, the memory cell array 110 can be divided into four sub-blocks Sub0, Sub1, Sub2, and Sub3. The control circuit 120 can independently control the operation of each sub-block (e.g., sub-block Sub0).

[0015] Each memory cell string (e.g., memory cell string 101, 102, or 103) shown in Figure 1 includes multiple memory cells (e.g., memory cells M') connected in series along the Z direction. The memory cell array 110 includes multiple word lines (WL), such as the word lines WL1, ..., WLi, WLi+1, ..., WLn-1, WLn, ..., WLm shown in Figure 1. One word line (e.g., word line WLn) may correspond to one layer in the XY plane. Each of the word lines WL1 to WLm is coupled to multiple memory cells in a corresponding row of these memory cells. Multiple memory cells in each memory cell string (e.g., memory cell string 101) correspond to one word line (e.g., word line WLi+1). Memory cell M can be configured as a string select transistor coupled to a string select line (SSL, such as string select lines SSL0, SSL1, SSL2, and SSL3), and another memory cell can be configured as a ground select transistor coupled to a ground select line (GSL). The string select transistor and the ground select transistor are located on opposite sides of each memory cell string (e.g., memory cell string 101). In this example, multiple memory cell strings (e.g., memory cell strings 101, 102, etc.) coupled to the same string select line (e.g., string select line SSL0) on the same plane (e.g., the plane defined by the X and Z directions) can be defined as a subblock (e.g., subblock Sub0).

[0016] Each of the multiple bit lines (BL) is coupled to multiple memory cells in a corresponding column of these memory cells. That is, each memory cell string (e.g., memory cell string 101, 102, or 103) is connected to the corresponding bit line (e.g., bit line BL1, BLn, or BLm) via a corresponding string select transistor on a string select line (e.g., string select line SSL0). Memory cell strings (e.g., memory cell string 101) in the same column of different sub-blocks (e.g., sub-blocks Sub0, Sub1, etc.) along the Y direction are connected to the corresponding bit line (e.g., bit line BL1). The string select line (e.g., string select line SSL0) can be a conductive line or conductive layer formed above the topmost word line layer (e.g., word line WL1). Each memory cell string (e.g., memory cell string 101, 102, or 103) can be connected to the same common source line (CSL) via a corresponding ground select transistor on the ground select line GSL. The ground select line GSL can be a conductive line or conductive layer formed below the bottommost character line layer (e.g., character line WLm). The common source line CSL can be a conductive layer formed above the substrate of the non-volatile memory volumetric circuit 100. The serial select lines (e.g., serial select lines SSL0~SSL3) in the memory cell array 110 can be on the same conductive layer, but divided into independent lines. Each independent line (serial select line) can independently control the operation of the corresponding sub-block (e.g., sub-blocks Sub0, Sub1, etc.) in the memory cell array 110.

[0017] In one example, in a single-level cell (SLC) configuration, multiple memory cells (including memory cell M') coupled to the same character line or character line layer (e.g., character line WLn) in a sub-region (e.g., sub-region Sub0) can be defined as a page. In another example, in a triple-level cell (TLC) configuration, multiple memory cells (including memory cell M') coupled to the same character line or character line layer (e.g., character line WLn) in a sub-region (e.g., sub-region Sub0) can be defined as three pages. In the TLC configuration, these three pages include a high page, a middle page, and a low page. Memory cells M' located on the same character line (e.g., character line WLn) are subjected to the same voltage. Each character line (e.g., character line WLn) can be connected to a driver circuit, such as an X-decoder (or scan driver).

[0018] In one example, one or more dummy lines or layers (not shown) may be provided between the string select lines (e.g., string select lines SSL0~SSL3) and the character line layers (e.g., character line WL1), and between the ground select line GSL and the bottommost character line layer (e.g., character line WLm). In another example, one or more dummy lines or layers (not shown) may be provided in the middle portion of each memory cell string (e.g., memory cell string 101, 102, or 103). The non-volatile memory volume circuit 100 also includes control circuitry 120 for implementing corresponding operations on the memory cell array 110.

[0019] FIG2 is a circuit block diagram of a non-volatile memory volume circuit 100 according to an embodiment of the present invention. The non-volatile memory volume circuit 100 shown in FIG2 can be referred to the relevant description in FIG1. ​​An external circuit 11 sends commands to the non-volatile memory volume circuit 100 and sends and receives data to the non-volatile memory volume circuit 100. Based on the control of the external circuit 11 (e.g., a memory controller), the non-volatile memory volume circuit 100 shown in FIG2 provides data access functions to the external circuit 11. In the embodiment shown in FIG2, the control circuit 120 includes an interface circuit 121, a command decoder 122, an address decoder 123, word line operation logic 124, bit line operation logic 125, a word line decoding circuit 126, a bit line decoding circuit 127, and a page buffer 128.

[0020] Command decoder 122 receives commands (e.g., programming commands, read mode commands, write mode commands, etc.) from external circuit 11 via interface circuit 121. Upon receiving a command, command decoder 122 decodes the command to perform the corresponding operation. For example, command decoder 122 transmits the array address to address decoder 123 based on the command decoding result. Based on the control of command decoder 122, word line operation logic 124 notifies word line decoding circuit 126 of the word line to be selected (WL) and the word line to be deselected. Address decoder 123 decodes the array address and transmits the address decoding result to word line decoding circuit 126 and bit line decoding circuit 127. Based on the control of address decoder 123 and word line operation logic 124, word line decoding circuit 126 selects the corresponding word line of memory cell array 110.

[0021] Based on the control of the command decoder 122, the bit-line operation logic 125 notifies the bit-line decoding circuit 127 of the bit-line to be selected (BL) and the bit-line to be deselected. Based on the control of the address decoder 123 and the bit-line operation logic 125, the bit-line decoding circuit 127 transmits and receives data to and from the external chip 11 through the interface circuit 121. The bit-line decoding circuit 127 selects the corresponding bit-line of the memory cell array 110 based on the control of the bit-line operation logic 125. The page buffer 128 includes a sense amplifier to sense the signal of the bit-line to generate corresponding data.

[0022] Figure 3 is a circuit block diagram of a clock transmission device 400 according to one embodiment. Based on practical applications, the clock transmission device 400 can be arranged in any functional circuit of any integrated circuit. For example, the clock transmission device 400 can be arranged within the interface circuit 121 of the non-volatile memory volumetric circuit 100 shown in Figure 2. The clock transmission device 400 shown in Figure 3 includes a clock transmission circuit CT41. The clock transmission circuit CT41 generates an output clock CKout41 based on the input clock CKin41 for the next stage circuit (not shown). The symbol "VCCQ" in Figure 3 represents the power supply voltage. Inevitably, the power supply voltage VCCQ may contain power supply noise. The power supply noise of the power supply voltage VCCQ will cause the output clock CKout41 to jitter, and such jitter is called power noise induced jitter (PNIJ).

[0023] Figure 4 is a circuit block diagram of a clock transmission device 500 according to an embodiment of the present invention. Based on practical design and application, the clock transmission device 500 shown in Figure 4 can be arranged in any functional circuit of any integrated circuit. For example, the clock transmission device 500 can be arranged in the interface circuit 121 of the non-volatile memory volumetric circuit 100 shown in Figure 2, or in other circuits. The clock transmission device 500 shown in Figure 4 includes a clock transmission circuit CT51 and a jitter suppression circuit JS51. The jitter suppression circuit JS51 is coupled to the power supply terminal of the clock transmission circuit CT51. The jitter suppression circuit JS51 can adaptively suppress power noise-induced jitter (PNIJ) of the output clock CKout51 in response to power noise of the power supply voltage VCCQ.

[0024] Figure 5 is a schematic flowchart of an operation method of a clock transmission device according to an embodiment of the present invention. Referring to Figures 4 and 5, in step S610, the jitter suppression circuit JS51 supplies power current IP51 to the clock transmission circuit CT51 based on the power supply voltage VCCQ. In step S620, the clock transmission circuit CT51 generates an output clock CKout51 based on the input clock CKin51 for the next stage circuit (not shown). In step S630, the jitter suppression circuit JS51 adaptively adjusts the power supply current IP51 in response to power supply noise in the power supply voltage VCCQ to suppress jitter caused by power supply noise in the output clock CKout51.

[0025] In summary, the jitter suppression circuit JS51 can detect power supply noise components of the power supply voltage VCCQ and dynamically adjust the power supply current IP51 of the clock transmission circuit CT51 based on these noise components. For example, when power supply noise in the power supply voltage VCCQ causes VCCQ to rise, the jitter suppression circuit JS51 adaptively decreases the power supply current IP51 of the clock transmission circuit CT51. When power supply noise in the power supply voltage VCCQ causes VCCQ to fall, the jitter suppression circuit JS51 adaptively increases the power supply current IP51 of the clock transmission circuit CT51. Therefore, the jitter suppression circuit JS51 can adaptively suppress jitter caused by power supply noise in the output clock CKout51 of the clock transmission circuit CT51 in response to power supply noise in the power supply voltage VCCQ.

[0026] In applications where the clock transmission device 500 is applied to the transmission path of the select signal DQS, the clock transmission device 500 can suppress jitter caused by power supply noise in the select signal DQS (output clock CKout51). Therefore, the select signal DQS can select the center of the data signal DQ, thereby maintaining the data valid window.

[0027] FIG6 is a circuit block diagram of a clock transmission device 700 according to another embodiment of the present invention. Based on practical design and application, the clock transmission device 700 shown in FIG6 can be arranged in any functional circuit of any integrated circuit. For example, the clock transmission device 700 can be arranged in the interface circuit 121 of the non-volatile memory volume circuit 100 shown in FIG2, or arranged in other circuits. The clock transmission device 700 shown in FIG6 includes a clock transmission circuit CT71 and a jitter suppression circuit JS71. The jitter suppression circuit JS71 is coupled to the power supply terminal and the reference terminal of the clock transmission circuit CT71. In the embodiment shown in FIG6, the clock transmission circuit CT71 includes multiple clock transmission paths (e.g., n clock transmission paths CT71_1, ..., CT71_n, where n is an integer). The jitter suppression circuit JS71 is coupled to the power supply terminal and the reference terminal of the clock transmission paths CT71_1 to CT71_n, as shown in FIG6.

[0028] The jitter suppression circuit JS71 supplies power current to the clock transmission circuit CT71 based on the power supply voltage VCCQ. For example, the jitter suppression circuit JS71 supplies power current IP71 to the clock transmission path CT71_1 based on the power supply voltage VCCQ. Similarly, the jitter suppression circuit JS71 supplies power current IP7n to the clock transmission path CT71_n based on the power supply voltage VCCQ. The clock transmission circuit CT71 generates different output clocks for the next stage circuit (not shown) based on multiple input clocks. For example, the clock transmission path CT71_1 generates the output clock CKout71 based on the input clock CKin71. Similarly, the clock transmission path CT71_n generates the output clock CKout7n based on the input clock CKin7n. Any of the clock transmission paths CT71_1 to CT71_n can be deduced by referring to the relevant description of the clock transmission circuit CT51 shown in Figure 4, and the jitter suppression circuit JS71 can be deduced by referring to the relevant description of the jitter suppression circuit JS51 shown in Figure 4, so it will not be described in detail.

[0029] FIG7 is a circuit block diagram of a clock transmission circuit CT51 according to an embodiment of the present invention. The clock transmission circuit CT51 shown in FIG7 can be one of many embodiments of the clock transmission circuit CT51 shown in FIG4. In the embodiment shown in FIG7, the clock transmission circuit CT51 includes a gain circuit 810 and a clock tree circuit 820. A jitter suppression circuit JS51 supplies a power supply current IP51 to the power supply terminal of the gain circuit 810 based on the power supply voltage VCCQ, and draws a power supply current IP51 from the reference terminal of the gain circuit 810. The gain circuit 810 gains the input clock CKin51 to generate a gained clock CK81. The jitter suppression circuit JS51 senses power supply noise of the power supply voltage VCCQ to adaptively adjust the power supply current IP51, thereby suppressing jitter caused by power supply noise through the gained clock CK81. The clock tree circuit 820 is coupled to the gain circuit 810 to receive the gained clock CK81. The clock tree circuit 820 generates the output clock CKout51 based on the gained clock CK81.

[0030] Figure 8 is a circuit block diagram of a jitter suppression circuit JS51 according to an embodiment of the present invention. The jitter suppression circuit JS51 shown in Figure 8 can be one of many embodiments of the jitter suppression circuit JS51 shown in Figure 4. The clock transmission circuit CT51 shown in Figure 8 can be referred to the relevant description of the clock transmission circuit CT51 shown in Figure 7, and therefore will not be repeated here. In the embodiment shown in Figure 8, the jitter suppression circuit JS51 includes a noise amplifier circuit 910, a compensation circuit 920, and a compensation circuit 930. The noise amplifier circuit 910 senses the power supply noise of the power supply voltage VCCQ to generate control signals Pctrl9 and Nctrl9 corresponding to the power supply noise. For example, the noise amplifier circuit 910 compares the power supply voltage VCCQ with a reference voltage VREF. The reference voltage VREF can be a bandgap voltage or other fixed voltage. Based on the difference between the power supply voltage VCCQ and the reference voltage VREF, the noise amplifier circuit 910 generates control signals Pctrl9 and Nctrl9.

[0031] The input terminal of the compensation circuit 920 receives the power supply voltage VCCQ. The output terminal of the compensation circuit 920 is coupled to the power supply terminal of the clock transmission circuit CT51 to supply the power supply current IP51. The control terminal of the compensation circuit 920 is coupled to the noise amplifier circuit 910 to receive the control signal Pctrl9. The input terminal (second terminal) of the compensation circuit 930 is coupled to the reference terminal of the clock transmission circuit CT51 to draw the power supply current IP51. The output terminal (first terminal) of the compensation circuit 930 receives a reference voltage (e.g., ground voltage or other fixed voltage). The control terminal of the compensation circuit 930 is coupled to the noise amplifier circuit 910 to receive the control signal Nctrl9. The compensation circuits 920 and 930 adaptively adjust the power supply current IP51 in response to the control signals Pctrl9 and Nctrl9.

[0032] In the embodiment shown in FIG8, the compensation circuit 920 includes a transistor 921, and the compensation circuit 930 includes a transistor 931. A first terminal (e.g., the source) of transistor 921 receives a power supply voltage VCCQ. A second terminal (e.g., the drain) of transistor 921 is coupled to the power supply terminal of clock transmission circuit CT51 to supply power supply current IP51. A control terminal (e.g., the gate) of transistor 921 is coupled to noise amplifier circuit 910 to receive a control signal Pctrl9. A first terminal (e.g., the source) of transistor 931 receives a reference voltage (e.g., ground voltage or other fixed voltage). A second terminal (e.g., the drain) of transistor 931 is coupled to the reference terminal of clock transmission circuit CT51 to draw power supply current IP51. A control terminal (e.g., the gate) of transistor 931 is coupled to noise amplifier circuit 910 to receive a control signal Nctrl9.

[0033] Transistor 921 adaptively adjusts the power supply current IP51 in response to control signal Pctrl9, and transistor 931 adaptively adjusts the power supply current IP51 in response to control signal Nctrl9. For example, when power supply noise in the power supply voltage VCCQ causes the power supply voltage VCCQ to rise, the noise amplifier circuit 910 adaptively increases control signal Pctrl9 and adaptively decreases control signal Nctrl9. Therefore, the power supply current IP51 of the clock transmission circuit CT51 is correspondingly reduced. When power supply noise in the power supply voltage VCCQ causes the power supply voltage VCCQ to fall, the jitter suppression circuit JS51 adaptively decreases control signal Pctrl9 and adaptively increases control signal Nctrl9. Therefore, the power supply current IP51 of the clock transmission circuit CT51 is correspondingly increased.

[0034] The implementation of compensation circuits 920 and 930 should not be limited to the example shown in FIG8. Compensation circuits 920 and 930 may have different implementations depending on the actual design and application. For example, FIG9 is a circuit block diagram of compensation circuits 920 and 930 according to another embodiment of the present invention. The jitter suppression circuit JS51 shown in FIG9 can be one of many implementation examples of the jitter suppression circuit JS51 shown in FIG4. The clock transmission circuit CT51 shown in FIG9 can be referred to the relevant description of the clock transmission circuit CT51 shown in FIG7, and therefore will not be repeated here.

[0035] In the embodiment shown in FIG9, the compensation circuit 920 includes a transistor 922 and a capacitor 923. A first terminal (e.g., the source) of transistor 922 receives a power supply voltage VCCQ. A second terminal (e.g., the drain) of transistor 922 is coupled to the power supply terminal of clock transmission circuit CT51 to supply power supply current IP51. A control terminal (e.g., the gate) of transistor 921 is coupled to noise amplifier circuit 910 to receive a control signal Pctrl9. Transistor 922 adaptively adjusts the power supply current IP51 in response to the control signal Pctrl9. A first terminal of capacitor 923 receives the power supply voltage VCCQ. A second terminal of capacitor 923 is coupled to the control terminal of transistor 922.

[0036] In the embodiment shown in FIG9, the compensation circuit 930 includes transistor 932, transistor 933, and capacitor 934. The control terminal (e.g., gate) of transistor 933 is controlled by the power supply voltage VCCQ. The first terminal (e.g., source) of transistor 933 receives a reference voltage (e.g., ground voltage or other fixed voltage). The first terminal (e.g., source) of transistor 932 is coupled to the second terminal (e.g., drain) of transistor 933. The second terminal (e.g., drain) of transistor 932 is coupled to the reference terminal of clock transmission circuit CT51 to draw power supply current IP51. The control terminal (e.g., gate) of transistor 932 is coupled to noise amplifier circuit 910 to receive control signal Nctrl9. Transistor 932 adaptively adjusts power supply current IP51 in response to control signal Nctrl9. The first terminal of capacitor 934 receives power supply voltage VCCQ. The second terminal of capacitor 934 is coupled to the first terminal of transistor 932. When the bandwidth of the noise amplifier circuit 910 is insufficient, capacitors 923 and 934 can compensate for the bandwidth.

[0037] FIG10 is a circuit block diagram of a noise amplifier circuit 910 according to an embodiment of the present invention. The noise amplifier circuit 910 shown in FIG10 can be one of many embodiments of the noise amplifier circuit 910 shown in FIG8 or FIG9. The clock transmission circuit CT51 shown in FIG10 can be described with reference to the relevant description of the clock transmission circuit CT51 shown in FIG4. The compensation circuits 920 and 930 shown in FIG10 can be described with reference to the relevant description of the compensation circuits 920 and 930 shown in FIG8, or with reference to the relevant description of the compensation circuits 920 and 930 shown in FIG9.

[0038] In the embodiment shown in FIG. 10, the noise amplifier circuit 910 includes an error amplifier circuit 911. The input terminal IN111 of the error amplifier circuit 911 (e.g., one of a non-inverting input and an inverting input) receives the power supply voltage VCCQ. The input terminal IN112 of the error amplifier circuit 911 (e.g., the other of a non-inverting input and an inverting input) receives a reference voltage VREF11. The level of the reference voltage VREF11 can be determined according to the actual design and application. For example, the reference voltage VREF11 can be a bandgap voltage or other fixed voltage. The error amplifier circuit 911 compares the power supply voltage VCCQ with the reference voltage VREF11. Based on the difference between the power supply voltage VCCQ and the reference voltage VREF11, the error amplifier circuit 911 generates control signals Pctrl9 and Nctrl9. The output terminal OUT111 of the error amplifier circuit 911 is coupled to the control terminal of the compensation circuit 920 to supply the control signal Pctrl9. The output terminal OUT112 of the error amplifier circuit 911 is coupled to the control terminal of the compensation circuit 930 to supply the control signal Nctrl9.

[0039] FIG11 is a circuit diagram of an error amplifier circuit 911 according to an embodiment of the present invention. The error amplifier circuit 911 shown in FIG11 can be one of many embodiments of the error amplifier circuit 911 shown in FIG10. The error amplifier circuit 911, input terminal IN111, input terminal IN112, output terminal OUT111 and output terminal OUT112 shown in FIG11 can be referred to the relevant description in FIG10. In the embodiment shown in FIG11, the error amplifier circuit 911 includes transistors MP121, MP122, MN121, MN122, resistor R121, capacitor C121, capacitor C122, current source CS121 and current source CS122. The first terminal (e.g., source) of transistor MP121 and the first terminal (e.g., source) of transistor MP122 receive the power supply voltage VCCQ. The control terminal (e.g., gate) of transistor MP121 and the control terminal (e.g., gate) of transistor MP122 receive the reference voltage VSS. The level of the reference voltage VSS can be determined based on the actual design and application. For example, the reference voltage VSS can be ground voltage or other fixed voltage.

[0040] The second terminal (e.g., drain) of transistor MP121 is coupled to the output terminal OUT112 of error amplifier circuit 911. The second terminal (e.g., drain) of transistor MP122 is coupled to the output terminal OUT111 of error amplifier circuit 911. The first terminal (e.g., drain) of transistor MN121 is coupled to the second terminal of transistor MP121. The control terminal (e.g., gate) of transistor MN121 is coupled to the input terminal IN111 of error amplifier circuit 911. The first terminal (e.g., drain) of transistor MN122 is coupled to the second terminal of transistor MP122. The control terminal (e.g., gate) of transistor MN122 is coupled to the input terminal IN112 of error amplifier circuit 911. The first terminal of resistor R121 is coupled to the second terminal (e.g., source) of transistor MN121. The second terminal of resistor R121 is coupled to the second terminal (e.g., source) of transistor MN122. The first terminal of capacitor C121 is coupled to the control terminal of transistor MN121. The second terminal of capacitor C121 is coupled to the second terminal of transistor MN122. The first terminal of capacitor C122 is coupled to the control terminal of transistor MN122. The second terminal of capacitor C122 is coupled to the second terminal of transistor MN121. Current source CS121 is coupled to the second terminal of transistor MN121. Current source CS122 is coupled to the second terminal of transistor MN122.

[0041] FIG12 is a circuit diagram of an error amplifier circuit 911 according to another embodiment of the present invention. The error amplifier circuit 911 shown in FIG12 can be one of many embodiments of the error amplifier circuit 911 shown in FIG10. The error amplifier circuit 911, input terminal IN111, input terminal IN112, output terminal OUT111 and output terminal OUT112 shown in FIG12 can be referred to the relevant description in FIG10. In the embodiment shown in FIG12, the error amplifier circuit 911 includes transistors MP131, MP132, MN131, MN132, MN133, MN134, resistor R131, capacitor C131, capacitor C132, current source CS131, current source CS132, current source CS133 and current source CS134. The first terminal (e.g., drain) of transistor MN131 and the first terminal (e.g., drain) of transistor MN132 receive the power supply voltage VCCQ. The control terminal (e.g., gate) of transistor MN131 is coupled to the input terminal IN111 of error amplifier circuit 911. The control terminal (e.g., gate) of transistor MN132 is coupled to the input terminal IN112 of error amplifier circuit 911.

[0042] The control terminal (e.g., gate) of transistor MP131 is coupled to the second terminal (e.g., source) of transistor MN131. The first terminal (e.g., drain) of transistor MP131 is coupled to the output terminal OUT112 of error amplifier circuit 911. The control terminal (e.g., gate) of transistor MP132 is coupled to the second terminal (e.g., source) of transistor MN132. The first terminal (e.g., drain) of transistor MP132 is coupled to the output terminal OUT111 of error amplifier circuit 911. The first terminal (e.g., drain) of transistor MN133 is coupled to the first terminal of transistor MP131. The second terminal (e.g., source) of transistor MN133 receives a reference voltage (e.g., ground voltage or other fixed voltage). The first terminal (e.g., drain) of transistor MN134 is coupled to the first terminal of transistor MP132. The second terminal (e.g., source) of transistor MN134 receives a reference voltage (e.g., ground voltage or other fixed voltage). The control terminals (e.g., gates) of transistors MN133 and MN134 receive the power supply voltage VCCQ.

[0043] The first terminal of resistor R131 is coupled to the second terminal (e.g., the source) of transistor MP131. The second terminal of resistor R131 is coupled to the second terminal (e.g., the source) of transistor MP132. The first terminal of capacitor C131 is coupled to the control terminal of transistor MN131. The second terminal of capacitor C131 is coupled to the second terminal (e.g., the source) of transistor MP132. The first terminal of capacitor C132 is coupled to the control terminal of transistor MN132. The second terminal of capacitor C132 is coupled to the second terminal of transistor MP131. Current source CS131 is coupled to the second terminal of transistor MN131. Current source CS132 is coupled to the second terminal of transistor MN132. Current source CS133 is coupled to the second terminal of transistor MP131. Current source CS134 is coupled to the second terminal of transistor MP132.

[0044] FIG13 is a circuit block diagram of a noise amplifier circuit 910 according to another embodiment of the present invention. The noise amplifier circuit 910 shown in FIG13 can be one of many embodiments of the noise amplifier circuit 910 shown in FIG8 or FIG9. The clock transmission circuit CT51 shown in FIG13 can be referred to the relevant description of the clock transmission circuit CT51 shown in FIG4. The compensation circuits 920 and 930 shown in FIG13 can be referred to the relevant description of the compensation circuits 920 and 930 shown in FIG8, or the relevant description of the compensation circuits 920 and 930 shown in FIG9.

[0045] In the embodiment shown in FIG. 13, the noise amplifier circuit 910 includes an error amplifier circuit 912 and a gain circuit 913. The input terminal IN141 of the error amplifier circuit 912 (e.g., one of a non-inverting input and an inverting input) receives the power supply voltage VCCQ. The input terminal IN142 of the error amplifier circuit 912 (e.g., the other of a non-inverting input and an inverting input) receives a reference voltage VREF14. The level of the reference voltage VREF14 can be determined according to the actual design and application. For example, the reference voltage VREF14 can be a bandgap voltage or other fixed voltage. The error amplifier circuit 912 compares the power supply voltage VCCQ with the reference voltage VREF14. Based on the difference between the power supply voltage VCCQ and the reference voltage VREF14, the error amplifier circuit 912 generates error signals Vop14 and Von14 for the gain circuit 913. The error amplifier circuit 912 shown in Figure 13, its input terminals IN141 and IN142, and its output terminals OUT141 and OUT142 can be deduced by referring to the relevant descriptions of the error amplifier circuit 911, its input terminals IN111 and IN112, and its output terminals OUT111 and OUT112 shown in Figure 11, or by referring to the relevant descriptions of the error amplifier circuit 911, its input terminals IN111 and IN112, and its output terminals OUT111 and OUT112 shown in Figure 12. Therefore, they will not be elaborated upon here.

[0046] The input terminal IN143 of the gain circuit 913 is coupled to the output terminal OUT141 of the error amplifier circuit 912 to receive the error signal Vop14. The input terminal IN144 of the gain circuit 913 is coupled to the output terminal OUT142 of the error amplifier circuit 912 to receive the error signal Von14. The gain circuit 913 converts the error signal into control signals Pctrl9 and Nctrl9. The output terminal OUT143 of the gain circuit 913 is coupled to the control terminal of the compensation circuit 920 to supply the control signal Pctrl9. The output terminal OUT144 of the gain circuit 913 is coupled to the control terminal of the compensation circuit 930 to supply the control signal Nctrl9. Depending on the actual design, the gain circuit 913 may include a current-mode logic circuit or other gain circuits. For example, different implementation examples of the gain circuit 913 will be described below.

[0047] FIG14 is a circuit diagram of a gain circuit 913 according to an embodiment of the present invention. The gain circuit 913 shown in FIG14 can be one of many embodiments of the gain circuit 913 shown in FIG13. The gain circuit 913, input terminal IN143, input terminal IN144, output terminal OUT143 and output terminal OUT144 shown in FIG14 can be referred to the relevant description in FIG13. In the embodiment shown in FIG14, the gain circuit 913 includes transistors MP151, MP152, MP153, MP154, MN151, MN152 and a current source CS151. The first terminal (e.g., source) of transistor MP151 and the first terminal (e.g., source) of transistor MP152 receive the power supply voltage VCCQ. The second terminal (e.g., drain) of transistor MP151 is coupled to the output terminal OUT143 of the gain circuit 913. The second terminal (e.g., drain) of transistor MP152 is coupled to the output terminal OUT144 of gain circuit 913. The control terminal (e.g., gate) of transistor MP152 is coupled to the control terminal (e.g., gate) of transistor MP151.

[0048] The first terminal (e.g., drain) of transistor MN151 is coupled to the second terminal of transistor MP151. The control terminal (e.g., gate) of transistor MN151 is coupled to the input terminal IN144 of gain circuit 913. The first terminal (e.g., drain) of transistor MN152 is coupled to the second terminal of transistor MN152. The control terminal (e.g., gate) of transistor MN152 is coupled to the input terminal IN143 of gain circuit 913. The first terminal of transistor MP153 is coupled to the second terminal of transistor MP151. The second terminal of transistor MP153 is coupled to the control terminals of transistors MP151 and MP152. The first terminal of transistor MP154 is coupled to the second terminal of transistor MP152. The second terminal of transistor MP154 is coupled to the control terminals of transistors MP151 and MP152. The control terminals of transistors MP153 and MP154 receive a reference voltage VSS. The level of the reference voltage VSS can be determined according to the actual design and application. For example, the reference voltage VSS can be ground voltage or other fixed voltage. The current source CS151 is coupled to the second terminal (e.g., the source) of the third transistor MN151 and the second terminal (e.g., the source) of the transistor MN152.

[0049] FIG15 is a circuit diagram of a gain circuit 913 according to another embodiment of the present invention. The gain circuit 913 shown in FIG15 can be one of many embodiments of the gain circuit 913 shown in FIG13. The gain circuit 913, input terminal IN143, input terminal IN144, output terminal OUT143 and output terminal OUT144 shown in FIG15 can be referred to the relevant description in FIG13. In the embodiment shown in FIG15, the gain circuit 913 includes transistors MP161, MP162, MN161, MN162, MN163, MN164 and a current source CS161. The first terminal (e.g., source) of transistor MP161 is coupled to the first terminal (e.g., source) of transistor MP162 to the current source CS161. The second terminal (e.g., drain) of transistor MP161 is coupled to the output terminal OUT144 of the gain circuit 913. The control terminal (e.g., gate) of transistor MP161 is coupled to the input terminal IN143 of gain circuit 913. The second terminal (e.g., drain) of transistor MP162 is coupled to the output terminal OUT143 of gain circuit 913. The control terminal (e.g., gate) of transistor MP162 is coupled to the input terminal IN144 of gain circuit 913.

[0050] A first terminal (e.g., drain) of transistor MN161 is coupled to a second terminal of transistor MP161. A first terminal (e.g., drain) of transistor MN162 is coupled to a second terminal of transistor MP162. A control terminal (e.g., gate) of transistor MN162 is coupled to a control terminal (e.g., gate) of transistor MN161. A second terminal (e.g., source) of transistor MN161 and a second terminal (e.g., source) of transistor MN162 receive a reference voltage (e.g., ground voltage or other fixed voltage). A first terminal of transistor MN163 is coupled to a second terminal of transistor MP161. A second terminal of transistor MN163 is coupled to a control terminal of transistor MN161. A first terminal of transistor MN164 is coupled to a second terminal of transistor MP162. A second terminal of transistor MN164 is coupled to a control terminal of transistor MN162. The control terminals (e.g., gates) of transistor MN163 and transistor MN164 receive the power supply voltage VCCQ.

[0051] In other embodiments, the gain circuit 913 includes current-mode logic circuitry. For example, FIG16 is a circuit diagram of the gain circuit 913 according to another embodiment of the present invention. The gain circuit 913 shown in FIG16 can be one of many embodiments of the gain circuit 913 shown in FIG13. The gain circuit 913, input terminal IN143, input terminal IN144, output terminal OUT143 and output terminal OUT144 shown in FIG16 can be referred to the relevant description in FIG13. In the embodiment shown in FIG16, the gain circuit 913 includes transistors MN171 and MN172, resistors R171 and R172, and a current source CS171. The first terminal of resistor R171 and the first terminal of resistor R172 receive the power supply voltage VCCQ. The second terminal of resistor R171 is coupled to the output terminal OUT143 of the gain circuit 913. The second terminal of resistor R172 is coupled to the output terminal OUT144 of the gain circuit 913. The first terminal (e.g., drain) of transistor MN171 is coupled to the second terminal of resistor R171. The control terminal (e.g., gate) of transistor MN171 is coupled to the input terminal IN144 of gain circuit 913. The first terminal (e.g., drain) of transistor MN172 is coupled to the second terminal of resistor R172. The control terminal (e.g., gate) of transistor MN172 is coupled to the input terminal IN143 of gain circuit 913. Current source CS171 is coupled to the second terminal (e.g., source) of transistor MN171 and the second terminal (e.g., source) of transistor MN172.

[0052] FIG17 is a circuit diagram of a gain circuit 913 (current-mode logic circuit) according to another embodiment of the present invention. The gain circuit 913 shown in FIG17 can be one of many embodiments of the gain circuit 913 shown in FIG13. The gain circuit 913, input terminal IN143, input terminal IN144, output terminal OUT143 and output terminal OUT144 shown in FIG17 can be referred to the relevant description in FIG13. In the embodiment shown in FIG17, the gain circuit 913 includes transistor MP181, transistor MP182, resistor R181, resistor R182 and current source CS181. The first terminal (e.g., source) of transistor MP181 is coupled to the first terminal (e.g., source) of transistor MP182 to the current source CS181. The second terminal (e.g., drain) of transistor MP181 is coupled to the output terminal OUT144 of the gain circuit 913. The control terminal (e.g., gate) of transistor MP181 is coupled to the input terminal IN143 of gain circuit 913. The second terminal (e.g., drain) of transistor MP182 is coupled to the output terminal OUT143 of gain circuit 913. The control terminal (e.g., gate) of transistor MP182 is coupled to the input terminal IN144 of gain circuit 913. The first terminal of resistor R181 is coupled to the second terminal of transistor MP181. The first terminal of resistor R182 is coupled to the second terminal of transistor MP182. The second terminals of resistors R181 and R182 receive a reference voltage VSS. The level of the reference voltage VSS can be determined according to the actual design and application. For example, the reference voltage VSS can be ground voltage or other fixed voltage.

[0053] FIG18 is a circuit block diagram of a noise amplifier circuit 910 according to another embodiment of the present invention. The noise amplifier circuit 910 shown in FIG18 can be one of many embodiments of the noise amplifier circuit 910 shown in FIG8 or FIG9. The clock transmission circuit CT51 shown in FIG18 can be referred to the relevant description of the clock transmission circuit CT51 shown in FIG4. The compensation circuits 920 and 930 shown in FIG18 can be referred to the relevant description of the compensation circuits 920 and 930 shown in FIG8, or the relevant description of the compensation circuits 920 and 930 shown in FIG9.

[0054] In the embodiment shown in FIG18, the noise amplifier circuit 910 includes an error amplifier circuit 914, an error amplifier circuit 915, a gain circuit 916, and a gain circuit 917. The input terminal IN191 of the error amplifier circuit 914 (e.g., one of the non-inverting input and the inverting input) receives the power supply voltage VCCQ, while the input terminal IN192 of the error amplifier circuit 914 (e.g., the other of the non-inverting input and the inverting input) is connected to a reference voltage VREF19. The level of the reference voltage VREF19 can be determined according to the actual design and application. For example, the reference voltage VREF19 can be a bandgap voltage or other fixed voltage. The input terminal IN193 of the error amplifier circuit 915 (e.g., one of the non-inverting input and the inverting input) receives the power supply voltage VCCQ, while the input terminal IN194 of the error amplifier circuit 915 (e.g., the other of the non-inverting input and the inverting input) is connected to the reference voltage VREF19. Error amplifier circuits 914 and 915 can compare the power supply voltage VCCQ with the reference voltage VREF19. Based on the difference between the power supply voltage VCCQ and the reference voltage VREF19, error amplifier circuit 914 generates error signals Vop191 and Von191 to the gain circuit 916, while error amplifier circuit 915 generates error signals Vop192 and Von192 to the gain circuit 917. The error amplifier circuit 914, input terminals IN191, IN192, output terminals OUT191 and OUT192 shown in Figure 18 can be deduced from the relevant descriptions of the error amplifier circuit 911, input terminals IN111, IN112, output terminals OUT111 and OUT112 shown in Figure 11. Similarly, the error amplifier circuit 915, input terminals IN193, IN194, output terminals OUT193 and OUT194 shown in Figure 18 can be deduced from the relevant descriptions of the error amplifier circuit 911, input terminals IN111, IN112, output terminals OUT111 and OUT112 shown in Figure 12. Therefore, they will not be described in detail here.

[0055] The input terminal IN195 of the gain circuit 916 is coupled to the output terminal OUT191 of the error amplifier circuit 914 to receive the error signal Vop191. The input terminal IN196 of the gain circuit 916 is coupled to the output terminal OUT192 of the error amplifier circuit 914 to receive the error signal Von191. The gain circuit 916 converts the error signals Vop191 and Von191 into a control signal Pctrl9. The output terminal OUT195 of the gain circuit 916 is coupled to the control terminal of the compensation circuit 920 to supply the control signal Pctrl9. The input terminal IN197 of the gain circuit 917 is coupled to the output terminal OUT193 of the error amplifier circuit 915 to receive the error signal Von192. The input terminal IN198 of the gain circuit 917 is coupled to the output terminal OUT194 of the error amplifier circuit 915 to receive the error signal Von192. Gain circuit 917 converts error signals Vop192 and Von192 into control signal Nctrl9. The output terminal OUT196 of gain circuit 917 is coupled to the control terminal of compensation circuit 930 to supply control signal Nctrl9. The gain circuit 916, input terminals IN195, IN196, and output terminal OUT195 shown in Figure 18 can be deduced by referring to the relevant descriptions of gain circuit 913, input terminals IN143, IN144, and output terminal OUT143 shown in Figure 14, and similarly by referring to the relevant descriptions of gain circuit 917, input terminals IN197, IN198, and output terminal OUT196 shown in Figure 18. Therefore, they will not be elaborated upon here.

[0056] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0057] Figure 1 is a circuit block diagram of a non-volatile memory volume circuit according to an embodiment of the present invention. Figure 2 is a circuit block diagram of a non-volatile memory volume circuit according to an embodiment of the present invention. Figure 3 is a circuit block diagram of a clock transmission device according to an embodiment. Figure 4 is a circuit block diagram of a clock transmission device according to an embodiment of the present invention. Figure 5 is a flowchart illustrating an operation method of a clock transmission device according to an embodiment of the present invention. Figure 6 is a circuit block diagram of a clock transmission device according to another embodiment of the present invention. Figure 7 is a circuit block diagram of a clock transmission circuit according to an embodiment of the present invention. Figure 8 is a circuit block diagram of a jitter suppression circuit according to an embodiment of the present invention. Figure 9 is a circuit block diagram of a compensation circuit according to another embodiment of the present invention. Figure 10 is a circuit block diagram of a noise amplifier circuit according to an embodiment of the present invention. Figure 11 is a circuit block diagram of an error amplifier circuit according to an embodiment of the present invention. Figure 12 is a circuit diagram of an error amplifier circuit according to another embodiment of the present invention. Figure 13 is a circuit block diagram of a noise amplifier circuit according to another embodiment of the present invention. Figure 14 is a circuit diagram of a gain circuit according to one embodiment of the present invention. Figure 15 is a circuit diagram of a gain circuit according to another embodiment of the present invention. Figure 16 is a circuit diagram of a gain circuit according to yet another embodiment of the present invention. Figure 17 is a circuit diagram of a gain circuit according to yet another embodiment of the present invention. Figure 18 is a circuit block diagram of a noise amplifier circuit according to yet another embodiment of the present invention.

Claims

1. A clock transmission device, comprising: A clock transmission circuit that generates at least one output clock based on an input clock; The system also includes a jitter suppression circuit that supplies a power current to the clock transmission circuit based on a power supply voltage. The jitter suppression circuit adaptively adjusts the power current in response to power supply noise in the power supply voltage to suppress jitter caused by power supply noise in the at least one output clock. The jitter suppression circuit includes: a noise amplification circuit that senses the power supply noise in the power supply voltage to generate a first control signal corresponding to the power supply noise; and a first compensation circuit, wherein an input terminal of the first compensation circuit receives the power supply voltage, an output terminal of the first compensation circuit is coupled to a power supply terminal of the clock transmission circuit to supply the power current, a control terminal of the first compensation circuit is coupled to the noise amplification circuit to receive the first control signal, and the first compensation circuit adaptively adjusts the power current in response to the first control signal. The first compensation circuit further includes: A transistor, wherein a first terminal of the transistor receives the power supply voltage, a second terminal of the transistor is coupled to the power supply terminal of the clock transmission circuit to supply the power supply current, a control terminal of the transistor is coupled to the noise amplifier circuit to receive the first control signal, and the transistor adaptively adjusts the power supply current in response to the first control signal; and a capacitor, wherein a first terminal of the capacitor receives the power supply voltage, and a second terminal of the capacitor is coupled to the control terminal of the transistor.

2. The clock transmission device as claimed in claim 1, wherein the clock transmission circuit comprises: A gain circuit amplifies the input clock to generate a boosted clock, wherein a jitter suppression circuit supplies the power supply current to the gain circuit, the jitter suppression circuit senses the power supply noise of the power supply voltage and adaptively adjusts the power supply current to suppress jitter caused by power supply noise in the boosted clock; and a clock tree circuit coupled to an output of the gain circuit to receive the boosted clock, wherein the clock tree circuit generates the at least one output clock based on the boosted clock.

3. The clock transmission device as claimed in claim 1, wherein the noise amplification circuit includes: An error amplifier circuit is provided, wherein a first input terminal of the error amplifier circuit receives the power supply voltage, a second input terminal of the error amplifier circuit receives a first reference voltage, the error amplifier circuit compares the power supply voltage with the first reference voltage to generate the first control signal, and a first output terminal of the error amplifier circuit is coupled to the control terminal of the first compensation circuit to supply the first control signal.

4. The clock transmission device as claimed in claim 3, wherein the first reference voltage is a bandgap voltage.

5. The clock transmission device as claimed in claim 3, wherein the error amplification circuit comprises: A first transistor, wherein a first terminal of the first transistor receives the power supply voltage, a second terminal of the first transistor is coupled to a second output terminal of the error amplifier circuit, and a control terminal of the first transistor receives a second reference voltage; a second transistor, wherein a first terminal of the second transistor receives the power supply voltage, a second terminal of the second transistor is coupled to the first output terminal of the error amplifier circuit, and a control terminal of the second transistor receives the second reference voltage; a third transistor, wherein a first terminal of the third transistor is coupled to the second terminal of the first transistor, and a control terminal of the third transistor is coupled to the first input terminal of the error amplifier circuit; a fourth transistor, wherein a first terminal of the fourth transistor is coupled to the second terminal of the second transistor, and a control terminal of the fourth transistor is coupled to the second input terminal of the error amplifier circuit; a resistor, wherein a first terminal of the resistor is coupled to the second terminal of the third transistor, and a second terminal of the resistor is coupled to the second terminal of the fourth transistor; A first capacitor, wherein a first terminal of the first capacitor is coupled to the control terminal of the third transistor, and a second terminal of the first capacitor is coupled to the second terminal of the fourth transistor; a second capacitor, wherein a first terminal of the second capacitor is coupled to the control terminal of the fourth transistor, and a second terminal of the second capacitor is coupled to the second terminal of the third transistor; a first current source coupled to the second terminal of the third transistor; and a second current source coupled to the second terminal of the fourth transistor.

6. The clock transmission device as claimed in claim 3, wherein the error amplifier circuit comprises: A first transistor, wherein a first terminal of the first transistor receives the power supply voltage, and a control terminal of the first transistor is coupled to the first input terminal of the error amplifier circuit; a second transistor, wherein a first terminal of the second transistor receives the power supply voltage, and a control terminal of the second transistor is coupled to the second input terminal of the error amplifier circuit; a third transistor, wherein a control terminal of the third transistor is coupled to a second terminal of the first transistor, and a first terminal of the third transistor is coupled to a second output terminal of the error amplifier circuit; a fourth transistor, wherein a control terminal of the fourth transistor is coupled to a second terminal of the second transistor, and a first terminal of the fourth transistor is coupled to the first output terminal of the error amplifier circuit; a fifth transistor, wherein a first terminal of the fifth transistor is coupled to the first terminal of the third transistor, a second terminal of the fifth transistor receives a second reference voltage, and a control terminal of the fifth transistor receives the power supply voltage; A sixth transistor, wherein a first terminal of the sixth transistor is coupled to the first terminal of the fourth transistor, a second terminal of the sixth transistor receives the second reference voltage, and a control terminal of the sixth transistor receives the power supply voltage; a resistor, wherein a first terminal of the resistor is coupled to a second terminal of the third transistor, and a second terminal of the resistor is coupled to a second terminal of the fourth transistor; a first capacitor, wherein a first terminal of the first capacitor is coupled to the control terminal of the first transistor, and a second terminal of the first capacitor is coupled to the second terminal of the fourth transistor; a second capacitor, wherein a first terminal of the second capacitor is coupled to the control terminal of the second transistor, and a second terminal of the second capacitor is coupled to the second terminal of the third transistor; a first current source coupled to the second terminal of the first transistor; and a second current source coupled to the second terminal of the second transistor. A third current source coupled to the second terminal of the third transistor; and a fourth current source coupled to the second terminal of the fourth transistor.

7. The clock transmission device as claimed in claim 1, wherein the noise amplification circuit includes: An error amplifier circuit, wherein a first input terminal of the error amplifier circuit receives the power supply voltage, a second input terminal of the error amplifier circuit receives a first reference voltage, and the error amplifier circuit compares the power supply voltage with the first reference voltage to generate an error signal; And a gain circuit, wherein a first input terminal of the gain circuit is coupled to a first output terminal of the error amplifier circuit, a second input terminal of the gain circuit is coupled to a second output terminal of the error amplifier circuit, the gain circuit converts the error signal into the first control signal, and a first output terminal of the gain circuit is coupled to the control terminal of the first compensation circuit to supply the first control signal.

8. The clock transmission device as claimed in claim 7, wherein the gain circuit comprises: A first transistor, wherein a first terminal of the first transistor receives the power supply voltage, and a second terminal of the first transistor is coupled to the first output terminal of the gain circuit; a second transistor, wherein a first terminal of the second transistor receives the power supply voltage, a second terminal of the second transistor is coupled to a second output terminal of the gain circuit, and a control terminal of the second transistor is coupled to a control terminal of the first transistor; a third transistor, wherein a first terminal of the third transistor is coupled to the second terminal of the first transistor, and a control terminal of the third transistor is coupled to the second input terminal of the gain circuit; a fourth transistor, wherein a first terminal of the fourth transistor is coupled to the second terminal of the second transistor, and a control terminal of the fourth transistor is coupled to the first input terminal of the gain circuit; a fifth transistor, wherein a first terminal of the fifth transistor is coupled to the second terminal of the first transistor, a second terminal of the fifth transistor is coupled to the control terminal of the first transistor, and a control terminal of the fifth transistor receives a second reference voltage; A sixth transistor, wherein a first terminal of the sixth transistor is coupled to the second terminal of the second transistor, a second terminal of the sixth transistor is coupled to the control terminal of the second transistor, and the control terminal of the sixth transistor receives the second reference voltage; and a current source is coupled to a second terminal of the third transistor and a second terminal of the fourth transistor.

9. The clock transmission device as claimed in claim 7, wherein the gain circuit comprises: A current source; A first transistor, wherein a first terminal of the first transistor is coupled to the current source, a second terminal of the first transistor is coupled to a second output terminal of the gain circuit, and a control terminal of the first transistor is coupled to the first input terminal of the gain circuit; a second transistor, wherein a first terminal of the second transistor is coupled to the current source, a second terminal of the second transistor is coupled to the first output terminal of the gain circuit, and a control terminal of the second transistor is coupled to the second input terminal of the gain circuit; a third transistor, wherein a first terminal of the third transistor is coupled to the second terminal of the first transistor, and the second terminal of the third transistor receives a second reference voltage; a fourth transistor, wherein a first terminal of the fourth transistor is coupled to the second terminal of the second transistor, the second terminal of the fourth transistor receives the second reference voltage, and a control terminal of the fourth transistor is coupled to a control terminal of the third transistor; A fifth transistor, wherein a first terminal of the fifth transistor is coupled to the second terminal of the first transistor, a second terminal of the fifth transistor is coupled to the control terminal of the third transistor, and a control terminal of the fifth transistor receives the power supply voltage; and a sixth transistor, wherein a first terminal of the sixth transistor is coupled to the second terminal of the second transistor, a second terminal of the sixth transistor is coupled to the control terminal of the fourth transistor, and a control terminal of the sixth transistor receives the power supply voltage.

10. The clock transmission device as claimed in claim 7, wherein the gain circuit includes a current-mode logic circuit.

11. The clock transmission device as claimed in claim 10, wherein the current-mode logic circuitry comprises: A first resistor, wherein a first terminal of the first resistor receives the power supply voltage, and a second terminal of the first resistor is coupled to the first output terminal of the gain circuit; a second resistor, wherein a first terminal of the second resistor receives the power supply voltage, and a second terminal of the second resistor is coupled to a second output terminal of the gain circuit; a first transistor, wherein a first terminal of the first transistor is coupled to the second terminal of the first resistor, and a control terminal of the first transistor is coupled to the second input terminal of the gain circuit; a second transistor, wherein a first terminal of the second transistor is coupled to the second terminal of the second resistor, and a control terminal of the second transistor is coupled to the first input terminal of the gain circuit; and a current source coupled to a second terminal of the first transistor and a second terminal of the second transistor.

12. The clock transmission device as claimed in claim 10, wherein the current-mode logic circuitry includes: A current source; A first transistor, wherein a first terminal of the first transistor is coupled to the current source, a second terminal of the first transistor is coupled to a second output terminal of the gain circuit, and a control terminal of the first transistor is coupled to the first input terminal of the gain circuit; a second transistor, wherein a first terminal of the second transistor is coupled to the current source, a second terminal of the second transistor is coupled to the first output terminal of the gain circuit, and a control terminal of the second transistor is coupled to the second input terminal of the gain circuit; a first resistor, wherein a first terminal of the first resistor is coupled to the second terminal of the first transistor, and the second terminal of the first resistor receives a second reference voltage; and a second resistor, wherein a first terminal of the second resistor is coupled to the second terminal of the second transistor, and the second terminal of the second resistor receives the second reference voltage.

13. The clock transmission device as claimed in claim 1, wherein the noise amplification circuit includes: A first error amplifier circuit, wherein a first input terminal of the first error amplifier circuit receives the power supply voltage, a second input terminal of the first error amplifier circuit receives a first reference voltage, and the first error amplifier circuit compares the power supply voltage with the first reference voltage to generate a first error signal; a first gain circuit, wherein a first input terminal of the first gain circuit is coupled to a first output terminal of the first error amplifier circuit, a second input terminal of the first gain circuit is coupled to a second output terminal of the first error amplifier circuit, the first gain circuit converts the first error signal into the first control signal, and an output terminal of the first gain circuit is coupled to the control terminal of the first compensation circuit to supply the first control signal; A second error amplifier circuit, wherein a first input terminal of the second error amplifier circuit receives the power supply voltage, a second input terminal of the second error amplifier circuit receives the first reference voltage, and the second error amplifier circuit compares the power supply voltage with the first reference voltage to generate a second error signal; and a second gain circuit, wherein a first input terminal of the second gain circuit is coupled to a first output terminal of the second error amplifier circuit, a second input terminal of the second gain circuit is coupled to a second output terminal of the second error amplifier circuit, the second gain circuit converts the second error signal into a second control signal, an output terminal of the second gain circuit is coupled to a control terminal of a second compensation circuit of the jitter suppression circuit to supply the second control signal, a first terminal of the second compensation circuit receives a second reference voltage, and a second terminal of the second compensation circuit is coupled to a reference terminal of the clock transmission circuit.

14. The clock transmission device as claimed in claim 1, wherein the jitter suppression circuit further comprises: A second compensation circuit, wherein a first terminal of the second compensation circuit receives a reference voltage, a second terminal of the second compensation circuit is coupled to a reference terminal of the clock transmission circuit, and a control terminal of the second compensation circuit is coupled to the noise amplifier circuit to receive a second control signal.

15. The clock transmission device as claimed in claim 14, wherein the second compensation circuit comprises: A first transistor, wherein a first terminal of the first transistor receives the reference voltage, a second terminal of the first transistor is coupled to the reference terminal of the clock transmission circuit, and a control terminal of the first transistor is coupled to the noise amplifier circuit to receive the second control signal.

16. The clock transmission device as claimed in claim 14, wherein the second compensation circuit comprises: A first transistor, wherein a first terminal of the first transistor receives the reference voltage, and a control terminal of the first transistor receives the power supply voltage; A second transistor, wherein a first terminal of the second transistor is coupled to a second terminal of the first transistor, the second terminal of the second transistor is coupled to the reference terminal of the clock transmission circuit, and a control terminal of the second transistor is coupled to the noise amplifier circuit to receive the second control signal; and a first capacitor, wherein a first terminal of the first capacitor receives the power supply voltage, and a second terminal of the first capacitor is coupled to the first terminal of the second transistor.

17. A method of operating a clock transmission device, comprising: A clock transmission circuit of the clock transmission device generates at least one output clock based on an input clock. A jitter suppression circuit of the clock transmission device supplies a power current to the clock transmission circuit based on a power supply voltage; the jitter suppression circuit adaptively adjusts the power current in response to power supply noise of the power supply voltage to suppress jitter caused by power supply noise of the at least one output clock; a noise amplification circuit of the jitter suppression circuit senses the power supply noise of the power supply voltage to generate a first control signal corresponding to the power supply noise; a first compensation circuit of the jitter suppression circuit adaptively adjusts the power current in response to the first control signal, wherein an input terminal of the first compensation circuit receives the power supply voltage, an output terminal of the first compensation circuit is coupled to a power supply terminal of the clock transmission circuit to supply the power current, and a control terminal of the first compensation circuit is coupled to the noise amplification circuit to receive the first control signal; An error signal is generated by comparing the power supply voltage with a first reference voltage using an error amplifier circuit of the noise amplifier circuit. A first input terminal of the error amplifier circuit receives the power supply voltage, and a second input terminal of the error amplifier circuit receives the first reference voltage. The error signal is converted into a first control signal by a gain circuit of the noise amplifier circuit. A first input terminal of the gain circuit is coupled to a first output terminal of the error amplifier circuit, a second input terminal of the gain circuit is coupled to a second output terminal of the error amplifier circuit, and a first output terminal of the gain circuit is coupled to the control terminal of the first compensation circuit to supply the first control signal.

18. The operating method as described in claim 17, further comprising: A gain circuit that supplies the power current to the clock transmission circuit by the jitter suppression circuit; The gain circuit amplifies an input clock to generate a boosted clock; the jitter suppression circuit senses power supply noise in the power supply voltage and adaptively adjusts the power supply current to suppress jitter caused by power supply noise in the boosted clock; and a gain circuit and a clock tree circuit of the clock transmission circuit generate the at least one output clock based on the boosted clock, wherein the clock tree circuit is coupled to the gain circuit to receive the boosted clock.

19. The operating method as described in claim 17, wherein the first reference voltage is a bandgap voltage.

20. A method of operating a clock transmission device, comprising: A clock transmission circuit of the clock transmission device generates at least one output clock based on an input clock. A jitter suppression circuit of the clock transmission device supplies a power current to the clock transmission circuit based on a power supply voltage; the jitter suppression circuit adaptively adjusts the power current in response to power supply noise of the power supply voltage to suppress jitter caused by power supply noise of the at least one output clock; a noise amplification circuit of the jitter suppression circuit senses the power supply noise of the power supply voltage to generate a first control signal corresponding to the power supply noise; a first compensation circuit of the jitter suppression circuit adaptively adjusts the power current in response to the first control signal, wherein an input terminal of the first compensation circuit receives the power supply voltage, an output terminal of the first compensation circuit is coupled to a power supply terminal of the clock transmission circuit to supply the power current, and a control terminal of the first compensation circuit is coupled to the noise amplification circuit to receive the first control signal; A first error signal is generated by comparing the power supply voltage with a first reference voltage using a first error amplifier circuit of the noise amplifier circuit. A first input terminal of the first error amplifier circuit receives the power supply voltage, and a second input terminal of the first error amplifier circuit receives the first reference voltage. The first error signal is converted into a first control signal by a first gain circuit of the noise amplifier circuit. A first input terminal of the first gain circuit is coupled to a first output terminal of the first error amplifier circuit, a second input terminal of the first gain circuit is coupled to a second output terminal of the first error amplifier circuit, and an output terminal of the first gain circuit is coupled to the control terminal of the first compensation circuit to supply the first control signal. A second error signal is generated by comparing the power supply voltage with the first reference voltage using a second error amplifier circuit of the noise amplifier circuit. A first input terminal of the second error amplifier circuit receives the power supply voltage, and a second input terminal of the second error amplifier circuit receives the first reference voltage. The second error signal is converted into a second control signal by a second gain circuit of the noise amplifier circuit. A first input terminal of the second gain circuit is coupled to a first output terminal of the second error amplifier circuit, a second input terminal of the second gain circuit is coupled to a second output terminal of the second error amplifier circuit, and an output terminal of the second gain circuit is coupled to a control terminal of a second compensation circuit of the jitter suppression circuit to supply the second control signal. A first terminal of the second compensation circuit receives a second reference voltage, and a second terminal of the second compensation circuit is coupled to a reference terminal of the clock transmission circuit.

Images