Testing structure and testing method for semiconductor device

Abstract

A testing method of a semiconductor device of the present invention includes selecting multiple test elements of a testing structure, and obtaining multiple first electrical characteristic parameters of the selected test elements by a row decoder and a column decoder of the testing structure. Based on the first electrical characteristic parameters, it determines whether each test element is a weak element, and selects the weak elements by the row decoder and the column decoder, and performs an abnormal cause analysis on the selected weak elements. The present invention also provides a testing structure of the semiconductor device.

Description

Technical Field

[0001] This invention relates to a test structure and test method, and more particularly to a test structure and test method for semiconductor devices that can reduce test costs. Prior Technology

[0002] To perform various tests and verifications during semiconductor manufacturing to ensure process quality and performance, test structures, such as test keys or test element groups (TEGs), are typically placed on the wafer dicing channels. Specifically, while each process step is performed to fabricate components in the wafer area, test structures are simultaneously fabricated in the wafer dicing channels. Wafer acceptance testing is then used to measure various parameters of the test structures, serving as indicators of whether the process and components are functioning correctly, thereby effectively controlling product quality.

[0003] Generally, a test structure may include multiple test elements, such as transistors. However, during wafer acceptance testing, limitations in the number of test pads (or probes) and the layout of related measurement metal lines mean that only a portion of the test elements can be tested to roughly locate abnormal areas. With process miniaturization and increased capacity, this can easily lead to inaccurate test results, becoming a bottleneck for yield improvement. To improve test accuracy, more test structures must be set up, thus increasing test costs. Therefore, the testing efficiency of existing test structures and methods still needs improvement to reduce testing costs. Summary of the Invention

[0004] This invention provides a test structure and test method for semiconductor devices, which can improve the problems of low accuracy in locating abnormal areas, inaccurate test results, and low test efficiency in the prior art.

[0005] The semiconductor device testing method of the present invention includes: selecting a plurality of first test elements of the test structure by means of a row decoder and a column decoder of the test structure, and obtaining a plurality of first electrical parameters of the first test elements; determining whether each first test element is a weak element based on the first electrical parameters; and selecting weak elements by means of a row decoder and a column decoder, and performing anomaly cause analysis on the weak elements.

[0006] A test structure for a semiconductor device according to the present invention includes a first part. The first part includes a first test element group, a first pad group, a row decoder, and a column decoder. The first test element group includes a plurality of first test elements. The first pad group includes a plurality of first pads. The row decoder and column decoder are coupled between the first test element group and the first pad group, and are configured to select the first test elements and obtain a plurality of first electrical parameters of the first test elements; wherein the first electrical parameters are used to determine whether each first test element is a weak element, and the row decoder and column decoder select weak elements and perform anomaly cause analysis on the weak elements.

[0007] Based on the above, the test structure and test method of the semiconductor device according to the present invention can improve the accuracy of abnormal area positioning, the accuracy of test results and the test efficiency, thereby improving yield and reducing test costs. Simple Explanation of the Diagram

[0008] Figure 1 is a schematic diagram of a test structure according to an embodiment of the present invention. Figure 2 is a circuit diagram of a test structure according to an embodiment of the present invention. Figure 3 is a schematic diagram of the configuration table of the pad group according to an embodiment of the present invention. Figure 4 is a flowchart of a test method according to an embodiment of the present invention. Figure 5A is a schematic diagram of a first electrical parameter table according to an embodiment of the present invention. Figure 5B is a schematic diagram of the measurement of multiple second electrical parameters according to an embodiment of the present invention. Figure 6 is a schematic diagram of the test structure according to another embodiment of the present invention. Figure 7 is a schematic diagram of the second part of the test structure according to another embodiment of the present invention. Figure 8 is a schematic diagram of the configuration table of the pad group according to another embodiment of the present invention. Figure 9 is a flowchart of a test method according to another embodiment of the present invention. Figure 10 is a schematic diagram of a coarse electrical parameter table according to another embodiment of the present invention. Implementation

[0009] As shown in Figure 1, a test structure 10 according to an embodiment of the present invention can be disposed on the dicing track 12 of wafer 1 and between multiple dies 11. The test structure 10 is configured to perform electrical or functional tests, such as a wafer acceptance test (WAT), to determine whether the quality and reliability of wafer 1 meet the requirements. More specifically, as shown in Figure 2, the test structure 10 according to an embodiment of the present invention includes a pad group 100, a row decoder 101, a column decoder 102, and a test element group (TEG) 103. Therefore, the tests performed on the test structure 10 are not limited by the number of pads and the layout of related measurement metal lines, and can test more test elements than the number of pads, thereby improving the accuracy of abnormal area location, the accuracy of test results, and the testing efficiency, thereby improving yield and reducing testing costs.

[0010] The pad assembly 100 includes x pads PD1~PDx, which are coupled to the row decoder 101, column decoder 102, and TEG 103, and are configured to receive the drive signal VSUP, the row select signal CSEL[n:0], and the column select signal RSEL[m:0]. TEG 103 contains multiple test elements TE. These test elements TE can be arranged in an array. The first terminals (e.g., gates) of these test elements TE are connected via word lines WL1~WL Connected to the line decoder 101, the second end (e.g., the drain) is connected via data lines DL1~DL2. The circuit is connected to column decoder 102, and its third terminal (e.g., source) is commonly connected to pad PD2. A drive signal VSUP can be provided to the test element TE in TEG 103 to provide the operating voltage or other electrical signals required for the test element TE to operate. Row selection signal CSEL[n:0] and column selection signal RSEL[m:0] can be provided to row decoder 101 and column decoder 102 respectively, allowing them to select one of the test elements TE for testing. In this way, by changing the row selection signal CSEL[n:0] and column selection signal RSEL[m:0], the selected test element TE in TEG 103 can be tested, and the electrical parameters of the selected test element TE can be obtained by column decoder 102 or pad PD2. Therefore, the test circuit 10 of this embodiment can obtain test results for a larger number of test elements TE using a smaller number of pads, thus making the test not limited by the number of pads and the layout of related measurement metal lines. In a preferred embodiment, the test circuit 10 can obtain the test results of all test elements TE in TEG103, thereby improving the accuracy of the test results.

[0011] Please refer to Figures 2 and 3 simultaneously. For example, x is 25, m is 8, and n is 8. Specifically, pads PD1 and PD3-PD7 can be used to provide the drive signal VSUP. Pads PD8-16 can be used to provide the column selection signal RSEL[8:0] to select the corresponding column. Pads PD17-25 can be used to provide the row selection signal CSEL[8:0] to select the corresponding row. The drive signal VSUP may include decoder high voltage VINT, low voltage VSS, word line high voltage VPP, word line low voltage VNN, data line high voltage VBL, P-type transistor well voltage VBBsa, and array WA well voltage VBB. In this embodiment, pad PD1 is configured to provide the decoder high voltage VINT to the row decoder 101 and column decoder 102. Pad PD2 is configured to provide the low voltage VSS to the sources of the row decoder 101, column decoder 102, and test element TE. Pad PD3 is configured to provide a word line high voltage VPP to row decoder 101, and pad PD4 is configured to provide a word line low voltage VNN to row decoder 101. Pad PD5 is configured to provide a data line high voltage VBL to column decoder 102. Pads PD6 and PD7 are configured to provide P-type transistor well voltage VBBsa and array WA well voltage VBB to the transistor well area of ​​TEG103, respectively. The electrical parameters of the selected test element TE can be obtained from pads PD8~16 or pad PD2 according to the column select signal RSEL[8:0] and the row select signal CSEL[8:0].

[0012] In this example, column decoder 102 can select one column of TEG103 by decoding the binary column selection signal RSEL[8:0] into a one-hot signal. Similarly, row decoder 101 can select one row of TEG103 by decoding the binary row selection signal CSEL[8:0] into a one-hot signal. In this way, by using the present invention, only 25 pads are needed to select multiple test elements TE from 262,144 test elements for testing to obtain the corresponding electrical parameters.

[0013] The test method of an embodiment of the present invention illustrated in Figure 4 can be applied to the test structure 10 illustrated in Figures 1 and 2. The test method in Figure 4 includes steps S40 to S42.

[0014] In step S40, multiple test elements of the test structure TEG are selected by the row decoder and column decoder of the test structure, and multiple first electrical parameters of the selected test elements are obtained. For example, referring to FIG5A, the test structure 10 can select one of the test elements TE as the selected test element in step S40 through the row selection signal CSEL and the column selection signal RSEL, and obtain its corresponding first electrical parameters. Further, by changing the row selection signal CSEL and the column selection signal RSEL input to the test structure 10, the selected test element TE can be switched sequentially within a predetermined range, and the first electrical parameters of each test element TE within the predetermined range can be obtained. In this example, the test element TE can be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), and the first electrical parameters obtained by the test structure 10 can be, for example, the drain current ID of each transistor. In one embodiment, all test elements TE are selected for testing by row decoder 101 and column decoder 102, and a first electrical parameter table T2 as shown in FIG5A is generated, which records the first electrical parameters of each transistor, such as the drain current ID1,1 to ID512,512.

[0015] In step S41, the test element TE can be determined as a weak element based on the first electrical parameter. Specifically, after obtaining the first electrical parameter of the selected test element TE, the selected test element TE with a first electrical parameter that does not meet the preset condition can be determined as a weak element by comparing the first electrical parameter of each selected test element TE with preset conditions. In some embodiments, the preset condition represents the normal or acceptable range of electrical parameters of the test element, which can be determined based on the measured electrical parameter characteristics or element characteristics. The preset condition can be dynamic or static. For example, a static preset condition can have preset boundary values. The boundary values ​​of a dynamic preset condition can be related to the statistical value of the first electrical parameter (e.g., a group statistical range generated by calculating the mean and standard deviation), and the relatively outlier first electrical parameter can be screened out through the dynamic preset condition. Furthermore, if all the first electrical parameters meet the preset condition, the test is considered passed and ends.

[0016] In step S42, weak components can be selected using row decoder 101 and column decoder 102, and anomaly analysis can be performed on the weak components. Specifically, after determining the address of the weak component through step S41, the weak component can be selected by controlling row decoder 101 and column decoder 102, and the second electrical parameter of the weak component can be obtained. For example, when the test component TE is a MOSFET and the first electrical parameter is the drain current, the four terminal current parameters of the weak component can be obtained in step S42. For example, using row decoder 101 and column decoder 102, the gate current of the weak component can be obtained from pads PD17-25, the source current of the weak component can be obtained from pad PD2, the well current of the weak component can be obtained from pad PD7, and the drain current of the weak component can be obtained from pads PD8-16.

[0017] Please refer to Figure 5B, which illustrates the DC sweep relationship between the four-terminal current and gate voltage of a weak element. Specifically, the four-terminal current parameter curves L51~L54 measured for the weak element correspond to the well current, gate current, source current, and drain current of the weak element, respectively. As shown in Figure 5B, as the gate voltage VG on the horizontal axis changes, curves L51 and L52 corresponding to the well current and gate current of the weak element remain approximately equal. On the other hand, curves L53 and L54 corresponding to the drain current and source current of the weak element saturate at values ​​slightly higher than the gate current as the gate voltage increases, indicating that the weak element may be causing an anomaly. Therefore, the type of anomaly of the weak element can be further determined by the second electrical parameter measured in step S42. In this example, the anomaly of the weak element may be attributed to a short circuit between the drain and source of the weak element. In some embodiments, the second electrical parameter may also be an electrical parameter obtained by directly measuring the weak element, or other electrical parameters obtained through derivation. For example, the second electrical parameter may be, for instance, the transistor's threshold voltage (Vth), on-state current (Ion), and / or off-state current (Ioff), or other suitable electrical parameters.

[0018] Figure 6 is a schematic diagram of a test structure 60 according to another embodiment of the present invention. The test structure 60 can be disposed on the dicing channel 62 and between multiple dies 61. In detail, the test structure 60 may include a first part 60-1 and a second part 60-2. The structure and operation method of the first part 60-1 can be referred to the previous description of the test structure 10, and will not be repeated here. In other words, the first part 60-1 of the test structure 60 includes a pad group 100, a row decoder 101, a column decoder 102, and a TEG 103.

[0019] As shown in Figure 7, the second part 60-2 of the test structure 60 includes a pad group 600 and a TEG 603. The pad group 600 includes pads PD61 to PD6x. It should be noted that the second part 60-2 of the test structure 60 does not have a row decoder 101 and a column decoder 102.

[0020] In one embodiment, the TEG603 of the second part 60-2 of the test structure 60 can be configured to be the same as TEG103, and TEG603 and TEG103 can each be divided into 9 test partitions Blk1 to Blk9. Each test partition Blk1 to Blk9 includes multiple test elements TE. Each end of one of the test elements TE in each test partition Blk1 to Blk9 is directly coupled to one of the pads PD61 to PD6x. According to the test method of this embodiment, the test elements TE directly coupled to the pad group 600 in the multiple test partitions Blk1 to Blk9 of TEG603 can be coarsely tested by the test structure 60. Since TEG603 and TEG103 have the same test elements TE and division, the abnormal test partitions determined by the coarse test results of TEG603 can be used to select the corresponding test partitions of the first part 60-1 for fine testing (i.e., the aforementioned steps S40 to S42). In this way, detailed testing can be performed only on the abnormal test partitions of TEG103, which can reduce the overall testing time and save testing costs.

[0021] Figure 8 shows an example of the configuration table T3 for pad group 600. Referring to both Figures 7 and 8, the aforementioned x is, for example, 25, meaning that pad group 600 can contain 25 pads PD61~PD625. Specifically, pads PD61~PD63 and PD622~PD625 can be used to transmit the coarse test drive signal VSUP', and pads PD64~PD621 can be used to transmit the coarse test electrical parameters or coarse test drive voltages Source1~Source9 and Drain1~Drain9 of the test element TE directly coupled to the pad group 600. The coarse test drive signal VSUP' can include coarse test drive voltages (e.g., data line voltage BL_dummy, word line voltages WL_target1, WL_target2, WL_dummy, well voltages P_well, N_well, and substrate bias Sub) to provide appropriate bias to the data line, word line, transistor well region, or substrate. In the example in Figure 8, each test element TE directly coupled to pad group 600 is assigned at least four pads. For example, the source of the test element TE in test partition Blk1 is configured to be directly coupled to pad PD64 to receive the coarse test drive voltage, and its drain is configured to be directly coupled to pad PD65 to provide drain current to pad PD65 as coarse test electrical parameters. The gate and base of the test element TE in test partition Blk1 are configured to be directly coupled to pads PD62 and PD623, respectively, to receive the coarse test drive voltage.

[0022] In this embodiment, the number of solder pads in the solder pad group 100 of the first part 60-1 of the test structure 60 is less than the number of first electrical parameters obtained, and the number of solder pads in the solder pad group 600 of the second part 60-2 of the test structure 60 is greater than the number of coarse electrical parameters obtained. This reduces the area occupied by the test structure 60, simplifies the layout of the measurement metal lines, and improves testing efficiency.

[0023] Figure 9 illustrates a flowchart of a test method according to another embodiment of the present invention, which can be applied to the test structures 10 and 60 shown in Figures 1 and 2, 6 and 7, and includes steps S90 to S94.

[0024] In detail, in step S90, a coarse test is performed on the test structure including multiple test partitions to obtain coarse electrical parameters for each test partition. Specifically, in one embodiment, a coarse test can be performed on the second part 60-2 of the test structure 60 including multiple test partitions Blk1 to Blk9. The coarse test may include applying a coarse test drive signal VSUP' to the pad group 600, so that the test element TE, whose terminals are all directly coupled to the pad group 600, receives the coarse test drive voltage VSUP', and then simultaneously obtains multiple coarse electrical parameters from these test elements via multiple pads. In another embodiment, a coarse test can be performed on the test structure 10 including multiple test partitions Blk1 to Blk9. The coarse test may include applying a coarse test drive signal (e.g., VSUP) to the pad group 100, so that a portion of the test elements TE from each test partition Blk1 to Blk9 are selected via the row decoder 101 and the column decoder 102, and then multiple coarse electrical parameters are obtained from these selected test elements TE via multiple corresponding pads.

[0025] In step S91, the presence of abnormal test partitions in the test structure is determined based on the coarse electrical parameters. Refer to the coarse electrical parameter table T4 shown in Figure 10, which lists multiple coarse electrical parameters obtained from each test partition. Specifically, the coarse electrical parameters of each test partition are compared with preset conditions. If the coarse electrical parameters do not meet the preset conditions, the corresponding test partition is determined to be an abnormal test partition. In the embodiment shown in Figure 10, the coarse electrical parameter 0.1 μA of test partition Blk6 does not meet the preset conditions; therefore, test partition Blk6 is determined to be an abnormal test partition. If the coarse electrical parameters of all test partitions meet the preset conditions, the test is considered passed and ends.

[0026] In step S92, a detailed test is performed on all test elements of the abnormal test partition to obtain the first electrical parameters of all test elements of the abnormal test partition. Specifically, in one embodiment, test partition Blk6 of TEG603 in the second part 60-2 of test structure 60 is determined to be an abnormal test partition. Since TEG603 is configured to be the same as TEG103, the test elements TE of test partition Blk6 of TEG103 can be sequentially selected and switched through row decoder 101 and column decoder 102 until a detailed test is completed on all test elements TE of test partition Blk6 to obtain the first electrical parameters of all test elements TE of test partition Blk6. In another embodiment, when test partition Blk6 of test structure 10 is determined to be an abnormal test partition, the test elements TE of test partition Blk6 of TEG103 can be sequentially selected and switched through row decoder 101 and column decoder 102 until a detailed test is completed on all test elements TE of test partition Blk6 to obtain the first electrical parameters of all test elements TE of test partition Blk6. In one embodiment, both the first electrical parameter and the coarse electrical parameter may be the drain current.

[0027] In step S93, the test element TE can be determined as a weak element based on the first electrical parameter. The details of step S93 are the same as those of step S41, and therefore will not be repeated here.

[0028] In step S94, weak components can be selected by the row decoder and column decoder, and anomaly cause analysis can be performed on the weak components. The details of step S94 are the same as those of step S42, and therefore will not be repeated here.

[0029] In summary, the test structure and test method for the semiconductor device according to the present invention can improve the accuracy of abnormal area positioning, the accuracy of test results and the test efficiency, thereby improving yield and reducing test costs.

[0030] The semiconductor device of this invention can be any integrated circuit, including but not limited to any integrated circuit comprising a metal-oxide-semiconductor field-effect transistor, such as dynamic random-access memory (DRAM), flash memory, or variable-resistance memory. Furthermore, for three-dimensionally stacked integrated circuits, the test structure and test method of this invention can significantly improve yield and reduce test costs.

[0031] This invention is applicable to the fabrication of miniaturized semiconductor devices to increase the total number of dies on a wafer. Furthermore, the test structure and method for the semiconductor device according to this invention facilitate reducing the number of test structures or TEGs required while miniaturizing processes and increasing capacity and / or bandwidth, thereby reducing process materials and testing costs. Therefore, this invention can reduce the production cost and energy consumption of individual ICs, as well as the energy consumption of subsequent packaging, thereby reducing carbon emissions during semiconductor device manufacturing. Moreover, since the yield of the semiconductor device of this invention is improved, this invention provides a green semiconductor technology.

[0032] 1, 6: Wafer 10, 60, 60-1, 60-2: Test Structure 11, 61: Grain 12, 62: Cutting track 100, 600: Pad set 101: Line Decoder 102: Column Decoder 103, 603:TEG Blk1~Blk9: Test partitions CSEL[n:0], RSEL[m:0], VSUP: signal DL1~DLm, WL1~WLn: Lines ID1,1~ID512,512: Drain current PD1~PDx, PD61~PD6x: solder pads T2~T4: Table TE: Test Element BL_dummy, Drain1~Drain9, N_well, P_well, Source1~Source9, Sub, VBB, VBBsa, VBL, VINT, VNN, VPP, VSS, WL_dummy, WL_target1, WL_target2: voltage S40~S42, S90~S94: Steps VSUP: Signal / Voltage

Claims

1. A method for testing a semiconductor device, comprising: A test structure is provided, comprising: a first part, including: a first test element group, including a plurality of first test elements; a first pad group, including a plurality of first pads; and a row decoder and a column decoder, coupled between the first test element group and the first pad group; selecting the first test elements by the row decoder and the column decoder, and obtaining a plurality of first electrical parameters of the first test elements, wherein the number of the first pads is less than the number of the obtained first electrical parameters; determining whether each of the first test elements is a weak element based on the first electrical parameters; and selecting the weak element by the row decoder and the column decoder, and performing an anomaly cause analysis on the weak element.

2. A method for testing a semiconductor device as claimed in claim 1, wherein selecting the first test elements of the test structure by means of the row decoder and the column decoder of the test structure, and obtaining the first electrical parameters of the first test elements, includes: The test structure receives a row selection signal and a column selection signal through the first pads, and provides the row selection signal and the column selection signal to the row decoder and the column decoder respectively, so as to control the row decoder and the column decoder to select one of the first test elements for testing and obtain the first electrical parameter of the first test element; and by changing the row selection signal and the column selection signal, the first electrical parameter of each of the first test elements within a predetermined range is obtained.

3. The test method for the semiconductor device as claimed in claim 1, wherein each of the first electrical parameters is a drain current.

4. The method for testing a semiconductor device as claimed in claim 1, wherein determining whether each of the first test elements is the weak element based on the first electrical parameters includes: The first electrical parameters are compared with a preset condition to determine the first test element that has the first electrical parameters that do not meet the preset condition as the weak element.

5. A method for testing a semiconductor device as claimed in claim 1, wherein selecting the weak element by means of the row decoder and the column decoder, and performing the anomaly cause analysis on the weak element, includes: The weak element is selected by the row decoder and the column decoder, and a second electrical parameter of the weak element is obtained; And determine whether the second electrical parameter changes with a gate voltage in order to determine the type of abnormality of the weak component.

6. A method for testing a semiconductor device as claimed in claim 5, wherein obtaining the second electrical parameter of the weak element comprises: A gate current of the weak element is obtained from one of the corresponding first pads coupled to the decoder of that row; A drain current of the weak element is obtained from a corresponding one of the first pads coupled to the decoder; a source current of the weak element is obtained from a corresponding one of the first pads coupled to the source of the weak element; and a well current of the weak element is obtained from a corresponding one of the first pads coupled to the well region of the weak element.

7. The test method for the semiconductor device as described in claim 1, further comprising: A coarse test is performed on the test structure, which includes multiple test partitions, to obtain a coarse electrical parameter for each test partition; and the coarse electrical parameter is used to determine whether an abnormal test partition exists in the test structure; wherein, the first test elements of the test structure are selected by the row decoder and the column decoder of the test structure, and the first electrical parameters of the first test elements are obtained, including: a fine test is performed on all the first test elements of the abnormal test partition to obtain the first electrical parameters of all the first test elements of the abnormal test partition.

8. A test method for a semiconductor device as described in claim 7, wherein: The test structure further includes: a second part, comprising: a second test element group, including multiple second test elements; a second pad group, including multiple second pads, wherein each end of each of the second test elements is directly coupled to one of the second pads; the coarse test includes applying a coarse test drive signal to the second pad group, causing the second test elements to receive the coarse test drive voltage, and then simultaneously acquiring multiple coarse electrical parameters of the test partitions from the second test elements via the second pad group; determining whether the test structure has an abnormal test partition based on the coarse electrical parameters includes comparing the coarse electrical parameters of each test partition with a preset condition; when the coarse electrical parameters do not meet the preset condition, the corresponding one of the test partitions is determined to be an abnormal test partition; wherein the row decoder and column decoder of the test structure select the first test elements of the test structure and obtain the first electrical parameters of the first test elements, including: By using the row decoder and column decoder of the test structure, the first test elements in the test structure that correspond to the abnormal test partition where the second test elements are located are selected.

9. A test structure for a semiconductor device, comprising: A first part includes: a first test element group including a plurality of first test elements; a first pad group including a plurality of first pads; and a row decoder and a column decoder coupled between the first test element group and the first pad group, configured to select the first test elements and obtain a plurality of first electrical parameters of the first test elements, wherein the number of the first pads is less than the number of the obtained first electrical parameters; wherein each first test element is determined to be a weak element based on the first electrical parameters, and the weak element is selected by the row decoder and the column decoder, and an anomaly cause analysis is performed on the weak element.

10. The test structure of the semiconductor device as claimed in claim 9, wherein the row decoder and the column decoder receive a row selection signal and a column selection signal respectively via the first pad group, and obtain the first electrical parameter of each of the first test elements within a predetermined range by transforming the row selection signal and the column selection signal.

11. The test structure of the semiconductor device as claimed in claim 9, wherein the first electrical parameters are compared with a preset condition to determine the first test element having the first electrical parameters that do not meet the preset condition as the weak element.

12. The test structure of the semiconductor device as claimed in claim 9, wherein the weak element is selected by the row decoder and the column decoder, and a second electrical parameter of the weak element is obtained, and it is determined whether the second electrical parameter changes with a gate voltage, so as to determine the type of anomaly of the weak element.

13. A test structure for a semiconductor device as claimed in claim 12, wherein the second electrical parameter includes: A gate current of the weak element obtained from the first pads coupled to one of the row decoders, a drain current of the weak element obtained from the first pads coupled to one of the column decoders, a source current of the weak element obtained from the first pads coupled to one of the source terminals of the weak element, and a well current of the weak element obtained from the first pads coupled to one of the well terminals of the weak element.

14. The test structure for the semiconductor device as described in claim 9, further comprising: A second part includes: a second group of test elements, including a plurality of second test elements; a second group of pads, including a plurality of second pads, wherein each end of each of the second test elements is directly coupled to one of the second pads.

15. A test structure for a semiconductor device as claimed in claim 14, wherein the first group of test elements has a plurality of first test partitions, the second group of test elements is configured to be the same as the first group of test elements and has a plurality of second test partitions, each end of one of the second test elements in each of the second test partitions being directly coupled to one of the second pads.

16. A test structure for a semiconductor device as claimed in claim 15, wherein a coarse test is performed on each of the second test elements to obtain a coarse electrical parameter of each of the second test partitions, the coarse electrical parameter is used to determine whether an abnormal test partition exists in the test structure, and a fine test is performed on all of the first test elements corresponding to the abnormal test partition to obtain the first electrical parameters of all of the first test elements of the abnormal test partition.

17. The test structure of the semiconductor device as claimed in claim 16, wherein the number of the second pads is greater than the number of the coarse electrical parameters obtained.

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