Buffer output device having feedthrough cancellation mechanism and buffer output method thereof

Abstract

A buffer output device includes a buffer circuit, first switches, and a feedthrough cancellation circuit. The first switches are configured to be turned on according to a first clock signal, to provide a first input signal to a first input node of the buffer circuit and to provide a second input signal to a second input node of the buffer circuit. The buffer circuit is configured to generate a first output signal from a first output node according to the first input signal, and to generate a second output signal from a second output node according to the second input signal. The feedthrough cancellation circuit is configured to be turned on according to a second clock signal when the first switches are not turned on, to couple the second output node to the first input node and to couple the first output node to the second input node.

Description

Technical Field

[0001] This case concerns buffered output devices, particularly buffered output devices with feedthrough elimination mechanisms and their buffered output methods. Prior Technology

[0002] In the sampling circuit, when the sampling switch is not turned on, the input signal may still be misrepresented to the output node via the sampling switch and parasitic components in the subsequent circuit, thus affecting the signal level at the output node. This will reduce the signal accuracy at the output node and decrease the accuracy of subsequent signal processing. Summary of the Invention

[0003] In some embodiments, one of the objectives of this invention is (but not limited to) to provide a buffered output device and its buffered output method with a feedthrough elimination mechanism to improve the shortcomings of the prior art.

[0004] In some embodiments, the buffered output device includes a buffer circuit, a plurality of first switches, and a feedthrough cancellation circuit. The plurality of first switches are turned on according to a first clock signal to provide a first input signal to a first input node of the buffer circuit and a second input signal to a second input node of the buffer circuit. The buffer circuit is used to generate a first output signal from a first output node according to the first input signal and to generate a second output signal from a second output node according to the second input signal. The feedthrough cancellation circuit is turned on according to a second clock signal when the plurality of first switches are not turned on, to couple the second output node to the first input node and vice versa.

[0005] In some embodiments, the buffered output method includes: turning on a plurality of first switches according to a first clock signal to provide a first input signal to a first input node of a buffer circuit and providing a second input signal to a second input node of the buffer circuit; generating a first output signal from a first output node and a second output signal from a second output node by the buffer circuit according to the first input signal and the second input signal; and turning on a feedthrough cancellation circuit when the plurality of first switches are not turned on according to a second clock signal to couple the second output node to the first input node and the first output node to the second input node via the feedthrough cancellation circuit.

[0006] Regarding the features, implementation, and effects of this case, the preferred embodiments are described in detail below with reference to the drawings. Simple Explanation of the Diagram

[0007] [Figure 1] is a schematic diagram of a buffered output device according to some embodiments of this case; [Figure 2] is a schematic diagram of a buffered output device according to some embodiments of this case; [Figure 3] is a waveform diagram of the first clock signal and the second clock signal in Figure 1 or Figure 2, drawn according to some embodiments of this case; [Figure 4] is a schematic diagram of the buffer circuit in Figure 1 or Figure 2 according to some embodiments of this case; and [Figure 5] is a flowchart of a buffered output method according to some embodiments of this case. Implementation

[0008] All terms used herein have their common meanings. The definitions of the terms mentioned above in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not limit the scope or meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0009] As used herein, "coupling" or "connection" can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or moving together. As used herein, the term "circuit" can refer to a device in which at least one transistor and / or at least one active or passive component are connected in a certain manner to process signals.

[0010] As used herein, the term "and / or" includes any combination of one or more of the listed related items. In this document, the terms first, second, third, etc., are used to describe and distinguish individual elements. Therefore, a first element in this document may also be referred to as a second element without departing from the intent of this case. For ease of understanding, similar elements in the various diagrams will be assigned the same reference numerals.

[0011] Figure 1 is a schematic diagram of a buffered output device 100 according to some embodiments of the present invention. In some embodiments, the buffered output device 100 may be applied to a sampling circuit, but this invention is not limited thereto. The buffered output device 100 includes a switch 101, a switch 103, a buffer circuit 110, and a feedthrough cancellation circuit 120.

[0012] Switches 101 and 103 are turned on according to the clock signal CK1 to provide an input signal VIN to input node NI1 (e.g., corresponding to the negative input terminal) of buffer circuit 110, and to provide an input signal VIP to input node NI2 (e.g., corresponding to the positive input terminal) of buffer circuit 110. Buffer circuit 110 generates an output signal VON from output node NO1 (e.g., corresponding to the negative output terminal) according to the input signal VIN, and generates an output signal VOP from output node NO2 (e.g., corresponding to the positive output terminal) according to the input signal VIP. In some embodiments, buffer circuit 110 may be an analog buffer circuit. For example, buffer circuit 110 may be implemented by, but is not limited to, several source followers. The relevant configuration will be described later with reference to FIG4.

[0013] The feedthrough cancellation circuit 120 is activated according to the clock signal CK2 when switches 101 and 103 are not activated, to couple output node NO2 to input node NI1 and output node NO1 to input node NI2. Conversely, the feedthrough cancellation circuit 120 is also deactivated according to the clock signal CK2 when switches 101 and 103 are activated, to disconnect output node NO2 from input node NI1 and output node NO1 from input node NI2. In other words, when switches 101 and 103 are activated according to the clock signal CK1 to provide input signals VIN and VIP to the buffer circuit 110, the feedthrough cancellation circuit 120 is deactivated according to the clock signal CK2 to avoid affecting the operation of the buffer circuit 110. When switches 101 and 103 are not turned on according to clock signal CK1, feedthrough cancellation circuit 120 is turned on according to clock signal CK2 to perform feedthrough cancellation (that is, output node NO2 is coupled to input node NI1 and output node NO1 is coupled to input node NI2).

[0014] In detail, the feedthrough cancellation circuit 120 may include paths 122 and 124. Path 122 is coupled between output node NO2 and input node NI1, and path 124 is coupled between output node NO1 and input node NI2. In some embodiments, paths 122 and 124 may have the same circuit structure. Taking path 122 as an example, path 122 includes a switch SW1 and a capacitor C1. Capacitor C1 is coupled to output node NO2, and switch SW1 is coupled between input node NI1 and capacitor C1. Switch SW1 is turned on according to clock signal CK2 to couple input node NI1 to output node NO2 via capacitor C1. Similarly, path 124 includes a switch SW2 and a capacitor C2. Capacitor C2 is coupled to output node NO1, and switch SW2 is coupled between input node NI2 and capacitor C2. Switch SW2 is turned on according to clock signal CK2 to couple input node NI2 to output node NO1 via capacitor C2.

[0015] In some embodiments, the input signals VIN and VIP can be differential signals. Ideally, when switches 101 and 103 are not conducting, the input signals VIN and VIP are not provided to the input nodes NI1 and NI2 of the buffer circuit 110. However, in practical applications, due to the presence of parasitic elements in switches 101, 103, and the internal transistors of the buffer circuit 110, the input signals VIN and VIP may still be fed through (i.e. coupled) to the output nodes NO1 and NO2 via switches 101, 103, and the aforementioned parasitic elements of the internal transistors during the period when switches 101 and 103 are not conducting, thereby reducing the output accuracy of the buffer circuit 110. To improve the above problems, the feedthrough cancellation circuit 120 can couple the input node NI1 to the output node NO2 and the input node NI2 to the output node NO1 during the period when the switches 101 and 103 are not conducting, thereby using the characteristics of the differential signal to reduce the influence of the aforementioned signal feedthrough.

[0016] Figure 2 is a schematic diagram of a buffered output device 200 according to some embodiments of this invention. Unlike the buffered output device 100 of Figure 1, in this example, capacitor C1 is coupled to input node NI1, and switch SW1 is coupled between output node NO2 and capacitor C1, and is used to conduct according to clock signal CK2 to couple output node NO2 to input node NI1 via capacitor C1. Similarly, capacitor C2 is coupled to input node NI2, and switch SW2 is coupled between output node NO1 and capacitor C2, and is used to conduct according to clock signal CK2 to couple output node NO1 to input node NI2 via capacitor C2.

[0017] Figure 3 is a waveform diagram of clock signals CK1 and CK2 in Figure 1 or Figure 2, drawn according to some embodiments of this invention. As shown in Figure 3, switches 101 and 103 can be turned on during period T1 when clock signal CK1 has a high level, and not turned on during period T2 when clock signal CK1 has a low level. Correspondingly, switches SW1 and SW2 can be configured to be turned on during the aforementioned period T2. In some embodiments, as shown in waveform W1, clock signal CK2 and clock signal CK1 can have opposite phases. That is, when clock signal CK1 has a high level, clock signal CK2 has a low level; and vice versa. In other embodiments, as shown in waveform W2, clock signals CK1 and CK2 can be set as non-overlapping clock signals, meaning there is a time difference between the falling edge of clock signal CK1 and the rising edge of clock signal CK2, and the same time difference exists between the rising edge of clock signal CK1 and the falling edge of clock signal CK2. With the above waveform setting, the period during which the feedthrough cancellation circuit 120 is turned on (e.g., period T2 or period T3) can at least partially overlap with the period T2 during which switches 101 and 103 are not turned on. Thus, the feedthrough cancellation circuit 120 can turn on during the period T2 when switches 101 and 103 are not turned on to perform feedthrough cancellation, and can turn off during the period T1 when switches 101 and 103 are turned on to reduce the impact on the buffer circuit 110.

[0018] In some embodiments, clock signal CK1 and / or clock signal CK2 may have a duty cycle of approximately 50%, but this invention is not limited thereto. Clock signals CK1 and / or clock signal CK2 with various duty cycle values ​​are all within the scope of this invention.

[0019] Figure 4 is a schematic diagram of the buffer circuit 110 in Figure 1 or Figure 2 according to some embodiments of this invention. As previously described, the buffer circuit 110 can be implemented by several source followers. For example, the buffer circuit 110 may include source followers 410 and 420. Source follower 410 includes transistor MN1 and transistor MP1. A first terminal (e.g., a drain) of transistor MN1 receives a power supply voltage VDD, a second terminal (e.g., a source) of transistor MN1 is coupled to the first terminal (e.g., a source) of transistor MP1 to output node NO1 to generate an output signal VON, and a control terminal (e.g., a gate) of transistor MN1 is coupled to the control terminal (e.g., a gate) of transistor MP1 to input node NI1 to receive an input signal VIN. A second terminal (e.g., a drain) of transistor MP1 is coupled to ground. With the above configuration, source follower 410 can generate an output signal VON according to the input signal VIN.

[0020] Similarly, source follower 420 includes transistor MN2 and transistor MP2. The first terminal of transistor MN2 receives the power supply voltage VDD. The second terminal of transistor MN2 is coupled to the first terminal of transistor MP2 to output node NO2 to generate the output signal VOP. The control terminals of transistor MN2 and MP2 are coupled to input node NI2 to receive the input signal VIP. The second terminal of transistor MP2 is coupled to ground. With this configuration, source follower 420 can generate the output signal VOP based on the input signal VIP.

[0021] When switch 101 in Figure 1 is not turned on, the input signal VIN may be coupled to output node NO1 via the parasitic capacitance of switch 101, the parasitic capacitance of transistor MN1 (e.g., gate-source capacitance), and the parasitic capacitance of transistor MP1 (e.g., gate-source capacitance). Therefore, when switch 101 is not turned on, switch SW2 in path 124 can be turned on to connect input node NI2 to output node NO1, thereby reducing the impact of signal feedthrough. Similarly, when switch 103 in Figure 1 is not turned on, the input signal VIP may be coupled to output node NO2 via the parasitic capacitance of switch 103, the parasitic capacitance of transistor MN2 (e.g., gate-source capacitance), and the parasitic capacitance of transistor MP2 (e.g., gate-source capacitance). Therefore, when switch 103 is not turned on, switch SW1 in path 122 can be turned on to connect input node NI1 to output node NO2, thereby reducing the impact of the aforementioned signal feedthrough.

[0022] The configuration of the buffer circuit 110 shown in Figure 4 is for illustrative purposes only and is not intended to limit the scope of this invention. In other embodiments, other circuits may be added to the buffer circuit 110 in Figure 4 according to actual application requirements, such as, but not limited to, AC coupling circuits and DC bias circuits. Therefore, all types of buffer circuits 110 are within the scope of this invention.

[0023] Figure 5 is a flowchart illustrating a buffered output method 500 according to some embodiments of this invention. In different embodiments, the buffered output method 500 may be executed by either the buffered output device 100 of Figure 1 or the buffered output device 200 of Figure 2, but this invention is not limited thereto.

[0024] In operation S510, a plurality of first switches are turned on according to a first clock signal to provide a first input signal to a first input node of a buffer circuit and a second input signal to a second input node of the buffer circuit. In operation S520, the buffer circuit generates a first output signal from a first output node and a second output signal from a second output node according to the first input signal and the second input signal. In operation S530, a feedthrough cancellation circuit is turned on when the plurality of first switches are not turned on according to a second clock signal to couple the second output node to the first input node and the first output node to the second input node.

[0025] The relevant operations of the buffered output method 500 can be referred to the descriptions of the foregoing embodiments, and therefore will not be repeated here. The multiple operations in the buffered output method 500 are merely examples and are not limited to being executed in the order shown in these examples. Without departing from the operation mode and scope of the embodiments of this application, the relevant operations in the buffered output method 500 may be appropriately added, replaced, omitted, or executed in a different order. Alternatively, the relevant operations in the above figures may be executed simultaneously or partially simultaneously.

[0026] In summary, the buffer circuits and buffer output methods provided in some embodiments of this case can use feedthrough cancellation circuits to reduce the influence of parasitic elements, and use additional switching mechanisms to prevent the feedthrough cancellation circuits from affecting the main operation of the buffer circuits.

[0027] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the express or implied content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification.

[0028] 100, 200: Buffered output device 101, 103: Switches 110: Buffer circuit 120: Feedthrough cancellation circuit 122,124: Path 410, 420: Source Follower 500: Buffered Output Method C1, C2: Capacitors CK1, CK2: Clock signals MN1,MN2,MP1,MP2: Transistors NI1, NI2: Input nodes NO1, NO2: Output nodes S510, S520, S530: Operation SW1, SW2: Switches T1, T2, T3: Periods VDD: Power supply voltage VIN, VIP: Enter signal VON, VOP: Output signal W1, W2: waveform

Claims

1. A buffered output device, comprising: a buffer circuit; a plurality of first switches configured to be turned on according to a first clock signal to provide a first input signal to a first input node of the buffer circuit and to provide a second input signal to a second input node of the buffer circuit, wherein the buffer circuit is configured to generate a first output signal from a first output node according to the first input signal and to generate a second output signal from a second output node according to the second input signal; and a feedthrough cancellation circuit configured to be turned on according to a second clock signal when the plurality of first switches are not turned on, to couple the second output node to the first input node and to the second input node, wherein... The period during which the feedthrough cancellation circuit is turned on at least partially overlaps with the period during which the plurality of first switches are not turned on, or the first clock signal and the second clock signal have opposite phases.

2. The buffered output device of claim 1, wherein the feedthrough cancellation circuit is configured to de-conduct when the plurality of first switches are turned on according to the second clock signal, so as not to connect the second output node to the first input node and not to connect the first output node to the second input node.

3. The buffered output device of claim 1, wherein the feedthrough cancellation circuit comprises: a capacitor coupled to the second output node; and a second switch coupled between the first input node and the capacitor, and configured to be turned on according to the second clock signal to couple the first input node to the second output node via the capacitor.

4. The buffered output device of claim 1, wherein the feedthrough cancellation circuit comprises: a capacitor coupled to the first input node; and a second switch coupled between the second output node and the capacitor, and configured to be turned on according to the second clock signal to couple the second output node to the first input node via the capacitor.

5. The buffered output device of claim 1, wherein the buffer circuit comprises: a first source follower for generating the first output signal based on the first input signal; and a second source follower for generating the second output signal based on the second input signal.

6. The buffered output device of claim 1, wherein the first clock signal and the second clock signal are non-overlapping clock signals when the period during which the feedthrough cancellation circuit is turned on at least partially overlaps with the period during which the plurality of first switches are not turned on.

7. A buffered output method, comprising: activating a plurality of first switches according to a first clock signal to provide a first input signal to a first input node of a buffer circuit and providing a second input signal to a second input node of the buffer circuit; generating a first output signal from a first output node and a second output signal from a second output node by the buffer circuit according to the first input signal and the second input signal; and activating a feedthrough cancellation circuit when the plurality of first switches are not activated according to a second clock signal, to couple the second output node to the first input node and the first output node to the second input node via the feedthrough cancellation circuit, wherein... The period during which the feedthrough cancellation circuit is turned on at least partially overlaps with the period during which the plurality of first switches are not turned on, or the first clock signal and the second clock signal have opposite phases.

8. The buffered output method of claim 7 further includes: disabling the feedthrough cancellation circuit when the plurality of first switches are turned on according to the second clock signal, so as not connecting the second output node to the first input node and not connecting the first output node to the second input node.

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